NSC TMS426409A

TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
D
D
D
D
D
D
D
D
D
DJ/DGA PACKAGES
( TOP VIEW )
This data sheet is applicable to all
TMS41x409As and TMS42x409As symbolized
by Revision “B”, Revision “E”, and subsequent
revisions as described in the device
symbolization section.
Organization . . . 4 194 304 × 4
Single Power Supply (5 V or 3.3 V)
Performance Ranges:
’41x409A-50
’41x409A-60
’41x409A-70
’42x409A-50
’42x409A-60
’42x409A-70
ACCESS ACCESS ACCESS
TIME
TIME
TIME
tRAC
tCAC
tAA
MAX
MAX
MAX
50 ns
13 ns
25 ns
60 ns
15 ns
30 ns
70 ns
18 ns
35 ns
50 ns
13 ns
25 ns
60 ns
15 ns
30 ns
70 ns
18 ns
35 ns
EDO
CYCLE
tHPC
MIN
20 ns
25 ns
30 ns
20 ns
25 ns
30 ns
Extended-Data-Out (EDO) Operation
CAS-Before-RAS ( CBR) Refresh
Low Power Dissipation
3-State Unlatched Output
High-Reliability Plastic 24 / 26-Lead
300-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package (DJ Suffix) and
24/26-Lead 300-Mil-Wide Surface-Mount
Thin Small-Outline Package (TSOP)
(DGA Suffix)
Operating Free-Air Temperature Range
0°C to 70°C
VCC
DQ1
DQ2
W
RAS
A11†
1
26
2
3
4
5
25
24
23
22
6
21
A10
A0
A1
A2
A3
VCC
8
19
9
10
18
17
11
12
13
16
15
14
VSS
DQ4
DQ3
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
PIN NOMENCLATURE
A0 – A11†
DQ1 – DQ4
CAS
NC
OE
RAS
VCC
VSS
W
Address Inputs
Data In / Data Out
Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
5-V or 3.3-V Supply‡
Ground
Write Enable
† A11 is NC for TMS417409A and TMS427409A.
‡ See Available Options Table
AVAILABLE OPTIONS
POWER
SUPPLY
SELF
REFRESH,
BATTERY
BACKUP
TMS416409A
5V
–
4 096 in 64 ms
TMS417409A
5V
–
2 048 in 32 ms
TMS426409A
3.3 V
–
4 096 in 64 ms
TMS427409A
3.3 V
–
2 048 in 32 ms
description
DEVICE
The TMS41x409A and TMS42x409A series are
16 777 216-bit dynamic random-access memory
(DRAM) devices organized as 4 194 304 words of
four bits each.
These devices feature maximum RAS access
times of 50, 60, and 70 ns. All address and data-in
lines are latched on chip to simplify system
design. Data out is unlatched to allow greater
system flexibility.
REFRESH
CYCLES
The TMS416409A and TMS417409A are offered in a 24 / 26-lead plastic surface-mount SOJ package
(DJ suffix). The TMS426409A and TMS427409A are offered in a 24/26-lead plastic surface-mount SOJ
package (DJ suffix) and a 24 / 26-lead plastic surface-mount TSOP (DGA suffix). These packages are designed
for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
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1
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
logic symbol (TMS416409A and TMS426409A)†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
RAS
CAS
W
OE
DQ1
DQ2
DQ3
DQ4
9
10
11
12
RAM 4096 K × 4
20D10/21D0
15
16
17
18
19
21
8
6
5
23
4
22
2
3
24
25
A
0
4 194 303
20D19/21D9
20D20
20D21
C20 [ROW]
G23/[REFRESH ROW]
24 [PWR DWN]
C21[COLUMN]
G24
&
23,21D
G25
A,22D
26
23C22
24,25 EN
A,Z26
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
2
POST OFFICE BOX 1443
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
logic symbol (TMS417409A and TMS427409A)†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RAS
CAS
W
OE
DQ1
DQ2
DQ3
DQ4
9
10
11
12
RAM 4096 K × 4
20D11/21D0
15
16
17
18
A
0
4 194 303
19
21
8
5
23
4
22
2
3
24
25
20D21/21D10
C20 [ROW]
G23/[REFRESH ROW]
24 [PWR DWN]
C21[COLUMN]
G24
&
23,21D
G25
A,22D
26
23C22
24,25 EN
A,Z26
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
3
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
functional block diagram
TMS416409A, TMS426409A
RAS
CAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
ColumnAddress
Buffers†
A11
RowAddress
Buffers
DataIn
Reg.
256K Array
4
D
e
c
o
d
e
12
4
256K Array
R
o
w
I/O
Buffers
64
4
4
DataOut
Reg.
256K Array
DQ1 – DQ4
12
† Column addresses A10 and A11 are not used.
TMS417409A, TMS427409A
RAS
CAS
W
OE
Timing and Control
A0
A1
11
Column Decode
Sense Amplifiers
ColumnAddress
Buffers
A10
32
RowAddress
Buffers
4
256K Array R 256K Array
256K Array o 256K Array
w
11
D
e
c
o
d
256K Array e 256K Array
4
32
11
4
POST OFFICE BOX 1443
DataIn
Reg.
• HOUSTON, TEXAS 77251–1443
I/O
Buffers
4
4
DataOut
Reg.
DQ1 – DQ4
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
operation
extended data out
Extended data out (EDO) allows data output rates of up to 50 MHz for 50-ns devices. When keeping the same
row address while selecting random column addresses, the time for row-address setup and hold and for address
multiplex is eliminated. The maximum number of columns that can be accessed is determined by tRASP , the
maximum RAS low time.
Extended data out does not place the data in / data out pins (DQ pins) into the high-impedance state with the
rising edge of CAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM
decodes the next address. OE and W can control the output impedance. Descriptions of OE and W further
explain EDO operation benefit.
address: A0 – A11 ( TMS416409A and TMS426409A) and A0 – A10 (TMS417409A and TMS427409A)
Twenty-two address bits are required to decode each of the 4 194 304 storage cell locations. For the
TMS416409A and TMS426409A,12 row-address bits are set up on A0 through A11 and latched onto the chip
by the row-address strobe (RAS). Ten column-address bits are set up on A0 through A9. For the TMS417409A
and TMS427409A, 11 row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS.
Eleven column-address bits are set up on A0 through A10. All addresses must be stable on or before the falling
edge of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the
row decoder. CAS is used as a chip select, activating the output buffers and latching the address bits into the
column-address buffers.
output enable (OE)
OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance (see Figure 8). There are two
methods for placing the DQs into the high-impedance state and maintaining that state during CAS high time.
The first method is to transition OE high before CAS transitions high and keep OE high for tCHO (hold time, OE
from CAS) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS
falls again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a
minimum of tOEP (precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further
transitions on OE until CAS falls again (see Figure 8).
write enable ( W)
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled so long as CAS is high
(see Figure 9).
data in / data out (DQ1 – DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the later falling
edge of CAS or W strobes data into the on-chip data latch with setup and hold times referenced to the later edge.
The DQs drive valid data after all access times are met and remain valid except in cases described in the W
and OE sections.
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
RAS-only refresh
TMS416409A, TMS426409A
A refresh operation must be performed at least once every 64 ms to retain data. This can be achieved by strobing
each of the 4 096 rows (A0 – A11). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh.
TMS417409A, TMS427409A
A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing
each of the 2 048 rows (A0 – A10). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh.
hidden refresh
A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by
holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a
RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally.
CAS-before-RAS ( CBR) refresh
CBR refresh is performed by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after
RAS falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS.
The external address is ignored, and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh
( RAS-only or CBR ) cycle.
test mode
The test mode (see Figure 1) is initiated with a CBR-refresh cycle while simultaneously holding the W input low.
The entry cycle performs an internal refresh cycle while internally setting the device to perform parallel read or
write on subsequent cycles. While in the test mode, any data sequence can be performed. The device exits test
mode if a CBR refresh cycle with W held high or a RAS-only refresh cycle is performed.
In the test mode, the device is configured as 1024K bits × 4 bits for each DQ. Each DQ pin has a separate 4-bit
parallel read and write data bus that ignores column addresses A0 and A1. During a read cycle, the four internal
bits are compared for each DQ pin. If the four bits agree, DQ goes high; if not, DQ goes low. Test time is reduced
by a factor of four for this series.
6
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
test mode (continued)
Exit Cycle
Entry Cycle
Test Mode Cycle
Normal
Mode
RAS
CAS
W
NOTE A: The states of W, data in, and address are defined by the type of cycle used during test mode.
Figure 1. Test-Mode Cycle
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7
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (TMS41x409A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Supply voltage range, VCC (TMS42x409A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range on any pin (TMS41x409A) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on any pin (TMS42x409A) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
TMS41x409A
TMS42x409A
MIN
NOM
MAX
MIN
NOM
4.5
5
5.5
3
3.3
VCC
VSS
Supply voltage
VIH
VIL
High-level input voltage
2.4
6.5
2
Low-level input voltage (see Note 2)
–1
0.8
– 0.3
Supply voltage
0
MAX
UNIT
3.6
V
0
V
VCC + 0.3
0.8
V
V
TA
Operating free-air temperature
0
70
0
70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
8
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TMS416409A
PARAMETER
TEST CONDITIONS†
VOH
High-level output
voltage
VOL
Low-level output voltage
II
Input current (leakage)
IO
Output current
(leakage)
VCC = 5.5 V,
CAS high
ICC1‡§
Average read- or
write-cycle current
VCC = 5.5 V,
ICC2
Average
g standby
y
current
IOH = – 5 mA
’416409A - 50
MIN
’416409A - 60
MAX
2.4
IOL = 4.2 mA
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
MIN
MAX
2.4
’416409 A- 70
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
± 10
± 10
± 10
µA
VO = 0 V to VCC,
± 10
± 10
± 10
µA
Minimum cycle
100
80
70
mA
VIH = 2.4 V ( TTL),
After one memory cycle,
RAS and CAS high
2
2
2
mA
VIH = VCC – 0.2 V (CMOS),
After one memory cycle,
RAS and CAS high
1
1
1
mA
ICC3‡§
Average refresh current
(RAS-only refresh or
CBR)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
100
80
70
mA
ICC4‡¶
Average EDO current
VCC = 5.5 V,
RAS low,
100
90
80
mA
tHPC = MIN,
CAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
POST OFFICE BOX 1443
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9
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS417409A
PARAMETER
TEST CONDITIONS†
VOH
High-level output
voltage
VOL
Low-level output voltage
II
Input current (leakage)
IO
Output current
(leakage)
VCC = 5.5 V,
CAS high
ICC1‡§
Average read- or
write-cycle current
VCC = 5.5 V,
ICC2
Average
g standby
y
current
IOH = – 5 mA
’417409 A- 50
MIN
’417409A - 60
MAX
2.4
IOL = 4.2 mA
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
MIN
MAX
2.4
’417409A - 70
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
± 10
± 10
± 10
µA
VO = 0 V to VCC,
± 10
± 10
± 10
µA
Minimum cycle
130
110
100
mA
VIH = 2.4 V ( TTL),
After one memory cycle,
RAS and CAS high
2
2
2
mA
VIH = VCC – 0.2 V (CMOS),
After one memory cycle,
RAS and CAS high
1
1
1
mA
ICC3‡§
Average refresh current
(RAS-only refresh or
CBR)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
130
110
100
mA
ICC4‡¶
Average EDO current
VCC = 5.5 V,
RAS low,
110
90
80
mA
tHPC = MIN,
CAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
10
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS426409A
PARAMETER
VOH
High-level
output
voltage
VOL
Low-level
output
voltage
II
Input current
(leakage)
IO
ICC1‡§
ICC2
’426409A - 50
TEST CONDITIONS†
MIN
’426409A -60
MAX
MIN
MAX
2.4
MIN
MAX
UNIT
IOH = – 2 mA
LVTTL
IOH = – 100 µA
LVCMOS
IOL = 2 mA
LVTTL
0.4
0.4
0.4
IOL = 100 µA
LVCMOS
0.2
0.2
0.2
VCC = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
Output
current
(leakage)
VCC = 3.6 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
Average
read- or
write- cycle
current
VCC = 3.6 V,
Minimum cycle
90
70
60
mA
VIH = 2 V (LVTTL)
After one memory cycle, RAS and CAS
high
2
2
2
mA
VIH = VCC – 0.2 V (LVCMOS),
After one memory cycle, RAS and CAS
high
1
1
1
mA
90
70
60
mA
100
90
80
mA
Average
standby
current
2.4
’426409A - 70
2.4
V
VCC – 0.2
VCC – 0.2
VCC – 0.2
V
ICC3‡§
Average
refresh
current
(RAS-only
refresh
or CBR)
VCC = 3.6 V,
Minimum cycle,
RAS cycling,
CAS high (RAS-only refresh),
RAS low after CAS low (CBR)
ICC4‡¶
Average
EDO current
VCC = 3.6 V,
RAS low,
tHPC = MIN,
CAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
POST OFFICE BOX 1443
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11
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS427409A
PARAMETER
VOH
High-level
output
voltage
VOL
Low-level
output
voltage
II
Input current
(leakage)
IO
ICC1‡§
ICC2
’427409A - 50
TEST CONDITIONS†
MIN
’427409A -60
MAX
MIN
MAX
2.4
MIN
MAX
UNIT
IOH = – 2 mA
LVTTL
IOH = – 100 µA
LVCMOS
IOL = 2 mA
LVTTL
0.4
0.4
0.4
IOL = 100 µA
LVCMOS
0.2
0.2
0.2
VCC = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
Output
current
(leakage)
VCC = 3.6 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
Average
read- or
write- cycle
current
VCC = 3.6 V,
Minimum cycle
120
100
90
mA
VIH = 2 V (LVTTL)
After one memory cycle, RAS and CAS
high
2
2
2
mA
VIH = VCC – 0.2 V (LVCMOS),
After one memory cycle, RAS and CAS
high
1
1
1
mA
Average
standby
current
2.4
’427409A - 70
2.4
V
VCC – 0.2
VCC – 0.2
VCC – 0.2
V
ICC3‡§
Average
refresh
current
(RAS-only
refresh
or CBR)
VCC = 3.6 V,
Minimum cycle,
RAS cycling,
CAS high (RAS-only refresh),
RAS low after CAS low (CBR)
120
100
90
mA
ICC4‡¶
Average
EDO current
VCC = 3.6 V,
RAS low,
110
90
80
mA
tHPC = MIN,
CAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
12
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
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capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 – A11†
5
pF
Ci(OE)
Input capacitance, OE
7
pF
Ci(RC)
Input capacitance, CAS and RAS
7
pF
Ci(W)
Input capacitance, W
Output capacitance‡
7
pF
7
pF
Co
† A11 is NC (no internal connection) for TMS417409A and TMS427409A.
‡ CAS and OE = VIH to disable outputs
NOTE 3: VCC = NOM supply voltage ± 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x409A-50
’42x409A-50
PARAMETER
MIN
MAX
’41x409A-60
’42x409A-60
MIN
MAX
’41x409A-70
’42x409A-70
MIN
UNIT
MAX
tAA
tCAC
Access time from column address (see Note 5)
25
30
35
ns
Access time from CAS (see Note 5)
13
15
18
ns
tCPA
tRAC
Access time from CAS precharge (see Note 5)
28
35
40
ns
Access time from RAS (see Note 5)
50
60
70
ns
tOEA
tCLZ
Access time from OE (see Note 5)
13
15
18
ns
Delay time, CAS to output in low impedance
0
tREZ
tCEZ
Output buffer turn off delay from RAS (see Note 6)
3
13
3
15
3
18
ns
Output buffer turn off delay from CAS (see Note 6)
3
13
3
15
3
18
ns
tOEZ
tWEZ
Output buffer turn off delay from OE (see Note 6)
3
13
3
15
3
18
ns
Output buffer turn off delay from W (see Note 6)
3
13
3
15
3
18
ns
0
0
ns
NOTES: 4. With ac parameters, it is assumed that tT = 2 ns.
5. For TMS42x409A, access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V.
6. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the output is no longer driven. Data in should not be driven
until one of the applicable maximum specifications is satisfied.
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13
TMS416409A, TMS417409A, TMS426409A, TMS427409A
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EDO timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x409A-50
’42x409A-50
MIN
MAX
’41x409A-60
’42x409A-60
MIN
MAX
’41x409A-70
’42x409A-70
MIN
UNIT
MAX
tHPC
tPRWC
Cycle time, EDO page mode, read-write
20
25
30
ns
Cycle time, EDO read-write
57
68
78
ns
tCSH
tCHO
Delay time, RAS active to CAS precharge
40
48
58
ns
Hold time, OE from CAS
7
10
10
ns
tDOH
tCAS
Hold time, output from CAS
5
Pulse duration, CAS active (see Note 7)
8
tWPE
tOCH
Pulse duration, W active (output disable only)
7
7
7
ns
Setup time, OE before CAS
8
10
10
ns
tCP
tOEP
Pulse duration, CAS precharge
8
10
10
ns
Precharge time, OE
5
5
5
ns
5
10 000
NOTES: 4: With ac parameters, it is assumed that tT = 2 ns.
7. In a read-write cycle, tCWD and tCWL must be observed.
14
POST OFFICE BOX 1443
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10
5
10 000
12
ns
10 000
ns
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
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timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x409A-50
’42x409A-50
’41x409A-60
’42x409A-60
’41x409A-70
’42x409A-70
MIN
MIN
MIN
MAX
Cycle time, random read or write
tRASP
tRAS
Pulse duration, RAS active, fast page mode (see Note 8)
50
100 000
60
100 000
70
100 000
ns
Pulse duration, RAS active, non-page mode (see Note 8)
50
10 000
60
10 000
70
10 000
ns
tRP
tWP
Pulse duration, RAS precharge
30
40
50
ns
Pulse duration, write command
8
10
10
ns
tASC
tASR
Setup time, column address
0
0
0
ns
Setup time, row address
0
0
0
ns
tDS
tRCS
Setup time, data in (see Note 9)
0
0
0
ns
Setup time, read command
0
0
0
ns
tCWL
tRWL
Setup time, write command before CAS precharge
8
10
12
ns
Setup time, write command before RAS precharge
8
10
12
ns
Setup time, write command before CAS active
(early-write only)
0
0
0
ns
Cycle time, read-write
104
UNIT
MAX
tRC
tRWC
tWCS
84
MAX
111
124
135
ns
160
ns
tWRP
tWTS
Setup time, W high before RAS low (CBR refresh only)
10
10
10
ns
Setup time, W low before RAS low (test mode only)
10
10
10
ns
tCSR
tCAH
Setup time, CAS referenced to RAS ( CBR refresh only )
5
5
5
ns
Hold time, column address
8
10
12
ns
tDH
tRAH
Hold time, data in (see Note 9)
8
10
12
ns
Hold time, row address
8
10
10
ns
tRCH
tRRH
Hold time, read command referenced to CAS (see Note 10)
0
0
0
ns
Hold time, read command referenced to RAS (see Note 10)
0
0
0
ns
Hold time, write command during CAS active
( early-write only )
8
10
12
ns
tWCH
tROH
tWRH
Hold time, RAS referenced to OE
8
10
10
ns
Hold time, W high after RAS low (CBR refresh)
10
10
10
ns
tWTH
tCHR
Hold time, W low after RAS low (test mode only)
10
10
10
ns
Hold time, CAS referenced to RAS ( CBR refresh only )
10
10
10
ns
tOEH
tRHCP
Hold time, OE command
13
15
18
ns
Hold time, RAS active from CAS precharge
28
35
40
ns
NOTES: 4.
8.
9.
10.
With ac parameters, it is assumed that tT = 2 ns.
In a read-write cycle, tRWD and tRWL must be observed.
Referenced to the later of CAS or W in write operations
Either tRRH or tRCH must be satisfied for a read cycle.
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
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timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4) (continued)
’41x409A-50
’42x409A-50
MIN
MAX
’41x409A-60
’42x409A-60
MIN
MAX
’41x409A-70
’42x409A-70
MIN
UNIT
MAX
Delay time, column address to write command
( read-write only )
42
49
57
ns
tCPW
tCRP
Delay time, W low after xCAS precharge (read-write only)
45
54
62
ns
5
5
5
ns
tCWD
tOED
Delay time, CAS to write command ( read-write only )
30
34
40
ns
Delay time, OE to data in
13
15
18
ns
tRAD
tRAL
Delay time, RAS to column address (see Note 11)
10
Delay time, column address to RAS precharge
25
tCAL
tRCD
Delay time, column address to CAS precharge
18
Delay time, RAS to CAS ( see Note 11)
12
tRPC
Delay time, RAS precharge to CAS
5
5
5
ns
tRSH
Delay time, CAS active to RAS precharge
8
10
12
ns
tRWD
Delay time, RAS to write command (read-write only)
67
79
92
ns
tTAA
Access time from address (test mode)
30
35
40
ns
tTCPA
Access time, from column precharge (test mode)
35
40
45
ns
tTRAC
Access time, from RAS (test mode)
55
tT
Transition time
tREF
Refresh time interval
tAWD
Delay time, CAS precharge to RAS
2
25
30
30
14
2
35
14
ns
52
75
30
2
ns
ns
25
45
65
30
12
35
20
37
ns
ns
30
ns
’4x6409A
64
64
64
ms
’4x7409A
32
32
32
ms
NOTES: 4. With ac parameters, it is assumed that tT = 2 ns.
11. The maximum value is specified only to ensure access time.
16
12
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PARAMETER MEASUREMENT INFORMATION
VTH
VCC
RL
R1
Output Under Test
Output Under Test
CL = 100 pF
(see Note A)
CL = 100 pF
(see Note A)
(a) LOAD CIRCUIT
R2
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
’41x409A
DEVICE
VCC (V)
5
’42x409A
3.3
R1 (W)
R2 (W)
828
295
VTH (V)
1.31
1178
868
1.4
RL (W)
218
500
Figure 2. Load Circuits for Timing Parameters
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17
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
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SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tCSH
tRCD
tRSH
tCRP
tCAS
tASR
CAS
tRAD
tCP
tASC
tRAH
Address
Row
tCAL
tRAL
Don’t Care
Column
tRCS
tRRH
tRCH
tCAH
W
Don’t Care
Don’t Care
tCAC
tCEZ
tREZ
tAA
DQ1 – DQ4
Hi-Z
Valid Data Out
See Note A
tCLZ
tRAC
tWEZ
tOEA
tWPE
tOEZ
tROH
OE
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 3. Read-Cycle Timing
18
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
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SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCSH
tCAS
tASR
CAS
tCP
tASC
tCAL
tRAL
tRAH
Address
tCAH
Row
Don’t Care
Column
tCWL
tRAD
tRWL
tWCH
W
tWCS
Don’t Care
Don’t Care
tDH
tDS
DQ1 – DQ4
Don’t Care
Valid Data
Don’t Care
OE
Figure 4. Early-Write-Cycle Timing
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19
TMS416409A, TMS417409A, TMS426409A, TMS427409A
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SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCAS
tCSH
tASR
tASC
CAS
tCP
tRAL
tCAL
tRAH
tCAH
Address
Row
Don’t Care
Column
tCWL
tRAD
W
tDS
tRWL
Don’t Care
Don’t Care
tWP
tCLZ
tDH
Don’t Care
Valid Data In
DQ1 – DQ4
Invalid Data Out
tOED
tOEH
OE
Don’t Care
Don’t Care
Figure 5. Write-Cycle Timing
20
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
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SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tRP
tT
tCRP
tRCD
tCAS
tASR
CAS
tCP
tRAH
tCAH
tRAD
Address
tT
tASC
Row
Don’t Care
Column
tCWL
tRCS
tRWL
tRWD
tWP
Don’t Care
W
tAWD
tCWD
tCAC
tDS
tAA
tDH
tCLZ
DQ1 – DQ4
Hi-Z
Data
Out
See Note A
tRAC
Data
In
tOEZ
tOEA
tOED
OE
Don’t Care
tOEH
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Read-Write-Cycle Timing
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21
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
tRASP
RAS
tT
tRCD
tCSH
tCRP
tHPC
tCAS
CAS
tRP
tRHCP
tRSH
tCP
tRAH
tASC
tCAL
tASR
tRAL
tCAH
Address
Row
Column #1
Column #2
Column #3
tRAD
tRCH
tOEA
OE
tRCS
tCAC
tRRH
tDOH
W
tCAC
tAA
tAA
tCEZ
tCPA
tRAC
See Note C
tREZ
tCLZ
DQ1 – DQ4
See Note A
Data #1
Data #2
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. Access time is tCPA-, tAA-, or tCAC-dependent.
C. Output is turned off by tCEZ if RAS goes high during CAS low.
Figure 7. EDO Read Cycle
22
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Data #3
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tRHCP
tHPC
tCP
tCAS
tRSH
tASR
CAS
tRAH
tASC
tCAL
tCAH
Row
Address
tRAL
Column #1
Column #2
Column #3
tRAD
tOCH
tCHO
tOEP
tOEP
OE
tOEA
tRRH
tRCS
tRCH
tOEA
W
tCAC
tDOH
tCLZ
tOEZ
tCAC
tAA
DQ1 – DQ4
tREZ
tOEZ
tRAC
See Note A
tCEZ
tCPA
tAA
Data #1
Data #1
Data #2
Data #3
NOTE A: Output is turned off by tCEZ if RAS goes high during CAS low.
Figure 8. EDO Read-Cycle With OE Control
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23
TMS416409A, TMS417409A, TMS426409A, TMS427409A
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SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
tRASP
RAS
tCSH
tRHCP
tHPC
tCP
tASR
tRAH
tASC
Address
tCRP
tRSH
tCAS
CAS
tRP
Row
tCAH
tRAL
tCAL
Column #1
Column #2
Column #3
tRAD
OE
tOEA
tCAC
tRCS
tCAC
tWPE
tRCH
tRRH
W
tDOH
tCAC
tWEZ
tAA
tCLZ
tRAC
DQ1 – DQ4
tCPA
tCPA
tAA
Data #1
tREZ
Data #2
Figure 9. EDO Read-Cycle With W Control
24
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tCEZ
tAA
Data #3
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tCSH
tRCD
tHPC
tCAS
tASC
CAS
tRAH
tCP
tCAH
tASR
Address
tCRP
tRSH
tRAL
tCAL
Row
Column
Column
tCWL
Don’t Care
tCWL
tRAD
tWCH
tRWL
tWCS
W
Don’t Care
Don’t Care
Don’t Care
tDH
tDS
DQ1 – DQ4
Data In
Data In
Don’t Care
Don’t Care
OE
NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated.
Figure 10. EDO Early-Write-Cycle Timing
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25
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
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SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tCSH
tHPC
tCRP
tRSH
tRCD
tCAL
tCAS
tASC
CAS
tRAH
tCP
Address
tRAL
tCAH
tASR
Row
tRAD
tCWL
tCWL
tRWL
tWP
tDS
W
Don’t Care
Don’t Care
Don’t Care
Don’t Care
tOEH
tDH
DQ1 – DQ4
Don’t Care
Column
Column
tCLZ
Valid
In
Valid Data In
Don’t Care
Invalid Data out
tOEH
tOED
Don’t Care
OE
Don’t Care
NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated.
Figure 11. EDO Write-Cycle Timing
26
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tRSH
tPRWC
tRCD
tCAS
tASR
tASC
CAS
tCAL
tCAH
tRAL
tRAD
Row
Address
tCRP
tCP
Column 1
Column 2
Don’t Care
tRAH
tCWL
tCWD
tCPW
tAWD
tRWL
tWP
tRWD
W
tRCS
tCPA
tAA
tDH
tRAC
Valid Out 2
(see Note A)
tDS
tCAC
Valid
In 1
DQ1 – DQ4
tCLZ
tOEA
tOEH
Valid
In 2
Valid
Out 1
tOEZ
tOED
tOEH
OE
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not violated.
Figure 12. EDO Read-Write-Cycle Timing
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27
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
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SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tCRP
tRP
tT
CAS
Don’t Care
tRPC
tRAH
tASR
Address
Don’t Care
Row
Don’t Care
Don’t Care
W
DQ1 – DQ4
Hi Z
Don’t Care
OE
Figure 13. RAS-Only Refresh-Cycle Timing
28
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Row
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWRP
tWRH
W
Address
Don’t Care
OE
Don’t Care
DQ1 – DQ4
Hi-Z
Figure 14. Automatic-CBR-Refresh-Cycle Timing
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29
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Cycle
tRP
tRP
tRAS
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Address
Row
Col
Don’t Care
tWRH
tWRP
tWRH
tRRH
tWRP
tRAC
W
tCAC
tWEZ
tREZ
tCEZ
tAA
Valid Data Out
DQ1 – DQ4
tCLZ
tOEZ
tOEA
OE
Figure 15. Hidden-Refresh-Cycle (Read) Timing
30
tWRH
tWRP
tRCS
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
tRP
tRAS
tRP
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Row
Address
Don’t Care
Col
tWRH
tWRP
tWCS
tWP
W
tWCH
tDH
tDS
DQ1 – DQ4
Don’t Care
Valid Data
Don’t Care
OE
Figure 16. Hidden-Refresh-Cycle (Write) Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
31
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tCSR
tCHR
tRPC
tT
CAS
tWTH
tWTS
Don’t Care
W
Address
Don’t Care
OE
Don’t Care
DQ1 – DQ4
Hi-Z
Figure 17. Test-Mode-Entry-Cycle Timing
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWRP
W
Don’t Care
Don’t Care
tWRH
Address
Don’t Care
tREZ
tCEZ
DQ1 – DQ4
Hi-Z
Don’t Care
Figure 18. Test-Mode-Exit-Cycle CBR-Refresh-Cycle Timing
32
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
MECHANICAL DATA
DJ (R-PDSO-J24/26)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
0.680 (17,27)
0.670 (17,02)
26
21
19
14
0.340 (8,64)
0.330 (8,38)
0.305 (7,75)
0.295 (7,49)
1
6
8
13
0.032 (0,81)
0.026 (0,66)
0.106 (2,69) TYP
0.148 (3,76)
0.128 (3,25)
0.008 (0,20) NOM
Seating Plane
0.020 (0,51)
0.016 (0,41)
0.004 (0,10)
0.007 (0,18) M
0.275 (6,99)
0.260 (6,60)
0.050 (1,27)
4040092-3 / B 02/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
33
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
MECHANICAL DATA
DGA (R-PDSO-G24/26)
PLASTIC SMALL-OUTLINE PACKAGE
0.020 (0,50)
0.012 (0,30)
0.050 (1,27)
26
0.008 (0,21) M
14
0.371 (9,42)
0.355 (9,02)
0.304 (7,72)
0.296 (7,52)
0.006 (0,15) NOM
1
13
0.679 (17,24)
0.671 (17,04)
Gage Plane
0.010 (0,25)
0°– 5°
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.047 (1,19) MAX
0.004 (0,10)
0.002 (0,05) MIN
4040265-3 / C 11/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
34
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
device symbolization (TMS416409A illustrated)
TI
-SS
Speed ( - 50, - 60, - 70)
TMS416409A
DJ
Package Code
W
E
Y
M LLLL
P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
35
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
36
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
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