ETC CXA3328TN

CXA3328TN/EN
Analog Signal Processor RX-IF IC for W-CDMA Cellular Phones
Description
The CXA3328TN/EN is an analog signal processor
RX-IF IC for W-CDMA cellular phones. This IC contains
a gain control amplifier and quadrature demodulator.
16 pin TSSOP (Plastic)
Features
• Wide gain control range
• Linear gain slope
• Wide band (100 to 600MHz)
• Small package
16-pin TSSOP (CXA3328TN)
16-pin VSON (CXA3328EN)
• Low voltage operation (2.7 to 3.3V)
16 pin VSON (Plastic)
Absolute Maximum Ratings
• Supply voltage
VCC
• Operating temperature Topr
• Storage temperature
Tstg
–0.3 to 5.5
–55 to +125
–65 to +150
V
°C
°C
Operating Conditions
• Supply voltage
• Operating temperature
2.7 to 3.3
–25 to +85
V
°C
VCC
Ta
Structure
Bipolar silicon monolithic IC
VCONT
VCC_BUF
GND_BUF
QX
Q
GND_BUF
IX
I
Block Diagram
16
15
14
13
12
11
10
9
AGC
CONT
SWITCH
INX
GND_IF
GND_IF
5
6
7
8
GND_R
4
LOCAL IN
3
LOCAL SW
2
1/4
VCC_IF
1
IN
1/2
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00738D24-PS
CXA3328TN/EN
Pin Description
Pin
No.
Symbol
Typical pin
voltage [V]
Equivalent Circuit
Pin Description
20k
20k
Vcc_IF
1
2
1, 2
IN, INX
2.85
IF differential input.
GND_IF
3, 4
GND_IF
0
GCA, quadrature demodulator
block ground.
5
Vcc_IF
2.85
GCA, quadrature demodulator
block VCC.
Vcc_IF
30k
Local frequency division ratio
setting.
6
6
LOCAL SW
—
High: 1/4 frequency division
Low: 1/2 frequency division
GND_IF
Vcc_IF
2k
7
7
LOCAL IN
—
0.5k
2k
Local input.
50
GND_R
8
GND_R
GND_IF
0
Local signal GND.
Vcc_BUF
9, 10,
12, 13
I, IX,
Q, QX
9
1.5
10
12
13
GND_BUF
–2–
Baseband I, Q outputs.
CXA3328TN/EN
Pin
No.
Symbol
Typical pin
voltage [V]
11, 14
GND_BUF
0
15
Vcc_BUF
2.85
Equivalent Circuit
Pin Description
Output buffer block ground.
Output buffer block VCC.
Vcc_IF
16k
16k
40k
16
VCONT
—
16
Gain control voltage input.
12k
12k
GND_IF
–3–
CXA3328TN/EN
Electrical Characteristics
(VCC = 2.85V, Ta = 27°C)
Current Consumption
Item
Current
Consumption
Symbol
Icc
MeasureMeasurement circuit ment point
Conditions
Vcont = 1.3V
1
A
Min.
Typ.
Max.
Unit
8
11
15
mA
I/O Resistance
Item
(VCC = 2.85V, Ta = 27°C)
Symbol
MeasureMeasurement circuit ment point
Conditions
Min.
Typ.
Max.
Unit
Input resistance
VCONT pin
RIVC
DC measurement:
VIN = 2.85V
1
B
10
—
—
kΩ
LO input
resistance
RILO
DC measurement:
IIN = 2mA
1
C
37.5
50
62.5
Ω
Output resistance
ZOUT
I, IX, Q, QX pins
DC measurement:
IOUT = 100µA
1
D, E
F, G
80
250
550
Ω
IF I/O Resistance (Design Values)
Item
Symbol
(VCC = 2.85V, Ta = 27°C)
Conditions
Min.
Typ.
Max.
Unit
IF input
resistance
RIIF
Differential between Pins 1 and 2
380MHz
—
2.6
—
kΩ
IF input
capacitance
CIIF
Differential between Pins 1 and 2
380MHz
—
2
—
pF
Input Conditions
Item
(VCC = 2.85V, Ta = 27°C)
Symbol
Conditions
Min.
Typ.
Max.
Unit
IF input frequency 1
FRXIF1
LOCAL SW = “L”
—
380
—
MHz
IF input frequency 2
FRXIF2
LOCAL SW = “H”
—
190
—
MHz
LO input frequency
FLO
—
760
—
MHz
LO input level
VLO
–18
–15
–12
dBm
–4–
CXA3328TN/EN
GCA Block
Item
Input conversion
noise figure
Input conversion
3rd intercept
point
(VCC = 2.85V, Ta = 27°C)
Symbol
Measure- Measurement circuit ment point
Conditions
Min.
Typ.
Max.
Unit
3
A, B
C, D
—
—
10
dB
Gain = +65dB
FRXIF = 382MHz
IIP3_1
FLO = 760MHz
LOCAL SW = “L”
2
A, B
C, D
–58
—
—
dBm
Gain = –10dB
FRXIF = 382MHz
IIP3_2
FLO = 760MHz
LOCAL SW = “L”
2
A, B
C, D
–10
—
—
dBm
—
0.25
dB
–25.5 –20.5
dB
NF
Gain = +65dB
GF
FRXIF = 382 ± 2.5MHz
LOCAL SW = “L”
FLO = 2 × (FRXIF + 2) MHz
2
A, B
C, D
–0.25
GMIN
Vcont = 0.3 [V],
30mVp-p differential output
FRXIF = 382MHz
FLO = 760MHz
LOCAL SW = “L”
2
A, B
C, D
—
Maximum gain
GMAX
Vcont = 2.3 [V],
100mVp-p differential output
FRXIF = 382MHz
FLO = 760MHz
LOCAL SW = “L”
2
A, B
C, D
67.5
72.5
—
dB
Gain temperature
error
GERR
Ta = –25 to +85°C
2
A, B
C, D
–4
—
4
dB
Gain flatness
Minimum gain
–5–
CXA3328TN/EN
Quadrature Demodulator Block
Item
(VCC = 2.85V, Ta = 27°C)
Symbol
MeasureMeasurement circuit ment point
Conditions
Min.
Typ.
Max.
Unit
VMAX
RL = 10kΩ, CL = 10pF
FRXIF = 382MHz
FLO = 760MHz
LOCAL SW = “L”
2
A, B
C, D
500
—
—
mVp-p
I/Q output band
width
VBW
–3dB band width
2
A, B
C, D
5
13
—
MHz
I/Q phase error
PERR
FRXIF = 382MHz
FLO = 760MHz
LOCAL SW = “L”
2
A, B
C, D
–4
—
4
deg
I/Q output
VBL
amplitude balance
FRXIF = 382MHz
FLO = 760MHz
LOCAL SW = “L”
2
A, B
C, D
–1.5
—
1.5
dB
I-IX/Q-QX
DC offset
DC measurement
2
A, B
C, D
–200
—
200
mV
I/Q maximum
output amplitude
VOFST
Local Frequency Division Ratio
LOCAL SW (Pin 6)
Frequency division ratio
L
1/2
H
1/4
–6–
CXA3328TN/EN
Electrical Characteristics Measurement Circuit 1
15
14
13
12
E
D
11
I
IX
Q
QX
VCC_BUF
VCONT
16
F
GND_BUF
G
GND_BUF
B
10
9
AGC
CONT
SWITCH
1/2
600
∗2
TRANS
50 : 500Ω
8
GND_R
7
LOCAL IN
82n
6
LOCAL SW
5
VCC_IF
4
GND_IF
3
GND_IF
∗1
2
INX
IN
1
1/4
100p
1µ
C
FRXIF
A
∗1 LQN21A (MURATA MFG. CO., LTD.)
∗2 616DS-1135 (TOKO, Inc.)
–7–
CXA3328TN/EN
Electrical Characteristics Measurement Circuit 2
C
15
14
10k
10000p
10p
IX
Q
12
10000p
10p
GND
10p
13
A
10k
10000p
10p
QX
VCONT
VCC_BUF
GND_BUF
10000p
16
B
10k
11
I
D
10k
10
9
AGC
CONT
SWITCH
1/2
7
8
GND_R
LOCAL IN
82n
6
LOCAL SW
5
VCC_IF
4
GND_IF
3
GND_IF
∗1
2
INX
IN
1
1/4
100p
600
∗2
TRANS
50 : 500Ω
1µ
FLO
FRXIF
∗1 MURATA LQN21A
∗2 TOKO 616DS-1135
–8–
CXA3328TN/EN
Electrical Characteristics Measurement Circuit 3
C
B
10k
10k
15
10p
13
12
10000p
10p
10p
IX
Q
QX
10p
14
10k
10000p
GND
GND_BUF
VCC_BUF
VCONT
16
10k
10000p
10000p
A
11
I
D
10
9
AGC
CONT
SWITCH
1/2
7
8
GND_R
LOCAL IN
82n
6
LOCAL SW
5
VCC_IF
4
GND_IF
3
GND_IF
∗1
2
INX
IN
1
1/4
100p
600
1µ
FLO
∗1 MURATA LQN21A
–9–
CXA3328TN/EN
Application Circuit
To LPF
16
15
14
13
12
11
I
IX
GND_BUF
Q
QX
VCONT
VCC_BUF
GND_BUF
Vcc
10
9
AGC
CONT
SWITCH
1/2
8
GND_R
7
LOCAL IN
∗
6
LOCAL SW
5
VCC_IF
4
GND_IF
3
GND_IF
INX
2
IN
1
1/4
∗
RX
BPF
From receive
RF circuit
Vcc
Local signal
∗ Adjust this value so that the impedance matching with this IC is optimum.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 10 –
CXA3328TN/EN
Description of Operation
1. Outline of Operation
This IC performs the signal processing between the analog transmit baseband processing block and the
analog transmit RF processing block of the cellular phone. The figure below shows the general circuit block
diagram for the portable cellular phone using this IC. The input of this IC is connected to the analog RF
processing block; the output is connected to the baseband signal processing block.
CXA3328TN/EN
RF receive/transmit
processing
CXG1110EN
LPF
Digital processing mobile
station modem
CXA3309ER
CODEC
LPF
2. IC Internal Signal Flow
An IF signal and a local signal are input to this IC as shown in the figure below. The IF signal is gaincontrolled to the necessary level by the gain control amplifier and is input to the quadrature demodulator
block. The local signal is 1/2 or 1/4 frequency-divided. Also, that signal becomes the quadrature I/Q local
signal via the FF phase shifter and quadrature-demodulated with the IF signal to become the baseband
signal.
OUT (I)
IF
OUT (Q)
1/2
Local
1/4
Phase
Shifter,
Switch
– 11 –
CXA3328TN/EN
Notes on Operation
1. IF Input
The IF signal is differentially input to the IN pin and INX pin of this IC. IF is input to the input pin by AC
coupling. The value of the AC coupling is selected so that the transfer power from the receive RF circuit is
maximum.
CXA3328TN/EN
1
From receive
RF circuit
RX
BPF
∗
∗
2
∗ This value must be the value taken for the optimum impedance matching between the BPF filter and this IC.
2. Notes on Power Supplies
The CXA3328TN/EN is designed to operate by a 2.85V stabilized power supply to allow use with the
battery driven portable phones. Using multiple voltage regulators throughout the phone is recommended to
minimize the power supply noise in the CXA3328TN/EN power supply input. The recommended power
supply range for the CXA3328TN/EN is 2.7 to 3.3V. Decouple the power supplies around the CXA3328TN/
EN using 1µF capacitor for each VCC pin. Locate this capacitor as close to the pins as possible, and
minimize the series inductance for the pin connections. Using an additional 1nF decoupling capacitor in
parallel to the 1µF capacitor is recommended to further reduce the high frequency noise in the power
supply input to the CXA3328TN/EN.
– 12 –
CXA3328TN/EN
Example of Representative Characteristics
Voltage gain vs. Control voltage Vcont
80
70
60
Voltage gain [dB]
50
40
30
20
10
0
–10
–20
–30
0
0.5
1
1.5
2
2.5
3
Vcont [V]
Noise figure vs. Voltage gain
80
70
Noise figure [dB]
60
50
40
30
20
10
0
–10
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
50
60
70
80
90
Voltage gain [dB]
IIP3 vs. Voltage gain
10
0
–10
IIP3 [dBm]
–20
–30
–40
–50
–60
–70
–80
–40
–30
–20
–10
0
10
20
30
Voltage gain [dB]
– 13 –
40
CXA3328TN/EN
Package Outline
Unit: mm
CXA3328TN
16PIN TSSOP (PLASTIC)
1.2MAX
4.1
S
2.05
A
16
B
0.08 S
X2
9
0.2
S A B
3.9
(3.0)
0.1 ± 0.05
0.25
0.1
2.9
0.1
X
X
8
X4
0.1
S A B
0.45 ± 0.1
1
0.5
0˚ to 8˚
0.08 M S A
0.2 ± 0.02
+ 0.036
0.22 – 0.03
DETAIL B
0.1 ± 0.01
+ 0.026
0.12 – 0.02
B
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.03g
TSSOP-16P-L01
SONY CODE
SCT & Kokubu Ass’y
16PIN TSSOP (PLASTIC)
1.2MAX
4.1
S
2.05
A
16
B
0.08 S
X2
9
0.2
S A B
3.9
(3.0)
0.1 ± 0.05
0.25
0.1
2.9
0.1
X
X
8
X4
0.1
0.5
S A B
0.45 ± 0.1
1
0˚ to 8˚
0.08 M S A
0.2 ± 0.02
+ 0.036
0.22 – 0.03
DETAIL B
0.1 ± 0.01
+ 0.026
0.12 – 0.02
B
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.03g
TSSOP-16P-L01
SONY CODE
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
– 14 –
CXA3328TN/EN
Package Outline
Unit: mm
CXA3328EN
16PIN VSON (PLASTIC)
0.9 MAX
0.6
3.5
0.05 S
A
0.5 ± 0.2
2.7
2.5
0.35 ± 0.1
S
B
2x
0.4
0.35 ± 0.1
0.2 S B
4x
1.4
0.2 S A B
0.03 ± 0.03
0.2 ± 0.01
0.23 ± 0.02
0.05 M S A-B
Soldrer Plating
0.13 ± 0.025
+ 0.09
0.14 – 0.03
NOTE: 1) The dimensions of the terminal section apply to the
ranges of 0.1mm and 0.25mm from the end of a terminal.
TERMINAL SECTION
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.02 g
SONY CODE
VSON-16P-01
SCT & Kokubu Ass’y
16PIN VSON (PLASTIC)
0.9 MAX
0.6
3.5
0.05 S
A
B
0.4
0.5 ± 0.2
2.7
2.5
0.35 ± 0.1
S
2x
0.35 ± 0.1
0.2 S B
4x
1.4
0.03 ± 0.03
0.2 ± 0.01
0.05 M S A-B
0.23 ± 0.02
0.2 S A B
Soldrer Plating
0.13 ± 0.025
+ 0.09
0.14 – 0.03
NOTE: 1) The dimensions of the terminal section apply to the
ranges of 0.1mm and 0.25mm from the end of a terminal.
TERMINAL SECTION
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.02 g
SONY CODE
VSON-16P-01
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
– 15 –
Sony Corporation