November 1996 LMX9301 Frequency Synthesizer Module General Description Features The Frequency Synthesizer Module is a Low Temperature Co-fired Ceramic (LTCC) RF module consisting of a high performance frequency synthesizer, loop filter, and voltage controlled oscillator (VCO). The frequency synthesizer is fabricated using National’s ABiC IV BiCMOS process (fT e 14 GHz). The loop filter and VCO are fabricated with National’s Low Temperature Co-fired Ceramics. The Frequency Synthesizer Module can be used for local oscillator applications. Using a digital phase locked loop technique, the on board frequency synthesizer can generate a very stable, low noise local oscillator. Serial data is transferred into the module using a three wire interface. The loop filter is designed for fast lock times and maximum attenuation of reference spurs. The module is available in an 18-pin 500 mil c 500 mil c 125 mil (refer to dwg) package. Y Y Y Low current consumption Low phase noise tunable local oscillator 1.1 GHz PLLatinumTM PLL in module Applications Y Y AMPS wireless cellular systems Portable wireless communications (PCS/PCN, cordless) TL/W/12822 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. MICROWIRETM and PLLatinumTM are trademarks of National Semiconductor Corporation. C1996 National Semiconductor Corporation TL/W/12822 RRD-B30M17/Printed in U. S. A. http://www.national.com LMX9301 Frequency Synthesizer Module ADVANCE INFORMATION Pin Diagram TL/W/12822 – 2 Pin Descriptions Pin No. Pin Name 1 GND 2 OSCÐIN 3 VCC1 Power supply voltage input to PLL. 4 GND Ground. 5 RFOUT 6 GND Ground. 7 GND Ground. 8 VCC2 Power supply voltage input to VCO. 9 GND Ground. 10 GND Ground. 11 GND Ground. 12 GND Ground. 13 GND 14 CLK I High impedance CMOS Clock input. Data is clocked in on the rising edge, into the various counters and registers. 15 DATA I Binary serial data input. Data entered MSB first. LSB is control bit. High impedance CMOS input. 16 LE I Load enable input (with internal pull-up resistor). When LE transitions HIGH, data stored in the shift registers is loaded into the appropriate latch (control bit dependent). Clock must be low when LE toggles high or low. See serial diagram. 17 LD O Lock detect. Output provided to indicate when the VCO frequency is in ‘‘lock’’. When the loop is locked, the pin’s output is HIGH with narrow pulses. 18 GND http://www.national.com I/O Description Ground. I O Reference Oscillator input. A CMOS inverting gate input intended for connection to a crystal resonator for operation as an oscillator. The input has a VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. May also be used as a buffer for an externally provided reference oscillator. VCO frequency output. Ground. Ground. 2 Functional Diagram TL/W/12822 – 3 Typical Application Example TL/W/12822 – 4 3 http://www.national.com Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Power Supply Voltage VCC VP Power Supply Voltage (VCC) Operating Temperature (TA) Note 1: Absolute Maximum Rating indicate limits beyond which daage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. b 0.3V to a 6.5V b 0.3V to a 6.5V Voltage on Any Pin with GND e 0V (VI) b 0.3V to a 6.5V Storage Temperature Range (TS) Lead Temperature (TL) (solder, 4 sec.) 4.75V to 5.5V b 10§ C to a 70§ C b 65§ C to a 150§ C a 260§ C Electrical Characteristics The following specifications are guaranteed over the recommended operating conditions unless otherwise specified. Symbol Parameter Value Conditions Min Typ Max 45 ICC Power Supply Current 35 fOSC Reference Oscillator Frequency 15 fVCO Frequency 738 POUT Output Level b3 fi (fm) Single Side Band Phase Noise Spurious Reference Sidebands Nth Spurious Harmonic fm e 1000 Hz 80 fm e 30000 Hz 110 0 60 kHz Offset b 90 2nd harmonic b 38 Spurious Non Harmonic Frequency Lock Time (MAX) TLOCK Frequency Lock Time (Adjacent Channels) g 1 kHz from carrier, 30 kHz jump 766 MHz a3 dBm dBc/Hz b 80 TLOCK mA MHz dBc/Hz 30 kHz Offset g 1 kHz from carrier, 25 MHz jump Units b 70 dBc b 10 dBc b 70 dBc dBc 25 40 ms 8 20 ms DC Electrical Characteristics The following specifications are guaranteed over the recommended operating conditions. DIGITAL INTERFACE SECTION Symbol Parameter Conditions Value Min Typ Max VCC b 0.8 Units VIH High Level Input Voltage VIL Low Level Input Voltage IIN Input Current tCS Data to Clock Set Up Time 50 ns tCH Data to Clock Hold Time 10 ns tCWH Clock Pulse Width High 50 ns tCWL Clock Pulse Width Low 50 ns tES Clock to Load Enable Set Up Time 50 ns tEW Load Enable Pulse Width 50 ns GND k VIN k VCC b 1.0 Note 1: DC Electrical Characteristics for the digital section apply to the power down pin and the MICROWIRE TM interface. http://www.national.com 4 V 0.8 V 1.0 mA PLL Functional Description The simplified block diagram below shows the 19-bit data register, the 14-bit R Counter and the S Latch, and the 18-bit N Counter (intermediate latches are not shown). The data stream is clocked (on the rising edge of clock) into the DATA input, MSB first. If the Control Bit (last bit input) is HIGH, the DATA is transferred into the R Counter (programmable reference divider) and the S Latch (prescaler select: 64/65 and 128/129). If the Control Bit (LSB) is LOW, the DATA is transferred into the N Counter (programmable divider). TL/W/12822 – 5 PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND PRESCALER SELECT (S LATCH) If the Control Bit (last bit shifted into the Data Register) is HIGH, data is transferred from the 19-bit shift register into a 14-bit latch (which sets the 14-bit R Counter) and the 1-bit S Latch (S15, which sets the prescaler 64/65 and 128/129). Serial data format is shown below. TL/W/12822 – 6 14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER) The R divide ratio must be set to maintain a 30 kHz phase comparator frequency. The divide ratio is chosen by dividing the selected reference oscillator frequency by 30 kHz. For example, a 15 MHz reference oscillator frequency gives: Re OSCÐIN 15 MHz e e 500 30 kHz 30 kHz 1-BIT PRESCALER SELECT (S LATCH) Prescaler Select P 128/129 Divide Ratio R S 14 S 13 S 12 S 11 S 10 S 9 S 8 S 7 S 6 S 5 S 4 S 3 S 2 S 1 3 0 0 0 0 0 0 0 0 0 0 0 0 1 1 # # # # # # # # # # # # # # # 1333 0 0 0 1 0 1 0 0 1 1 0 1 0 1 64/65 S 15 0 1 Notes: Divide ratios less than 3 or greater than 1333 are prohibited. S1 to S14: These bits select the divide ratio of the programmable reference divider. C: Control bit (set to HIGH level to load R counter and S Latch) Data is shifted in MSB first. 5 http://www.national.com PLL Functional Description (Continued) PROGRAMMABLE DIVIDER (N COUNTER) The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control Bit (last bit shifted into the Data Register) is LOW, data is transferred from the 19-bit shift register into a 7-bit latch (which sets the 7-bit Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter). Serial data format is shown below. TL/W/12822 – 7 Note: S8 to S18: Programmable counter divide ratio control bits (3 to 2047) 7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER) The A COUNTER divide ratio is dependent on the PRESCALER select. PRESCALER e 64/65 PRESCALER e 128/129 Divide Ratio A S 7 S 6 S 5 S 4 S 3 S 2 S 1 Divide Ratio A S 7 S 6 S 5 S 4 S 3 S 2 S 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 # # # # # # # # # # # # # # # # 64 0 1 1 1 1 1 1 127 1 1 1 1 1 1 1 Notes: Divide ratio: 0 to 63 Notes: Divide ratio: 0 to 127 BtA BtA 11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER) The B COUNTER divide ratio is dependent on the PRESCALER select. PRESCALER e 64/65 Divide Ratio R S 18 S 17 S 16 S 15 S 14 S 13 S 12 S 11 S 10 S 9 S 8 384 0 0 1 1 0 0 0 0 0 0 0 # # # # # # # # # # # # 399 0 0 1 1 0 0 0 1 1 1 1 Note: Divide ratio: 384 to 399 (Other divide ratios are prohibited) PRESCALER e 128/129 Divide Ratio R S 18 S 17 S 16 S 15 S 14 S 13 S 12 S 11 S 10 S 9 S 8 192 0 0 0 1 1 0 0 0 0 0 0 # # # # # # # # # # # # 199 0 0 0 1 1 0 0 0 1 1 1 Note: Divide ratio: 192 to 199 (Other divide ratios are prohibited) http://www.national.com 6 Functional Description (Continued) PULSE SWALLOW FUNCTION fVCO e [(P c B) a A] c fOSC/R, where fOSC e 30 kHz. Output frequency of voltage controlled oscillator (VCO), 738 MHz to 766 MHz fVCO B: Preset divide ratio of binary 11-bit programmable counter, If P e 128, then 192 s B s 199 If P e 64, then 384 s B s 399 A: Preset divide ratio of binary 7-bit swallow counter (0 s A s 127, A s B) If P e 128, then 0 s A s 127 If P e 64, then 0 s A s 64 fOSC: Output frequency of the external reference frequency oscillator R: Preset divide ratio of binary 14-bit programmable reference counter (3 to 1333) P: Preset modulus of dual modulus prescaler SERIAL DATA INPUT TIMING TL/W/12822 – 8 Notes: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6 V/ns with amplitudes of 2.2V @ VCC e 2.7V and 2.6V @ VCC e 5.5V. Typical Lock Detect Circuit A lock detect circuit is needed in order to provide a steady LOW signal when the PLL is in the locked state. A typical circuit is shown below. TL/W/12822 – 9 7 http://www.national.com TL/W/12822 – 10 http://www.national.com 8 9 http://www.national.com LMX9301 Frequency Synthesizer Module Physical Dimensions inches (millimeters) unless otherwise noted LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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