74LVX163 Low Voltage Synchronous Binary Counter with Synchronous Clear General Description The LVX163 is a synchronous modulo-16 binary counter. This device is synchronously presettable for application in programmable dividers and has two types of Count Enable inputs plus a Terminal Count output for versatility in forming multistage counters. The CLK input is active on the rising edge. Both PE and CLR inputs are active on low logic levels. Presetting is synchronous to rising edge of CLK and the Clear function of the LVX163 is synchronous to CLK. Two enable inputs (ENP and ENT) and Carry Output are provided to enable easy cascading of counters, which facilitates easy implementation of n-bit counters without using external gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. Features Y Y Y Y Input voltage level translation from 5V to 3V Ideal for low power/low noise 3.3V applications Available in SOIC JEDEC, SOIC EIAJ, and TSSOP packages Guaranteed simultaneous switching noise and dynamic threshold performance Logic Symbols Connection Diagram IEEE/IEC Pin Assignment for TSSOP and SOIC TL/F/12157–1 TL/F/12157 – 3 TL/F/12157 – 2 Order Number SOIC JEDEC SOIC EIAJ TSSOP 74LVX163M 74LVX163MX 74LVX163SJ 74LVX163SJX 74LVX163MTC 74LVX163MTCX M16A M16D MTC16 See NS Package Number C1996 National Semiconductor Corporation TL/F/12157 Pin Names Description CEP CET CP MR P0 –P3 PE Q0 –Q3 TC Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Synchronous Master Reset Input Parallel Data Inputs Parallel Enable Inputs Flip-Flop Outputs Terminal Count Output RRD-B30M17/Printed in U. S. A. http://www.national.com 74LVX163 Low Voltage Synchronous Binary Counter with Synchronous Clear December 1996 Functional Description nous reset for flip-flops, registers or counters. When the Output Enable (OE) is LOW, the parallel data outputs O0 – O3 are active and follow the flip-flop Q outputs. A HIGH signal on OE forces O0 –O3 to the High Z state but does not prevent counting, loading or resetting. Logic Equations: Count Enable e CEP # CET # PE The LVX163 counts in modulo-16 binary sequence. From state 15 (HHHH) it increments to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: synchronous reset, parallel load, count-up and hold. Four control inputsÐ Synchronous Reset (MR), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)Ðdetermine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The LVX163 uses D-type edge-triggered flip-flops and changing the MR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. TC e Q0 # Q1 # Q2 # Q3 # CET Mode Select Table MR PE CET CEP L H H H H X L H H H X X H L X X X H X L Action on the Rising Clock Edge ( L ) Reset (Clear) Load (Pn x Qn) Count (Increment) No Change (Hold) No Change (Hold) H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial State Diagram Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchro- TL/F/12157 – 4 TL/F/12157 – 5 FIGURE 1 TL/F/12157 – 6 FIGURE 2 http://www.national.com 2 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. TL/F/12157 – 7 Block Diagram 3 http://www.national.com Absolute Maximum Ratings (Note) Supply Voltage (VCC) DC Input Diode Current (IIK) VI e b0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO e b0.5V VO e VCC a 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. b 0.5V to a 7.0V b 20 mA b 0.5V to 7V b 20 mA a 20 mA Recommended Operating Conditions b 0.5V to VCC a 0.5V g 25 mA Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Input Rise and Fall Time (Dt/Dv) g 50 mA b 65§ C to a 150§ C Power Dissipation 180 mW 2.0V to 3.6V 0V to 5.5V 0V to VCC b 40§ C to a 85§ C 0 ns/V to 100 ns/V DC Electrical Characteristics Symbol Parameter VCC VIH High Level Input Voltage 2.0 3.0 3.6 Low Level Input Voltage 2.0 3.0 3.6 High Level Output Voltage 2.0 3.0 3.0 Low Level Output Voltage 2.0 3.0 3.0 IIN Input Leakage Current ICC Quiescent Supply Current 74LVX163 74LVX163 TA e a 25§ C TA e b 40§ C to a 85§ C Min VIL VOH VOL http://www.national.com Typ Max 1.5 2.0 2.4 Min 1.9 2.9 2.58 2.0 3.0 0.0 0.0 Conditions Max 1.5 2.0 2.4 0.5 0.8 0.8 Units V 0.5 0.8 0.8 1.9 2.9 2.48 V VIN e VIL or VIH IOH e b50 mA IOH e b50 mA IOH e b4 mA VIN e VIL or VIH IOL e 50 mA IOL e 50 mA IOL e 4 mA V 0.1 0.1 0.36 0.1 0.1 0.44 V 3.6 g 0.1 g 1.0 mA VIN e 5.5V or GND 3.6 2.0 20.0 mA VIN e VCC or GND 4 Noise Characteristics LVX163 Symbol VCC (V) Parameter TA e 25§ C Units Typ Limits VOLP* Quiet Output Maximum Dynamic VOL 3.3 0.2 0.5 V VOLV* Quiet Output Minimum Dynamic VOL 3.3 b 0.2 b 0.5 V VIHD* Minimum High Level Dynamic Input Voltage 3.3 2.0 V VILD* Maximum Low Level Dynamic Input Voltage 3.3 0.8 V CL (pF) 50 50 50 50 *Parameter guaranteed by design. AC Electrical Characteristics Symbol Parameter VCC (V) LVX163 LVX163 TA e 25§ C TA e b40§ C to a 85§ C Min tPLH, tPHL Propagation Delay Time (CP–Qn) 2.7 3.3 g 0.3 tPLH, tPHL Propagation Delay Time (CP–TC, Count) 2.7 3.3 g 0.3 tPLH, tPHL Propagation Delay Time (CP–TC, Load) 2.7 3.3 g 0.3 tPLH, tPHL Propagation Delay Time (CET–TC) 2.7 3.3 g 0.3 fmax Maximum Clock Frequency 2.7 3.3 g 0.3 Units Conditions Typ Max Min Max 9.0 14.0 1.0 16.0 ns CL e 15 pF 11.3 17.0 1.0 19.0 CL e 50 pF 8.3 12.8 1.0 15.0 ns CL e 15 pF 10.8 16.3 1.0 18.5 CL e 50 pF 9.5 14.3 1.0 16.7 ns CL e 15 pF 12.5 18.5 1.0 20.5 CL e 50 pF 8.7 13.6 1.0 16.0 ns CL e 15 pF 11.2 17.1 1.0 19.5 11.4 18.0 1.0 21.0 ns CL e 15 pF 14.0 21.0 1.0 24.0 CL e 50 pF 11.0 17.2 1.0 20.0 ns CL e 15 pF 13.5 20.7 1.0 23.5 CL e 50 pF CL e 50 pF 8.6 13.5 1.0 15.0 ns CL e 15 pF 11.0 16.5 1.0 18.5 CL e 50 pF 7.5 12.3 1.0 14.5 ns CL e 15 pF 10.5 15.8 1.0 18.0 CL e 50 pF 75 115 65 MHz CL e 15 pF 50 80 45 CL e 50 pF 80 130 70 MHz CL e 15 pF 55 85 50 CIN Input Capacitance 4 CPD Power Dissipation Capacitance 23 10 CL e 50 pF 10 pF VCC e Open (Note 1) pF Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) e CPD * VCC * fIN a ICC. When the outputs drive a capacitive load, total current consumption is the sum of CPD, and DICC which is obtained from the following formula: DICC e FCP # VCC # CQO C C C C a Q1 a Q2 a Q3 a TC 2 4 8 16 16 J CQ0 –CQ3 and CTC are the capacitances at Q0–Q3 and TC, respectively. FCP is the input frequency of the CP. 5 http://www.national.com AC Operating Requirements Symbol Parameter VCC (V) LVX163 LVX163 TA e 25§ C TA e b40§ C to a 85§ C Units Conditions Guaranteed Minimum tS Minimum Setup Time (Pn –CP) 2.7 3.3 g 0.3 5.5 5.5 6.5 6.5 ns tS Minimum Setup Time (PE –CP) 2.7 3.3 g 0.3 8.0 8.0 9.5 9.5 ns tS Minimum Setup Time (CEP or CET–CP) 2.7 3.3 g 0.3 7.5 7.5 9.0 9.0 ns tS Minimum Setup Time (MR–CP) 2.7 3.3 g 0.3 4.0 4.0 4.0 4.0 ns tH Minimum Hold Time (Pn –CP) 2.7 3.3 g 0.3 1.0 1.0 1.0 1.0 ns tH Minimum Hold Time (PE –CP) 2.7 3.3 g 0.3 1.0 1.0 1.0 1.0 ns tH Minimum Hold Time (CEP or CET–CP) 2.7 3.3 g 0.3 1.0 1.0 1.0 1.0 ns tH Minimum Hold Time (MR–CP) 2.7 3.3 g 0.3 1.5 1.5 1.5 1.5 ns tW(L) tW(H) Minimum Pulse Width CP (Count) 2.7 3.3 g 0.3 5.0 5.0 5.0 5.0 ns Ordering Information The device number is used to form part of a simplified purchasing code, where the package type and temperature range are defined as follows: TL/F/12157 – 8 http://www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Molded JEDEC SOIC Order Number 74LVX163M NS Package Number M16A 16-Lead Molded EIAJ SOIC Order Number 74LVX163SJ NS Package Number M16D 7 http://www.national.com 74LVX163 Low Voltage Synchronous Binary Counter with Synchronous Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Molded JEDEC Type 1 TSSOP Order Number 74LVX163MTC NS Package Number MTC16 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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