QL3060 pASIC 3 FPGA Data Sheet •••••• 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 60,000 Usable PLD Gates with 316 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths • 0.35 µm four-layer metal non-volatile CMOS process for smallest die sizes Easy to Use / Fast Development Cycles • 100% routable with 100% utilization and complete pin-out stability • Variable-grain logic cells provide high performance and 100% utilization • Comprehensive design tools include high quality Verilog/VHDL synthesis Eight Low-Skew Distributed Networks • Two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs — each driven by an input-only pin • Six global clock/control networks available to the logic cell F1, clock set, and reset inputs and the input and I/O register clock, reset, and enable inputs as well as the output enable control — each driven by an inputonly or I/O pin, or any logic cell output or I/O cell feedback High Performance • Input + logic cell + output total delays under 6 ns • Data path speeds over 400 MHz • Counter speeds over 300 MHz Advanced I/O Capabilities • Interfaces with both 3.3 V and 5.0 V devices • PCI compliant with 3.3 V and 5.0 V buses for -1/-2/-3/-4 speed grades • Full JTAG boundary scan • I/O Cells with individually controlled Registered Input Path and Output Enables Total of 316 I/O Pins • 308 bidirectional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades • Eight high-drive input/distributed network pins Figure 1: 1,584 pASIC 3 Logic Cells © 2002 QuickLogic Corporation www.quicklogic.com • • • • • • 1 QL3060 pASIC 3 FPGA Data Sheet Rev D Architecture Overview The QL3060 is a 60,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3 FPGAs are fabricated on a 0.35 µm four-layer metal process using QuickLogic's patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The QL3060 contains 1,584 logic cells. With a maximum of 316 I/Os, the QL3060 is available in 208-PQFP and 456-pin PBGA packages. Software support for the complete pASIC 3 family, including the QL3060, is available through three basic packages. The turnkey QuickWorks package provides the most complete FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence, ExemplarTM, Mentor, Synopsys, Synplicity, ViewlogicTM, AldecTM, or other third-party tools for design entry, synthesis, or simulation. 2 • • • www.quicklogic.com • • • © 2002 QuickLogic Corporation QL3060 pASIC 3 FPGA Data Sheet Rev D Electrical Specifications AC Characteristics at VCC = 3.3 V, TA = 25°C (K = 1.00) To calculate delays, multiply the appropriate K factor from Table 7 by the numbers provided in Table 1 through Table 5. Table 1: Logic Cells Symbol tPD Propagation Delays (ns) Fanouta Parameter Combinatorial Delay b 1 2 3 4 8 1.4 1.7 1.9 2.2 3.2 tSU Setup Time b 1.7 1.7 1.7 1.7 1.7 tH Hold Time 0.0 0.0 0.0 0.0 0.0 tCLK Clock to Q Delay 0.7 1.0 1.2 1.5 2.5 tCWHI Clock High Time 1.2 1.2 1.2 1.2 1.2 tCWLO Clock Low Time 1.2 1.2 1.2 1.2 1.2 tSET Set Delay 1.0 1.3 1.5 1.8 2.8 tRESET Reset Delay 0.8 1.1 1.3 1.6 2.6 tSW Set Width 1.9 1.9 1.9 1.9 1.9 tRW Reset Width 1.8 1.8 1.8 1.8 1.8 a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 7. b. These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. Table 2: Input-Only/Clock Cells Symbol Propagation Delays (ns) Fanout a Parameter 1 2 3 4 8 12 24 tIN High Drive Input Delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 tINI High Drive Input, Inverting Delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 tISU Input Register Set-Up Time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 tIH Input Register Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 tlCLK Input Register Clock To Q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 tlRST Input Register Reset Delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 tlESU Input Register clock Enable Set-Up Time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 tlEH Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 7. • © 2002 QuickLogic Corporation www.quicklogic.com •• • • • 3 QL3060 pASIC 3 FPGA Data Sheet Rev D Table 3: Clock Cells Symbol Propagation Delays (ns) Loads per Half Column a Parameter 1 2 3 4 8 10 11 tACK Array Clock Delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 tGCKP Global Clock Pin Delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 tGCKB Global Clock Buffer Delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 a. The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to eight loads per half column. The global clock has up to 11 loads per half column. Table 4: Input-Only I/O Cells Symbol Parameter Propagation Delays (ns) Fanout a 1 2 3 4 8 10 tI/O Input Delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 tISU Input Register Set-Up Time 3.1 3.1 3.1 3.1 3.1 3.1 tIH Input Register Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 tlOCLK Input Register Clock To Q 0.7 1.0 1.2 1.5 2.5 3.0 tlORST Input Register Reset Delay 0.6 0.9 1.1 1.4 2.4 2.9 tlESU Input Register clock Enable Set-Up Time 2.3 2.3 2.3 2.3 2.3 2.3 tlEH Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 7. 4 • • • www.quicklogic.com • • • © 2002 QuickLogic Corporation QL3060 pASIC 3 FPGA Data Sheet Rev D Table 5: Output-Only I/O Cells Symbol Propagation Delays (ns) Output Load Capacitance (pF) Parameter 30 50 75 100 150 tOUTLH Output Delay Low to High 2.1 2.5 3.1 3.6 4.7 tOUTHL Output Delay High to Low 2.2 2.6 3.2 3.7 4.8 tPZH Output Delay Tri-state to High 1.2 1.7 2.2 2.8 3.9 tPZL Output Delay Tri-state to Low 1.6 2.0 2.6 3.1 4.2 tPHZ Output Delay High to Tri-State 2.0 - - - - tPLZ Output Delay Low to Tri-State 1.2 - - - - a a. The loads presented in Figure 2 are used for tPXZ: tPHZ 1ΚΩ 5 pF 1ΚΩ tPLZ 5 pF Figure 2: Loads used for tPXZ • © 2002 QuickLogic Corporation www.quicklogic.com •• • • • 5 QL3060 pASIC 3 FPGA Data Sheet Rev D DC Characteristics The DC specifications are provided in Table 6 through Table 8. Table 6: Absolute Maximum Ratings Parameter Value Parameter Value VCC Voltage -0.5 V to 4.6 V DC Input Current ±20 mA VCCIO Voltage -0.5 V to 7.0 V ESD Pad Protection ±2000 V Input Voltage -0.5 V to VCCIO +0.5 V Storage Temperature -65°C to +150°C Latch-up Immunity ±200 mA Lead Temperature 300°C Table 7: Operating Range Symbol Military Industrial Commercial Unit Min Max Min Max Min Max Supply Voltage 3.0 3.6 3.0 3.6 3.0 3.6 V I/O Input Tolerance Voltage 3.0 5.5 3.0 5.5 3.0 5.25 V TA Ambient Temperature -55 - -40 85 0 70 °C TC Case Temperature - 125 - - - - °C -0 Speed Grade - - 0.43 1.90 0.46 1.85 n/a -1 Speed Grade 0.42 1.64 0.43 1.54 0.46 1.50 n/a -2 Speed Grade 0.42 1.37 0.43 1.28 0.46 1.25 n/a -3 Speed Grade 0.43 0.90 0.46 0.88 n/a -4 Speed Grade 0.43 0.82 0.46 0.80 n/a VCC VCCIO K 6 Parameter • • • www.quicklogic.com • • • Delay Factor © 2002 QuickLogic Corporation QL3060 pASIC 3 FPGA Data Sheet Rev D Table 8: DC Characteristics Symbol Parameter Conditions Min Max Units VIH Input HIGH Voltage 0.5 VCC VCCIO+0.5 V VIL Input LOW Voltage -0.5 0.3 VCC V VOH Output HIGH Voltage VOL Output LOW Voltage IOH = -12 mA 2.4 V IOH = -500 µA 0.9 VCC V IOL = 16 mAa 0.45 V IOL = 1.5 mA 0.1 VCC V II I or I/O Input Leakage Current VI = VCCIO or GND -10 10 µA IOZ 3-State Output Leakage Current VI = VCCIO or GND -10 10 µA CI Input Capacitanceb 10 pF IOS Output Short Circuit Currentc ICC ICCIO D.C. Supply Current d D.C. Supply Current on VCCIO VO = GND -15 -180 mA VO = VCC 40 210 mA VI, VIO = VCCIO or GND 0.50 (typ) 2 mA 0 100 µA a. Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All other devices have 8 mA IOL specifications. b. Capacitance is sample tested only. Clock pins are 12 pF maximum. c. Only one output at a time. Duration should not exceed 30 seconds. d. For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all industrial grade devices. and 5 mA for all military grade devices. For AC conditions, contact QuickLogic customer applications group (see Contact Information). • © 2002 QuickLogic Corporation www.quicklogic.com •• • • • 7 QL3060 pASIC 3 FPGA Data Sheet Rev D Kv and Kt Graphs Voltage Factor vs. Supply Voltage 1.1000 1.0800 1.0600 Kv 1.0400 1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 3 3.1 3.2 3.3 3.4 3.5 3.6 Supply Voltage (V) Figure 3: Voltage Factor vs. Supply Voltage Temperature Factor vs. Operating Temperature 1.15 1.10 1.05 Kt 1.00 0.95 0.90 0.85 -60 -40 -20 0 20 40 60 80 Junction Temperature C Figure 4: Temperature Factor vs. Operating Temperature 8 • • • www.quicklogic.com • • • © 2002 QuickLogic Corporation QL3060 pASIC 3 FPGA Data Sheet Rev D Power-up Sequencing Voltage VCCIO VCC (VCCIO -VCC)MAX VCC 400 us Time Figure 5: Power-up Requirements The following requirements must be met when powering up the device (refer to Figure 5): • When ramping up the power supplies keep (VCCIO -VCC)MAX ≤ 500 mV. Deviation from this recommendation can cause permanent damage to the device. • VCCIO must lead VCC when ramping the device. • The power supply must take greater than or equal to 400 µs to reach VCC. Ramping to VCC/VCCIO earlier than 400 µs can cause the device to behave improperly. An internal diode is present in-between VCC and VCCIO, as shown in Figure 6. V CC Internal Logic Cells, RAM blocks, etc V CCIO IO Cells Figure 6: Internal Diode Between VCC and VCCIO • © 2002 QuickLogic Corporation www.quicklogic.com •• • • • 9 QL3060 pASIC 3 FPGA Data Sheet Rev D JTAG TCK TMS TAp Controller State Machine (16 States) Instruction Decode & Control Logic TRSTB Instruction Register RDI Mux Mux TDO Boundary-Scan Register (Data Register) Bypass Register Internal Register I/O Registers User Defined Data Register Figure 7: JTAG Block Diagram Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not the least of which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR); these allow users to run three required tests, along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. 10 • • • www.quicklogic.com • • • © 2002 QuickLogic Corporation QL3060 pASIC 3 FPGA Data Sheet Rev D The 1149.1 standard requires the following three tests: • Extest Instruction. The Extest instruction performs a PCB interconnect test. This test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. • Sample/Preload Instruction. This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. • Bypass Instruction. The Bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device. • © 2002 QuickLogic Corporation www.quicklogic.com •• 11 • • • QL3060 pASIC 3 FPGA Data Sheet Rev D Pin Descriptions Table 9: Pin Descriptions Pin Function Description TDI Test Data In for JTAG Hold HIGH during normal operation. Connect to VCC if not used for JTAG. TRSTB Active low Reset for JTAG Hold LOW during normal operation. Connect to ground if not used for JTAG. TMS Test Mode Select for JTAG Hold HIGH during normal operation. Connect to VCC if not used for JTAG. TCK Test Clock for JTAG Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. TDO Test data out for JTAG STM Special Test Mode Output that must be left unconnected if not used for JTAG. Must be grounded during normal operation. I/ACLK High-drive input and/or array Can be configured as either or both. network driver I/GCLK High-drive input and/or global Can be configured as either or both. network driver I High-drive input Use for input signals with high fanout. I/O Input/Output pin Can be configured as an input and/or output. VCC Power supply pin Connect to 3.3 V supply. VCCIO Input voltage tolerance pin GND Ground pin Connect to 5.0 V supply if 5 V input tolerance is required, otherwise connect to 3.3 V supply. Connect to ground. Ordering Information QL 3060 - 1 PQ208 C QuickLogic device pASIC 3 device part number Speed Grade 0 = Quick 1 = Fast 2 = Faster 3 = Faster *4 = Wow Operating Range C = Commercial I = Industrial M = Military Package Code PQ208 = 208-pin PQFP PB456 = 456-pin PBGA * Contact QuickLogic regarding availability (see Contact Information) 12 • • • www.quicklogic.com • • • © 2002 QuickLogic Corporation QL3060 pASIC 3 FPGA Data Sheet Rev D 208 PQFP Pinout Diagram Pin 157 Pin 1 pASIC 3 QL3060-1PQ208C Pin 53 Pin 105 Figure 8: Top View of 208 Pin PQFP • © 2002 QuickLogic Corporation www.quicklogic.com •• 13 • • • QL3060 pASIC 3 FPGA Data Sheet Rev D 208 PQFP Pinout Table Table 10: 208 PQFP Pinout Table 14 • • • www.quicklogic.com • • • 208 PQFP Function 208 PQFP Function 208 PQFP Function 208 PQFP Function 208 PQFP Function 208 I/O 43 GND 84 I/O 125 I/O 168 I/O 1 I/O 44 I/O 85 I/O 126 I/O 169 I/O 2 I/O 45 I/O 86 I/O 127 GND NC I/O 3 I/O 46 I/O 87 I/O 128 I/O 170 I/O 4 I/O 47 I/O 88 I/O NC I/O 171 I/O 5 I/O 48 I/O 89 I/O 129 GCLK / I 172 I/O NC I/O NC I/O 90 I/O 130 ACLK / I 173 I/O 6 I/O 49 I/O 91 I/O 131 VCC 174 I/O 7 I/O 50 I/O 92 I/O 132 GCLK / I 175 I/O 8 I/O 51 I/O NC I/O 133 GCLK / I NC I/O 9 I/O 52 I/O 93 I/O 134 VCC 176 I/O 10 VCC 53 I/O 94 I/O 135 I/O 177 GND 11 I/O 54 TDI 95 GND 136 I/O 178 I/O 12 GND NC I/O 96 I/O NC I/O 179 I/O 13 I/O NC I/O 97 VCC 137 I/O NC I/O 14 I/O 55 I/O 98 I/O NC GND 180 I/O NC I/O 56 I/O 99 I/O 138 I/O 181 I/O 15 I/O NC I/O 100 I/O 139 I/O 182 GND 16 I/O 57 I/O NC I/O 140 I/O NC VCC 17 I/O 58 I/O 101 I/O 141 I/O 183 I/O 18 I/O 59 GND NC I/O 142 I/O 184 I/O 19 I/O 60 I/O 102 I/O NC I/O 185 I/O 20 I/O 61 VCC NC I/O 143 I/O 186 I/O NC I/O 62 I/O NC I/O 144 I/O 187 VCCIO 21 I/O 63 I/O 103 TRSTB 145 VCC 188 I/O 22 I/O 64 I/O 104 TMS NC I/O NC I/O 23 GND NC I/O 105 I/O 146 I/O 189 I/O 24 I/O 65 I/O NC I/O 147 GND 190 I/O 25 GCLK / I 66 I/O 106 I/O 148 I/O 191 I/O 26 ACLK / I 67 I/O 107 I/O 149 I/O 192 I/O 27 VCC NC I/O 108 I/O 150 I/O 193 I/O 28 GCLK / I 68 I/O 109 I/O 151 I/O 194 I/O 29 GCLK / I 69 I/O NC I/O 152 I/O NC I/O 30 VCC 70 I/O 110 I/O 153 I/O 195 I/O 31 I/O NC I/O 111 I/O 154 I/O 196 I/O 32 I/O 71 I/O 112 I/O 155 I/O 197 I/O NC GND NC I/O 113 I/O 156 I/O 198 I/O 33 I/O 72 I/O 114 VCC 157 TCK NC I/O NC I/O 73 GND 115 I/O 158 STM 199 GND 34 I/O 74 I/O 116 GND NC I/O 200 I/O 35 I/O NC VCC 117 I/O 159 I/O 201 VCC 36 I/O 75 I/O NC I/O 160 I/O 202 I/O NC I/O 76 I/O 118 I/O 161 I/O 203 I/O 37 I/O 77 I/O 119 I/O 162 I/O 204 I/O 38 I/O 78 GND 120 I/O 163 GND 205 I/O 39 I/O 79 I/O 121 I/O 164 I/O 206 I/O NC I/O 80 I/O NC I/O 165 VCC 207 TDO 40 I/O 81 I/O 122 I/O 166 I/O 41 VCC 82 I/O 123 I/O NC 42 I/O 83 VCCIO 124 I/O 167 I/O I/O © 2002 QuickLogic Corporation QL3060 pASIC 3 FPGA Data Sheet Rev D 456 PBGA Pinout Diagram pASIC 3 QL3060-1PB456C BOTTOM View PIN A1 CORNER 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Figure 9: 456-Pin PBGA Pinout Diagram • © 2002 QuickLogic Corporation www.quicklogic.com •• 15 • • • QL3060 pASIC 3 FPGA Data Sheet Rev D 456 PBGA Pinout Table Table 11: 456 PBGA Pinout Table 456 Function 456 Function 456 Function 456 Function 456 Function A1 I/O B26 STM D25 I/O H4 I/O M14 GND/THERM A2 I/O C1 I/O D26 I/O H5 NC M15 GND/THERM A3 I/O C2 I/O E1 I/O H22 NC M16 GND/THERM A4 I/O C3 I/O E2 I/O H23 I/O M22 NC A5 I/O C4 TDO E3 I/O H24 I/O M23 NC A6 I/O C5 I/O E4 I/O H25 I/O M24 I/O A7 I/O C6 I/O E5 GND H26 I/O M25 I/O A8 I/O C7 I/O E6 VCC J1 I/O M26 I/O A9 I/O C8 I/O E7 GND J2 I/O N1 GCLK/I A10 I/O C9 I/O E8 NC J3 I/O N2 I/O A11 I/O C10 I/O E9 GND J4 NC N3 I/O A12 VCCIO C11 I/O E10 I/O J5 GND N4 GCLK/I A13 I/O C12 I/O E11 GND J22 NC N5 VCC A14 I/O C13 I/O E12 GND J23 NC N11 GND/THERM A15 I/O C14 I/O E13 VCC J24 I/O N12 GND/THERM A16 I/O C15 I/O E14 GND J25 I/O N13 GND/THERM A17 I/O C16 I/O E15 GND J26 I/O N14 GND/THERM A18 I/O C17 I/O E16 GND K1 I/O N15 GND/THERM A19 I/O C18 I/O E17 NC K2 I/O N16 GND/THERM A20 I/O C19 I/O E18 GND K3 I/O N22 GND A21 I/O C20 I/O E19 NC K4 I/O N23 I/O A22 I/O C21 I/O E20 GND K5 VCC N24 I/O A23 I/O C22 I/O E21 VCC K22 GND N25 I/O A24 I/O C23 I/O E22 GND K23 I/O N26 I/O A25 I/O C24 I/O E23 I/O K24 I/O P1 I/O A26 I/O C25 TCK E24 I/O K25 I/O P2 I/O B1 I/O C26 I/O E25 I/O K26 I/O P3 I/O B2 I/O D1 I/O E26 I/O L1 I/O P4 I/O B3 I/O D2 I/O F1 I/O L2 I/O P5 NC B4 I/O D3 I/O F2 I/O L3 I/O P11 GND/THERM B5 I/O D4 GND F3 I/O L4 I/O P12 GND/THERM B6 I/O D5 I/O F4 NC L5 NC P13 GND/THERM B7 I/O D6 NC F5 VCC L11 GND/THERM P14 GND/THERM B8 I/O D7 I/O F22 VCC L12 GND/THERM P15 GND/THERM B9 I/O D8 I/O F23 NC L13 GND/THERM P16 GND/THERM B10 I/O D9 GND F24 I/O L14 GND/THERM P22 NC B11 I/O D10 I/O F25 I/O L15 GND/THERM P23 GCLK / I B12 I/O D11 I/O F26 I/O L16 GND/THERM P24 GCLK / I B13 I/O D12 GND G1 I/O L22 NC P25 I/O B14 I/O D13 I/O G2 I/O L23 I/O P26 ACLK / I B15 I/O D14 I/O G3 I/O L24 I/O R1 I/O B16 I/O D15 GND G4 I/O L25 I/O R2 I/O B17 I/O D16 I/O G5 NC L26 I/O R3 I/O B18 I/O D17 I/O G22 GND M1 ACLK / I R4 NC B19 I/O D18 GND G23 I/O M2 GCLK/I R5 NC B20 I/O D19 I/O G24 I/O M3 I/O R11 GND/THERM B21 I/O D20 I/O G25 I/O M4 NC R12 GND/THERM B22 I/O D21 NC G26 I/O M5 GND R13 GND/THERM B23 I/O D22 I/O H1 I/O M11 GND/THERM R14 GND/THERM B24 I/O D23 GND H2 I/O M12 GND/THERM R15 GND/THERM B25 I/O D24 I/O H3 I/O M13 GND/THERM R16 GND/THERM (Sheet 1 of 2) 16 • • • www.quicklogic.com • • • © 2002 QuickLogic Corporation QL3060 pASIC 3 FPGA Data Sheet Rev D Table 11: 456 PBGA Pinout Table (Continued) 456 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 Function VCC NC I/O I/O GCLK / I I/O I/O I/O I/O VCC GND/THERMAL GND/THERMAL GND/THERMAL GND/THERMAL GND/THERMAL GND/THERMAL GND I/O I/O I/O I/O I/O I/O I/O I/O GND NC I/O I/O I/O I/O I/O I/O I/O NC NC GND NC I/O I/O I/O 456 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 Function I/O I/O I/O I/O NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O NC NC VCC VCC NC I/O I/O I/O I/O I/O I/O I/O GND VCC NC NC NC VCC GND 456 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 Function NC I/O GND VCC I/O NC VCC GND NC VCC GND I/O I/O I/O I/O I/O I/O NC GND I/O NC I/O I/O NC I/O I/O NC I/O VCCIO NC I/O I/O NC I/O I/O I/O NC GND I/O I/O I/O 456 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 Function I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 456 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Function I/O I/O I/O I/O I/O I/O I/O NC TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (Sheet 2 of 2) • © 2002 QuickLogic Corporation www.quicklogic.com •• 17 • • • QL3060 pASIC 3 FPGA Data Sheet Rev D 456 PBGA Mechanical Drawing Figure 10: 456 PBGA Mechanical Drawing 18 • • • www.quicklogic.com • • • © 2002 QuickLogic Corporation QL3060 pASIC 3 FPGA Data Sheet Rev D Contact Information Telephone: 408 990 4000 (US) 416 497 8884 (Canada) 44 1932 57 9011 (Europe) 49 89 930 86 170 (Germany) 852 8106 9091 (Asia) 81 45 470 5525 (Japan) E-mail: [email protected] Support: [email protected] Web site: http://www.quicklogic.com/ Revision History Table 12: Revision History Revision Date Comments A not avail. First release. B not avail. C May 2001 Update of AC/DC Specs and reformat D June 2002 Added Kfactor, Power-up, JTAG and mechanical drawing information. Reformatted. Copyright Information Copyright © 2002 QuickLogic Corporation. All Rights Reserved. The information contained in this product brief, and the accompanying software programs are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to make periodic modifications of this product without obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic, QuickWorks, pASIC, and ViaLink are registered trademarks of QuickLogic Corporation. Verilog is a registered trademark of Cadence Design Systems, Inc. All trademarks and registered trademarks are the property of their respective owners. • © 2002 QuickLogic Corporation www.quicklogic.com •• 19 • • •