100MHz~500MHz FSPLL BW2006L DECEMBER 1998. Ver1.0 Features General Description The BW2006L is a Phase Locked Loop (PLL) Clock . 0.35u CMOS device technology frequency synthesizer constructed in CMOS on a single . Single power supply 3.3V monolithic structure. . Output frequency range: 100~500MHz The device's PLL macro functions provide frequency . Jitter ¡¾80ps multiplication capabilities. The output clock frequency FOUT is related to the input . Output Duty ratio 40% to 60% clock frequency FIN by FOUT=m*8*FIN/p*s. . Input Duty ratio 40% to 60% BW2006L consists of a Phase/Frequency Detector (PFD), a charge pump, . Frequency changed by programmable dividers external loop filter, and a Voltage Controlled Oscillator(VCO), pre-divider(6bit), . Input frequency range: 10MHz¡ÂFIN¡Â50MHz main divider(6bit), post scaler(2bit) as shown in the block . Power Down mode diagram. FUNCTIONAL BLOCK DIAGRAM VDD VSS M<5:0> P<5:0> FILTER MAIN DIVIDER by M FIN PRE DIVIDER by P PFD 1/8 Charge VCO Pump POST SCALER by S Loop Filter VBB External PWRDN VDDA VSSA FOUT VSUB S<1:0> Figure1 . functional blcok diagram BW2006L 100MHz~500MHz FSPLL CORE PIN DESCRIPTION NAME I/O TYPE I/O PAD PIN DESCRIPTION VDD DP vddd Digital power supply VSS DG vssd Digital ground VDDA AP vdda Analog power supply VSSA AG vssa Analog ground VBB/VSUB AG vbba Substrate ground FIN DI picc_bb FILTER AO poa50r_bb FOUT DO pot12_bb or Special Buffer PLL clock input . Pump out is connected to Filter . A capacitor is connected between the pin and analog ground 100MHz~500MHz clock output need special drive buffer PWRDN AI picc_bb PLL power down.(Active High) -If isn't used this pin, tied to VSSA. P[5:0] DI picc_bb The values for 6bit programmable pre-divider. M[5:0] DI picc_bb The values for 6bit programmable main divider. S[1:0] DI picc_bb The values for 2bit programmable post scaler. I/O TYPE ABBR. AI : Analog Input DI : Digital Input AO : Analog Output DO : Analog Output AP AG AB DP DG DB : : : : : : Analog Power Analog Ground Analog Sub Bias Digital Power Digital Ground Digital Sub Bias BD : Bidirectional Port CORE CONFIGURATION FOUT FIN PWRDN M[5:0] M[0] M[1] M[2] M[3] M[4] M[5] P[5:0] P[0] P[1] P[2] P[3] P[4] P[5] S[1:0] S[0] S[1] Figure2. FILTER BW2006L Core configuration BW2006L 100MHz~500MHz FSPLL Absolute Maximum Ratings (Ta=25oC) Characteristics Symbol Unit DC Supply Voltage VDD / VDDA -0.3 to 3.8 V DC Input Voltage VIN -0.3 to VDD+0.3 V Storage Temperature TSTG -40 to 125 o C NOTE : 1. Absolute Maximum Rating specifies the values beyond which the device may be damaged permanently. Exposure to Absolute Maximum Rating conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5Kohm resistor(Human Body Model) Recommended Operating Conditions Characteristics Symbol VDD Supply Voltage VDDA Min Typ Max Unit 3.15 3.3 3.45 V Supply Voltage Difference VDD-VDDA -0.1 +0.1 V Reference Input frequency FIN 10 50 MHz External Loop Filter Capacitance LF Operating Temperature TOPR 300 pF 0 70 o C NOTE : It is strongly recommended that the supply pins(VDDA,VDD) be powered from the seperated sources. Electrical DC Characteristics (PLL Specifications : VDDA/VDD=3.3V +/-5%, VSS/VSSA/VBB/VSUB=0V) Characteristics Symbol Min Typ Max Unit Operating Voltage VDD/VDDA 3.15 3.3 3.45 V Dynamic Current @500MHz IDD Power Down Current IPD 10 mA 100 uA Max Unit Electrical AC Characteristics (PLL Specifications : VDDA/VDD=3.3V +/-5%, VSS/VSSA/VBB/VSUB=0V) Characteristics Symbol Min Typ Output Clock Frequency FOUT 100 500 MHz Output Clock Duty Ratio TOD 40 60 % Input Clock Duty Ratio TID 40 60 % Lock-In Time Tl 150 us Cycle to Cycle Jitter Tj +/-80 ps BW2006L 100MHz~500MHz FSPLL Functional Description A PLL is circuit synchronizing an feedback signal (divided down after generated by an VCO) with a reference or input signal in frequency as well as phase. In this application, it includes following basic blocks. . A voltage-controlled oscillator to generate the output frequency . A divider P to devide down the reference frequency by p . A divider M to devide down the VCO output frequency by m . A divider S to divide down the VCO output frequency by s . A phase detector to detect the phase difference between the reference frequency and the output frequency (after divide down) and control the charge pump voltage. . A loop filter to filter out the high frequency in charge pump voltage and give smooth and clean control to VCO The m, p, s values can be programmed by 14bit digital data from the external source. So, the PLL can be locked in the frequency we want. FOUT = m *8* FIN / p*s Where, m=M+2 , p=P+2, s=2^S NOTES . S1 - S0 : Output Frequency Scaler . M5 - M0 : VCO Frequency Divider . P5 - P0 : Reference Frequency Input Divider Main Divider Pin Pre Divider Pin Post Scaler Pin M5,M4,M3,M2,M1,M0 P5,P4,P3,P2,P1,P0 S0,S1 BW2006L 100MHz~500MHz FSPLL CORE EVALUATION GUIDE For the embedded PLL, we must consider the test circuits for the embedded PLL core in multiple applications. Hence, the following requirements should be satisfied. - The FILTER and FOUT pins must be provided for test. - For PLL test (Below 2 examples), it is needed to control the dividers - M<5:0>,P<5:0> and S<1:0> -that generate multiple clocks. #1. Registers can be used for easy control of divider values. #2. N sample bits of 14-bit divider pins can be bypassed for test using MUX. 3.3V Digital Power External Source Clock 3.3V Analog Power GND GND FIN VDD VSS VDDA VSSA VBB FOUT PWRDN BW2006L M<5:0> #1.14bit Register Block FILTER P<5:0> 300pF S<1:0> VSSA Select Pin Test Pins of N Sample bits (used to primary pad cells) Internal Divider Signal Line #2 M U X NOTES : 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 103 CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED Figure3 . Core evaluation guide BW2006L 100MHz~500MHz FSPLL PACKAGE CONFIGURATION (48QFP) 2bit Post Scaler 3.3V Digital PAD Power L L H H 3.3V PAD Power C C 36 35 34 33 32 31 30 29 28 27 26 25 V D D V D D V S S V S S S 0 S 1 N C N C V D D P V S S P F O U T N C NC 24 38 P4 NC 23 H 39 P3 NC 22 L H 40 P2 NC 21 L H 41 P1 VBB 20 L H 42 P0 VBB 19 L H 37 P5 L H L 6bit Pre-Divider BW2006L C 43 NC PWRDN 18 103 10uF 44 NC 16 L H 45 M0 NC L H 46 M1 FIN 15 L H 47 M2 VDDA 14 L H 48 M3 6bit Divider Main M 4 M 5 N C N C N C 1 2 3 4 5 H H L L N C 6 N C 7 300pF FILTER 17 N C 8 N C 9 N C V S S A 13 VDDA V S S A 10 11 12 *Package Pin Name and Functions are Same to Core Pin Description(Refer to Page 2) *NC : No Connection Figure4 . Package configuration 3.3V Analog Power C 100MHz~500MHz FSPLL BW2006L Design Considerations The following design considerations are applied : * Phase tolerance and jitter are independent of the PLL frequency. * Jitter is affected by the noise frequency in the power(VDD/VSS,VDDA/VSSA/VSUB and VBB) . It increases when noise level increases. * A CMOS-level input reference clock is recommended for signal compatibility with the PLL circuit. Other levels such as TTL may degrade the tolerances. * The use of two, or more PLLs requires special design considerations. Please consult your application engineer for more information. * The following apply to the noise level, which can be minimized by using good analog power and ground isolation techniques in the system: - Use wide PCB traces for POWER(VDD/VSS, VDDA/VSSA/VSUB and VBB) connections to the PLL core. Seperate the traces from the chip's VDD/VSS,VDDA/VSSA/VSUB and VBB supplies. - Use proper VDD/VSS,VDDA/VSSA/VSUB and VBB decoupling. - Use good power and ground sources on the board . - Use Power VBB(=VSUB) to minimize substrate noise. * The PLL core should be placed as close as possible to the dedicated loop filter and analog Power and ground pins. * It is inadvisable to locate noise-generating signals, such as data busses and high-current outputs, near the PLL I/O cells. * Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined placement restriction. BW2006L 100MHz~500MHz FSPLL PLL Specification We appreciate your interest in our products. If you have further questions, please specify in the attached form. Thank you very much. Parameter Min Typ Max Unit Remarks Supply Voltage Output frequency range Input frequency range Cycle to Cycle Jitter Lock up time Dynamic current Stand by current Output clock duty ratio Long term jitter Output slew rate - Do you need XTAL driver buffer in PLL Core? If you need it, what's the crystal frequency range? If not, What's the input frequency range? - Do you need the lock detector? Do you need the I/O cell of SEC? Do you need the external pin for PLL test? What's the main frequency & frequency range? How many FSPLLs do you use in your system? What's output loading? Could you external/internal pin configurations as required? Specially requested function list :