25MHz ~ 300MHz FSPLL PLL2026X February 2000 V2.0 General Description Features The PLL2026X is a Phase-Locked Loop (PLL) frequency synthesizer • 0.25um CMOS process technology constructed in CMOS process technology. The PLL macrofunctions • 2.5 Volt Single power supply provide frequency multiplication capabilities.The output clock frequency Fout is related to the reference input clock frequency, by the follwing • Output frequency range: 25MHz~300 MHz equation: • Cycle-to-cycle jitter: ±…100ps Fout=( m*Fin ) / ( p*s ) • Output Duty ratio: 40% to 60% where Fout is the output clock frequency. Fin is the reference input clock frequency. m,p and s are the values for programmable dividers. • Input Duty ratio: 30% to 70% PLL2026X consists of a Phase/Frequency Detector(PFD), a Charge Pump an External Loop Filter, a Voltage Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as • Frequency changed by programmable divider • Power down mode • Lock Detector mode shown in Figure 1. FUNCTIONAL BLOCK DIAGRAM LDT LD FIN Pre Divider PFD P Charge Pump VCO Post Scaler FOUT S FILTER Main Divider M PWRDN P[5]~P[0] M[7]~M[0] S[1],S[0] AVDD25A AVSS25A AVDD25D AVSS25D Figure 1. Functional Block Diagram 1 / 6 AVBB25 PLL2026X 25MHz~300MHz FSPLL SYMBOL PIN DESCRIPTION NAME I/O TYPE PIN DESCRIPTION AVDD25D DP Digital power supply AVSS25D DG Digital ground AVDD25A AP Analog power supply AVSS25A AG Analog ground AVBB25 AG Substrate ground FIN DI External Clock input FILTER AO . Pump out is connected to Filter . A capacitor and 2 resistor are connected between the pin and analog ground LDT DO Lock Detector output. High(locking state) FOUT DO 25MHz~300MHz clock output I/O TYPE ABBR. ¡¤ AI : Analog Input ¡¤ DI : Digital Input ¡¤ AO : Analog Output ¡¤ DO : Analog Output ¡¤ AP ¡¤ AG ¡¤ AB ¡¤ DP ¡¤ DG ¡¤ DB FSPLL clock power down. -If PWRDN is High, PLL does not operate under this condition. -If not used, tie it to VSS. PWRDN DI P[5:0] DI The values for 6bit programmable pre-divider. M[7:0] DI The values for 8bit programmable main divider. S[1:0] DI The values for 2bit programmable post scaler. : : : : : : Analog Power Analog Ground Analog Sub Bias Digital Power Digital Ground Digital Sub Vias ¡¤ BD : Bidirectional Port SYMBOL CONFIGURATION AVDD25D FIN Ž PWRDN Ž Ž Ž Ž Ž Ž Ž Ž Ž Ž Ž Ž Ž Ž Ž Ž Ž M[0] M[1] M[2] M[3] M[4] M[5] M[6] M[7] P[0] P[1] P[2] P[3] P[4] P[5] S[0] S[1] AVSS25D PLL2026X Ž LDT Ž FOUT Ž FILTER AVDD25A AVDD25A AVBB25 Figure 2. Symbol Configuration SEC ASIC 2 / 6 ANALOG PLL2026X 25MHz~300MHz FSPLL ABSOLUTE MAXIMUM RATINGS (Ta=25°C) Characteristics DC Supply Voltage Symbol AVDD25D Value Unit -0.3 to +3.0 V Applicable pin AVDD25A,AVSS25A,AVDD25D AVDD25A AVSS25D,AVBB25 P[5:0],M[7:0]S[1:0] DC Input Voltage VIN Vss-0.25 to Vdd+0.25 V Storage Temperature TSTG -40 to 125 °C PWRDN,LDT - NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5§Ú resistor (Human body model) Recommended Operating Conditions Characteristics Symbol AVDD25D Supply Voltage AVDD25A Oscillator Frequency *External Loop Filter Capacitance-1 Min Typ Max Unit 2.375 2.5 2.625 V FIN 14.318 MHz C1 680 pF C2 39 pF R1 8 Kilo-ohm (Refer to Board Application Methodology) *External Loop Filter Capacitance-2 (Refer to Board Application Methodology) *External Loop Filter Resistance (Refer to Board Application Methodology) Operating Temperature TOPR 0 70 °C NOTES 1. It is strongly recommended that all the supply pins (AVDD25A, AVDD25D) be powered from the same source to avoid power latch-up. Filter Pin Board Application Methodology External Pin PLL Core R1 8 §Ú C2 C1 39pF 680pF Custom Chip VSSA Figure 3. Board Application of Filter pin SEC ASIC 3 / 6 ANALOG PLL2026X 25MHz~300MHz FSPLL DC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit DC Supply Voltage AVDD25D/AVDD25A 2.2 2.5 3.0 V DC Input Voltage High VIH 1.6 DC Input Voltage Low VIL 0.6 V Dynamic Current @300MHz IDD 3.1 mA Power Down Current IPD 100 uA V AC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit Input Frequency FIN 8 14.318 40 MHz Output Clock Frequency FOUT 25 300 MHz Output Clock Duty Ratio TOD 40 60 % Input Clock Duty Ratio TID 30 70 % Lock-in Time TLT Cycle to Cycle Jitter TJCC 50 100 us -100 +100 ps Functional Description A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference signal in frequency as well as in phase. In this application, it includes the following basic blocks. . The voltage-controlled oscillator to generate the output frequency. . The divider P to divide the reference frequency by p. . The divider M to divide the VCO output frequency by m. . The divider S to divide the VCO output frequency by s. . The phase frequency detector to detect the phase difference between the reference frequency and the output frequency (after division) and to control the charge pump voltage. . The loop filter to filter out high frequency components in charge pump voltage and give smooth and clean control to VCO. The m, p, s values can be programmed by 16bit digital data from the external source. So the PLL can be locked onto the desired frequency. Fout = ( m * Fin ) / ( p*s ) Fin = 14.318MHz, m=M+8 , p=P+2, s=2^S Digital data format: Main Divider Pre Divider Post Scaler M[7],M[6],M[5],M[4],M[3],M[2],M[1],M[0] P[5],P[4],P[3],P[2],P[1],P[0] S[0],S[1] NOTES . S[1] - S[0] : Output Frequency Scaler . M[7] - M[0] : VCO Frequency Divider . P[5] - P[0] : Reference Frequency Input Divider SEC ASIC 4 / 6 ANALOG PLL2026X 25MHz~300MHz FSPLL DESIGN and CORE LAYOUT GUIDE • Dedicated power pins, guard bars • Neighboring circuitry pads • Created white space between the PLL and all other circuits • Don't place noisy, high frequency and high power cells near the PLL • Closely placed Loop Filter components • Analog signals should not be crossed by digital signals and should not run next to digital signals. This will minimize the capacitive coupling between the two signals • Power cuts are required to provide on-chip isolation => between dedicated PLL power/ground and all other power/ground • Use proper low jitter refernce clock • The external loop filter pin is placed between the analog power to avoid stray coupling outside the chip and magnetic coupling via board wires • Solid Group plane • Use proper power/ground de-coupling • Use good power and ground source on the board • Use wide PCB traces for analog power/ground connections to the PLL core • Separate the traces from the chip's power/ground supplies FOUT FILTER AVDD25A AVSS25A FIN FILTER FIN Divider P PFD &CP LF VCO LD LDT Scaler S FOUT Glue Logics PWRDN P[5:0] M[7:0] S[1:0] Divider M AVDD25D PLL Core AVSS25D MUX AVBB25 *Divider Bus *Optional Test Pins Figure 4. Example of PLL Embeddd Methodology SEC ASIC 5 / 6 ANALOG PLL2026X 25MHz~300MHz FSPLL PLL Specification We appreciate your interest in our products. If you have further questions, please specify in the attached form. Thank you very much. Parameter Min Typ Max Unit Remarks Supply Voltage Output frequency range Input frequency range Cycle to Cycle Jitter Lock up time Dynamic current Stand by current Output clock duty ratio Long term jitter Output slew rate - Do you need XTAL driver buffer in PLL Core? If you need it, what's the crystal frequency range? If not, What's the input frequency range? - Do you need the lock detector? Do you need the I/O cell of SEC? Do you need the external pin for PLL test? What's the main frequency & frequency range? How many FSPLLs do you use in your system? What's output loading? Could you external/internal pin configurations as required? Specially requested function list : SEC ASIC 6 / 6 ANALOG