20MHz ~ 300MHz FSPLL PLL2073X Ver 1.5_5 General Description The pll2073x is a Phase-Locked Loop (PLL) frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macro-functions provide frequency multiplication capabilities. The output clock frequency FOUT is related to the input clock frequency FIN by the following equation: FOUT=(m*FIN) / (p*2^S) Features • 0.18um CMOS device technology • 1.8 Volt single power supply • Output frequency range: 20 ~ 300 MHz • Jitter ±120ps at 300MHz Where, FOUT is the output clock frequency. FIN is the input clock frequency. m, p and s are the values for programmable dividers. pll2073x consists of a Phase/Frequency Detector(PFD), a Charge Pump, an Internal Loop Filter, a Voltage Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as shown in Figure1. • Duty ratio 45% to 55% (All tuned range) • Frequency changed by programmable divider • Power down mode NOTE 1. Don't set the P or M as zero, that is 000000 / 00000000 2. The proper range of P and M : 1<=P<=62, 1<=M<=248 3. The P and M must be selected considering stability of PLL and VCO output frequency range 4. Please consult with SEC application engineer to select the proper P, M and S values No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The contents of the datasheet is subject to change without any notice. FUNCTIONAL BLOCK DIAGRAM FIN Pre Divider PFD Charge PUMP Main Divider SAMSUNG ELECTRONICS Co. LTD VCO Post Scaler FOUT 20MHZ~300MHZ FSPLL PLL2073X CORE PIN DESCRIPTION I/O TYPE I/O PAD AVDD18D DP vdd1t_abb Digital power supply AVSS18D DG vss1t_abb Digital ground AVDD18A AP vdd1t_abb Analog power supply AVSS18A AG vss1t_abb Analog ground VABB AB/DB vbb1_abb Analog / Digital bulk bias FIN DI picc_abb PLL clock input FOUT DO pob8_abb 50MHz~500MHz clock output FILTER AO poar50_abb PWD DI picc_abb Power down. -If PWD is high, power down mode is enabled. P[5:0] DI picc_abb 6bit programmable pre-divider. M[7:0] DI picc_abb 8bit programmable main-divider. S[1:0] DI picc_abb 2bit programmable post-scaler. NAME PIN DESCRIPTION I/O TYPE ABBR. • • • • AI : DI : AO: DO: Analog Digital Analog Digital Input Input Output Output • • • • • • AP : AG: AB: DP : DG: DB: Analog Analog Analog Digital Digital Digital Power Ground Sub Bias Power Ground Sub Bias • BD : Bidirectional Port CORE CONFIGURATION FIN PWD M[5:0] P[5:0] S[1:0] SEC ASIC M[7] M[6] M[5] M[4] M[3] M[2] M[1] M[0] FOUT pll2073x P[5] P[4] P[3] P[2] P[1] P[0] FILTER S[1] S[0] 2 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2073X Recommended Operating Conditions Characteristics Symbol Min Supply Voltage Differential AVDD18D-AVDD18A Operating Temperature Topr Typ Max Unit -0.1 +0.1 V -40 85 ºC NOTES 1. It is strongly recommended that all the supply pins (AVDD18D, AVDD18A) be powered to the same supply voltage to avoid power latch-up. DC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit Operating Voltage AVDD18D/AVDD18A 1.7 1.8 1.9 V Digital Input Voltage High VIH 0.7VDD Digital Input Voltage Low VIL 0.3VDD V Dynamic Current Idd 3 mA Power Down Current Ipd 220 uA V AC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Input Frequency FIN Output Clock Frequency Typ Max Unit 4 40 MHz FOUT 20 300 MHz VCO Output Frequency Fvco 160 400 MHz Input Clock Duty Cycle TID 40 60 % Output Clock Duty Cycle TOD 45 55 % Locking Time TLT 150 us 20M~100MHz TJCC -300 +300 ps 100M~200MHz TJCC -200 +200 ps 200MHz~300MHz TJCC -120 +120 ps Cycle to Cycle Jitter NOTES 1. It is strongly recommended that input signal is not generated glitch, but if consumer cannot help generating glitch, Consumer must carefully considerate the specification. SEC ASIC 3 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2073X Functional Description A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference or input signal in frequency as well as in phase. In this application, it includes the following basic blocks. . The voltage-controlled oscillator (VCO) generates VCO output frequency (Fvco) with loop filter DC voltage. . The Pre-divider divides the input frequency by p. . The Main-divider divides the Fvco by m. . The Post-divider divides the Fvco by s and generates FOUT. . The phase frequency detector detects the phase difference between the reference frequency (=FIN/p) and the feedback frequency (=Fvco/m) and controls the loop filter DC voltage. . The loop filter removes high frequency components and generates stable DC control voltage for VCO. The m, p, s values can be programmed by 16bit digital data from the external source. So the PLL can be locked in the desired frequency. Fout = m * Fin / p*s (m=M+8 , p=P+2, s=2^S) Digital data format: Main Divider Pre Divider Post Scaler M7,M6,M5,M4,M3,M2,M1,M0 P5,P4,P3,P2,P1,P0 S1,S0 NOTES . S[1] - S[0] : Output Frequency Scaler . M[7] - M[0] : VCO Frequency Divider . P[5] - P[0] : Input Frequency Divider NOTE - Please contact SEC application engineer to confirm the proper selection of M, P, S values. SEC ASIC 4 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2073X CORE EVALUATION GUIDE 1. The FOUT should be bypassed for external test. 2. You can generate various output frequencies by changing M/P/S setting. There are two methods of controlling divider values - Method 1: 16 bit register can be used for easy control of divider values. - Method 2: P, M and S pins are bypassed to the external port, and you can control each port directly. It is undesirable to connect P[5:0], M[7:0] and S[1:0] to the internal power or ground directly FIN AVDD18D AVSS18D AVDD18A AVSS18A VABB PWD pll2073x M[7:0] FOUT P[5:0] S[1:0] NOTES : 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED SEC ASIC 5 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2073X CORE LAYOUT GUIDE • The digital power(AVDD18D,AVSS18D) and the analog power(AVDD18A,AVSS18A) must be dedicated to PLL only and seperated. If the dedicated AVDD18D and AVSS18D are not allowed, that of the least power consuming block is shared with the PLL. • The FOUT and FILTER pins must be placed far from the internal signals in order to avoid overlapping signal lines. • The blocks having a large digital switching current must be located away from the PLL core. • The PLL core must be shielded by guard ring • For the FOUT pad, you can use a custom drive buffer or pot8_abb buffer considering the drive current. Design Considerations The following design consideratios apply:. * Jitter is affected by the power noise, substrate noise...etc. It increases when the noise level increases. * A CMOS-level input reference clock is recommend for signal compatibility with the PLL circuit. Other levels such as TTL may degrade the tolerances. * The use of two, or more PLLs requires special design considerations. Please consult your application engineer for more information. * The PLL core should be placed as close as possible to the dedicated loop filter and analog Power and ground pins. * It is inadvisable to locate noise-generating signals, such as data buses and high-current outputs, near the PLL I/O cells. * Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined placement restriction SEC ASIC 6 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2073X PACKAGE CONFIURATION NC 1 48 NC NC 2 47 M7 S0 3 46 M6 S1 4 45 M5 PWD 5 44 M4 FIN 6 43 M3 NC 7 42 M2 NC 8 41 M1 VBBA 9 40 M0 VDDA 10 39 VSSD VSSA 11 38 VDDD FILTER 12 37 P5 VSSA 13 36 P4 VDDA 14 35 VDDD NC 15 34 VSSD NC 16 33 P3 NC 17 32 P2 FOUT 18 31 P1 NC 19 30 P0 NC 20 29 NC NC 21 28 NC VSSP 22 27 NC VDDP 23 26 NC INDEX1 24 25 INDEX2 pll2073X 10uF 0.1uF NC : No Connection Pin Figure4 : Package Pin Configuration SEC ASIC 7 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2073X PACKAGE PIN DESCRIPTION NAME PIN NO I/O TYPE PIN DESCRIPTION VDDD 35,38 DP Digital power supply VSSD 34,39 DG Digital ground VBBA 9 AB/DB PWD 5 DI P[0]~P[5] 30~33,35,36 DI Pre-Divider Input VDDA 10,14 AP Analog power supply VSSA 11,13 AG Analog ground FIN 6 DI External Input Clock FOUT 18 DO 20MHZ~300MHz clock output FILTER 12 AO Pump out is connected to the FILTER. S[0]~S[1] 3,4 DI Post scaler input M[0]~M[7] 40 ~ 47 DI 8bit main divider input VDDP 23 PP I/O PAD Power VSSP 22 PG I/O PAD Ground Analog / Digital Bulk Bias FSPLL clock power down -PWD is High, PLL do not operating under this condition. - If isn't used this pin, tied to VSSD. NOTES 1. I/O TYPE PP and PG denote PAD power and PAD ground respectively. SEC ASIC 8 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2073X Phantom Cell Information - Pins of the core can be assigned externally(Package pins) or internally(internal ports) depending on design methods. The term "external" implies that the pins should be assigned externally like power pins. The term "internal/external" implies that these pins are user dependant FILTER AVDD18A:P pll2073x VABB:G AVSS18A:G AVDD18D:P AVSS18D:G VABB:G FIN P0 P5 P2 P3 P1 P4 M0 M2 M3 M4 PWD M7 M5 M1 M6 S0 S1 FOUT Figure5. Phantom cell feature Pin Name Pin Usage AVDD18D External AVSS18D External AVDD18A External AVSS18A External VABB External FIN External FOUT External/Internal Pin Layout Guide -. Use dedicated power/ground pins for PLL -. Power cuts are required to provide on-chip isolation => between dedicated PLL power/ground and all other power/ground -. Use good power and ground source on board -. Do not place noisy, high frequency and high power consuming circuitry pads near the FIN. -. Use proper low jitter reference clock -. Do not place noisy, high frequency and high power consuming circuitry pads near the FOUT. -. Internal routing path should be short. This will minimize loading effect. -. FOUT signals should not be crossed by any signals and should not run next to digital signals. This will minimize capacitive coupling between the two signals. Pin Name Pin Usage Pin Layout Guide FILTER External -. Do not place noisy, high frequency and high power consuming circuitry pads near the FILTER. -. Ground shielding is needed for internal routing path. -. FILTER routing path should not be crossed by any signals and should not run next to digital signals. -. External loop filter pin shoud be placed between analog power and ground to avoid stray coupling outsidethe chip and magnetic coupling via bond wires. - Loop filter components should be placed as close as possible. PWD Interanl/External M[7]~M[0] Internal/External P[5]~P[0] Internal/External S[1]~S[0] Internal/External Table3. Pin Layout Guide SEC ASIC 9 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2073X PLL Specification We appreciate your interest in our products. If you have further questions, please specify in the attached form. Thank you very much. Parameter Min Typ Max Unit Remarks Supply Voltage Output frequency range Input frequency range Cycle to Cycle Jitter Lock up time Dynamic current Stand by current Output clock duty ratio Long term jitter Output slew rate • Do you need XTAL driver buffer in PLL Core? If you need it, what's the crystal frequency range? If not, What's the input frequency range? • • • • • • • Do you need the lock detector? Do you need the I/O cell of SEC? Do you need the external pin for PLL test? What's the main frequency & frequency range? How many FSPLLs do you use in your system? What's output loading? Could you external/internal pin configurations as required? Specially requested function list : SEC ASIC 10 / 10 ANALOG 20MHZ~300MHZ FSPLL Version Ver 1.0 Ver 1.0.1 Date PLL2073X Modified Items Comments 2000.04.21 Preminary version published 2000.07.25 PKG Pin Desciprtion Changed Power Name Changed (EX VDD18A2 --> AVDD18D : Digital Power) Locking time changed : 100us --> 150us Phantom cell port location changed / Cell size changed Ver 1.2 2001.07.30 Power down ability is enhanced in charge pump and vco DC Electrical Characteristic is changed. ( Power down current 40uA --> 120uA) Ver 1.3 2001.08.09 Phantom cell port location changed (Filter port is removed) Ver 1.4 2001.09.25 Phantom cell port location is restored (Filter port is added) DC Electrical Characteristic is changed ( Power down current 120uA --> 220uA) after qualification check DC Electrical Characteristic is changed ( Operating voltage Min.1.6, Max 2.0 --> Min 1.65, Max 1.95) Recommended Operating condition is changed (Operation temperature 0~70ºC --> -40~85ºC) Ver 1.5 Ver 1.5_5 2001.10.06 Guard ring for internal capacitor is added./ Core size is changed 2001.12.13 AC Electrical Characteristic is added (VCO Output Frequency) SEC ASIC ANALOG