ETC BW2010D

8BIT 250MSPS DAC
BW2010D
FEATURES
GENERAL DESCRIPTION
This is CMOS 8-bit Triple D/A Converter for general
applications.Its typical conversion rate is 250MHz and
Supply voltage is 3.3V
TYPICAL APPLICATIONS
• Graphic display
• Digital TV
• General purpose high-speed
digital-to-analog conversion
•
•
•
•
•
•
•
•
250MHz Operation
+3.3V power supply
Optional 7.5IRE Mode
BGR (Internal / External)
RS-343A output level
8bit Voltage parallel Input
0 ~ 1V Output Swing
Power Down mode(High active)
FUNCTIONAL BLOCK DIAGRAM
BLANKEN
SETUP
RA7~RA0
1’st Latch
GA7~GA0
1’st Latch
BA7~BA0
1’st Latch
Decoder1
Decoder1
Decoder1
2’nd Latch
DAC1
IOR
2’nd Latch
DAC2
IOG
2’nd Latch
DAC3
IOB
CLK
SLEEP
( High Active)
CCOMP
BGR
OPAMP
VREFOUT
Ver 1.6(Apr. 2002)
No responsibility is assumed by SEC for its use nor for any
infringements of patents or other rights of third parties that may
result from its use. The content of this datasheet is subject to
change without any notice.
SAMSUNG ELECTRONICS Co. LTD
I75uA
CM
IRSET
SENSE
SENSEZ
BW2010D
8BIT 250MSPS Triple DAC
CORE PIN DESCRIPTION
NAME
I/O
TYPE
IOR,IOG,IOB
RA0:RA7
GA0:GA7
BA0:BA7
CLK
SLEEP
VREFOUT
CCOMP
I75uA
SENSEZ
IRSET
VSETUP
BLANKEN
VDDA1
VDDA2
VDDD
VSSA1
VSSA2
VSSD
VBBA
AO
DI
DI
DI
DI
DI
AB
AB
AO
AO
AB
DI
DI
AP
AP
DP
AG
AG
DG
AG
I/O PAD
PIN DESCRIPTION
poa_bb_50option Analog DAC output (Red,Green,Blue)
picc_bb
Video signal RED Digital input
picc_bb
Video signal GREEN Digital input
picc_bb
Video signal BLUE Digital input
picc_bb
Clock
picc_bb
Power down mode (hign active)
poa_bb_50option Reference voltage input & monitoring
poa_bb_50option
External capacitance connection
poa_bb
RAM drive 150 [uA] (for RAMDAC)
poar50_bb
DAC output sensing (for RAMDAC)
poa_bb_50option
external resistor connection
picc_bb
Blank enable pin
picc_bb
7.5 IRE level enable
vdda
Analog Power
vdda
Analog Power
vddd
Digital Power
vssa
Analog Ground
vssa
Analog Ground
vssd
Digital Ground
vbba
Analog Ground
I/O TYPE ABBR.
•AI : Analog Input
•DI : Digital Input
•AO : Analog Output
•DO : Analog Output
•
•
•
•
•
•
AP
DP
AG
DG
AB
DB
:
:
:
:
:
:
Analog Power
Digital Power
Analog Ground
Digital Ground
Analog Bi-direction
Analog Bi-direction
CORE CONFIGURATION
VDDA1 VSSA1 VDDA2 VSSA2
VDDD
VSSD
VBBA
IOR
RA[7:0]
bw2010d
GA[7:0]
IOG
IOB
BA[7:0]
BLANKEN VSETUP SLEEP
SEC ASIC
CLK
CCOMPSENSEZ
IRSET
2 / 15
I75UA VREFOUT
ANALOG
BW2010D
8BIT 250MSPS Triple DAC
FUNCTIONAL DESCRIPTION
This Core is 8bit 250MSPS digital to analog data
converter and uses segment architecture for 4bits of
MSB sides and binary-weighted architecture for 4bits
of LSB side. It contains of First Latch Block,
Decoder Block ,Second Latch Block, OPA Block,
BGR Block, Switch Buffer Block, Sleep Block for
power down, CM(current mirror) Block and Analog
Switch Block. This core uses reference current to
decide the 1LSB current size by dividing the
reference current by 122times. So the reference current
must be constant and the switch's physical real size
can be constant by using OPA block with high DC
gain. The most significant block of this core is analog
switch block and it must maintain the uniformity at
each switch, so Layout designer must care about the
matching characteristics on analog switch and CM
block. And more than 80%
of supply current is
dissipated at Analog Switch Block and OPA Block.
And it uses samsung(SEC) standard cell as all digital
cell of latch, decoder and buffer. And to adjust full
current output, you must decide the "Rset" resistor
value(connected to IRSET pin) and "Vbias" voltage
value(connected to VREFOUT pin). Its voltage output
can be obtained by connecting RL1(connected to
IOR,IOG,IOB pin) .
SEC ASIC
3 / 15
Linearity Error : Linearity error is defined as the
maximum deviation of the actual analog output from
the ideal output, determined by a straight line drawn
from zero to full scale.
Monotonicity : A D/A converter is monotonic if
the output either increases or remains constants as
the digital input increases.
Offset Error : The deviation of the output current
from the ideal of zero is called offset error. For IO ,
0mV output expected when the inputs are all 0s.
Gain Errors : The difference between the actual
andideal output span. The actual span is determined
by the output when all inputs are set to 1s minus the
output when all inputs are set to 0s.
Output Compliance Range : The range of allowable
voltage at the output of a current-output DAC.
Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown
resulting in nonlinear performance.
Settling Time : The time required for the output to
reach and remain within a specified error band about
its final value, measured from the start of the output
transition
Glitch Impulse : Asymmetrical switching times in a
DAC give rise to undesired output transients that are
quantified by a glitch impulse. It is specified as the
net area of the glitch in pV-s
ANALOG
BW2010D
8BIT 250MSPS Triple DAC
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
SYMBOL
VALUES
UNIT
Supply Voltage
VDDA1
VDDA2
VDDA
-0.3 TO 7.0
V
Voltage on any Digital Voltage
Vin
VSSA-0.3 to VDDA+0.3
V
Storage Temperature Range
Tstg
-45 to 150
ºC
NOTES
1. It is strongly recommended that to avoid power latch-up all the supply
Pins(VDDA1,VDDA2,VSSA1,VSSA2,VDDA,VSSA) be driven from the same source.
2. Absolute Maximum Rating values applied individually while all other
parameters are within specified operating conditions. Function operation
under any of these conditions is not implied.
3. Applied voltage must be current limited to specified range.
4. Absolute Maximum Ratings are value beyond which the device may be
damaged permanently. Normal operation is not guaranteed.
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
Operating Supply Voltage
VDDA
3.15
3.3
3.45
V
Digital input Voltage HIGH
LOW
Vih
Vil
0.7VDDA
-
-
0.3VDDA
V
Operating Temperature Range
Topr
0
25
70
ºC
SEC ASIC
4 / 15
ANALOG
BW2010D
8BIT 250MSPS Triple DAC
DC ELECTRICAL CHARACTERISTICS
CHARACTERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
Resolution
-
-
8
-
Bits
Differential Linearity Error
DLE
-1
0.1
+1
LSB
Integral Linearity Error
ILE
-1
0.2
+1
LSB
Monotonicity
-
-
Guaranteed
-
-
White to Black Pedestral Voltage
-
0.55
0.6
0.65
V
Maximum Output Compliance
Voc
-0.3
-
+1.3
V
Exteranl Reference Voltage (option)
-
1.2
1.235
1.27
V
Internal BGR Reference Voltage
-
1.15
1.235
1.25
V
Power Supply Current
Is
60
66
67
mA
NOTES
1. White to Black Pedestal Voltage can be changed by using external RSET resistor
2. Converter Specifications (unless otherwise specified)
VDDA=3.3V
VSSA=GND
Ta=25ºC RL=37.5Ohm , VREFOUT=1.235V
AC ELECTRICAL CHARACTERISTICS
CHARACTERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
Conversion Speed
Fop
-
250
300
MHz
Analog Output Delay
Td
-
1
-
ns
Analog Output Rise Time
Tr
-
0.5
1
ns
Analog Output Fall Time
Tf
-
0.5
1
ns
Analog Output Settling Time
Ts
-
40
55
ns
Glitch Impulse
GI
-
50
70
pVsec
Feedthrough
fdth
17
18
-
dB
Setup Time
Ts
-
0.3
0.5
nsec
Hold Time
Th
-
0.3
0.5
nsec
Output Compliance
Voc
-0.3
-
1.3
V
THD(Total Harmonic Distortion)
THD
-
0.125
-
%
SNDR( Fin=6MHz , Fck=300MHz)
SNDR
44
47
-
dB
NOTES
1.The above parameters are guaranteed over the full temperature range.
2.Clock and data feed-through is a function of the amount of overshoot and undershoot on the
digital inputs .Settling time does not include clock and data feed-through . Glitch impulse include
clock and data feed-through.
3.Setup and Hold Time are simulation values, not a test result
SEC ASIC
5 / 15
ANALOG
BW2010D
8BIT 250MSPS Triple DAC
TIMING DIAGRAM ( FOR ONE CHANNEL )
D[7:0]
Ts
Th
CLK
Td
Tset
0.1%
50%
IO
Half clock pipeline delay
NOTES
1. Output delay measured from the 50% point of the rising edge of CLK to the full scale
transition
2. Settling time measured from the 50% point of full scale transition to the output remaining
within ±1, ±2LSB.
3. Output rise/fall time measured between the 10% and 90% points of full scale transition.
4. Power Down On Time : 5.5us , Power Down Off Time : 5.5ms
SEC ASIC
6 / 15
ANALOG
BW2010D
8BIT 250MSPS Triple DAC
TIMING DIAGRAM ( FOR ONE CHANNEL )
R/G/B output
7.5 IRE disable
7.5 IRE enable
mA
V
mA
V
17.6
0.66
19.04
0.714
WHITE LEVEL
100 IRE
BLACK LEVEL
0
0
1.44
0.54
0
0
7.5 IRE
BLANK LEVEL
NOTE:
1. OUTPUT CONNECTED TO A DOUBLY TERMINATED 75
Ω LOAD
2. Vref =1.23V
0.7V, Rset=1.27 KΩ
Figure2. RGB video output
7.5 IRE FUNCTION ( FOR EACH CHANNEL )
DAC OUTPUT CURRENT(mA)
BINARY INPUT
VSETUP
BLANKEN
0
0
1
0
0
1
1
1
RL = 37.5 Ohm
DATA
CODE
R,G,B channel
000H
3FFH
0
1023
1.44
19.04
000H
3FFH
0
1023
0
17.6
SEC ASIC
ANALOG
8 / 15
BW2010D
8BIT 250MSPS Triple DAC
CORE EVALUATION GUIDE
3.3V
3.3V
3.3V
Cc
Cc
+
+
Ct
VDDA2
VSSA2
VDDA
+
Cc
Ct
Cc
Ct
VSSA VDDA1
VSSA1 VBBA
CCOMP
8
I75uA
RA<7:0>
SENSEZ
8
bw2010d
GA<7:0>
MAIN
PATH
IOR
IOG
IOB
8
R2
BA<7:0>
R2
R2
CLK
SLEEP(GND)
BLANKEN
IRSET
VREFOUT
VSETUP
8
8
selection
option
R1
1.235V
16
SELECT
MUX
Bi-drectional PAD
DAC function Measuring&Digitla input forcing
SEC ASIC
LOCATION
DESCRIPTION
Cc
0.1uF
R1
147 Ohm
R2
37.5 Ohm
Ct
10uF
Cc
0.1uF
10 / 15
ANALOG
BW2010D
8BIT 250MSPS Triple DAC
1.Testability
Whether you use MUX or the internal logic for testability, it is required to be able to select the values of digital
inputs ,TEST PATH block 16pins. See above figure. Only if it is, you can check the main function (Linearity)
and output (IOR,IOG,IOB), VREFOUT ,IRSET and CCOMP pins are reserved for external use.
2. Analysis
The voltage applied to VREFOUT is measured at IRSET node . And the voltage value is proportioned to the
reference current value of resistor which is connected to IRSET node. So you can estimate the full scale current
value by measuring the voltage, and check the DC characteristics of the OPAMP. For reference, as VREFOUT
applied to CCOMP node is given at IRSET node, the current flowing through IRSET is given as VREFOUT/RSET.
The voltage is scaled factor of 1/122 for VIDEO. The full scale current is given as the decimal value equivalent to
the digital code.
*Resolution
If you want to change the resolution, use as many appear bits as you want and connect the rest
lower bits to the ground as above diagram which is 8bit application.
*Output Range Alteration
In order to change the output swing, use following equation.
Vout = { VREFOUT/(RSET×122)}×DAC_CODE×Rio
SEC ASIC
11 / 15
ANALOG
BW2010D
8BIT 250MSPS Triple DAC
PHANTOM CELL INFORMATION
- Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending
on design methods.
The term "External" implies that the pins should be assigned externally like power pins.
The term "External/internal" implies that the applications of these pins depend on the user.
BLANKEN
VSETUP
VBBA
VBBA
VBBA
VBBA
RA[7]
Pin Name
Pin Usage
Pin Layout Guide
VDDD
External
- Maintain the large width of lines as
VSSD
External
VBBA
External
VDDA1
External
VSSA1
External
VDDA2
External
RA[6]
RA[5]
RA[4]
RA[3]
RA[1]
VDDA1
VSSA2
CCOMP
VREFOUT
GA[7]
8bit tripe 250MSPS DAC
IRSET
External
GA[3]
VDDA2
GA[2]
GA[1]
IOR
GA[0]
VDDA2
on board.
External/Internal - Do not overlap with digtal lines.
External/Internal - Maintain the shortest path to pads.
External/Internal - Separate from all other analog signals
GA[4]
VDDA2
blocks.
IREF
GA[6]
GA[5]
VSSA2
- Do not merge the analog powers
- Use good power and ground source
RA[0]
BW2010D
the length of power lines.
with another power from other
RA[2]
VSSA1
far as the pads.
- place the port positions to minimize
IOR
External/Internal - Maintain the larger width and the
IOG
External/Internal
IOB
External/Internal - Separate from all other digital lines.
SLEEP
External/Internal
BLANKEN External/Internal
VSETUP
shorter length as far as the pads.
External/Internal
RA[7:0]
External/Internal
IOG
BA[7]
GA[7:0]
External/Internal
VREFOUT
BA[6]
BA[7:0]
External/Internal
CCOMP
BA[5]
IOB
BA[4]
VSSA2
BA[3]
- Separated from the analog clean
signals if possible.
- Do not exceed the length by
1,000um.
BA[2]
BA[1]
BA[0]
CLK
VDDD
VSSD
VDDD
VSSD
SLEEP
SEC ASIC
12 / 15
ANALOG
BW2010D
8BIT 250MSPS Triple DAC
PACKAGE CONFIGURATION
250MHz
digital
input
data
BA0
1
48 VDDA
BA1
2
47 VSSA
BA2
3
46 CLK
BA3
4
45
SLEEP
BA4
5
44
NC
BA5
6
43
VREFOUT
BA6
7
42
VSSA2
BA7
8
41
NC
GA0
9
40
VDDA2
GA1
10
39
GA2 11
38
GA3 12
37
IOG
13
36
I75uA
GA5 14
35
IOR
GA6 15
34
SENSEZ
GA7 16
33
VDDA2
17
32
IRSET
RA1 18
31
VSSA2
RA2
19
30
VDDA1
RA3
20
29
VSSA1
RA4
21
28
RA5
22
27
VSETUP
RA6
23
26
BLANKEN
RA7
24
25
VBBA
GA4
RA0
C2
+3.3V
C1
0V
3.3V
normal 0V operation
C2
+1.235V
C1
Cc
C2
IOB
+3.3V
C1
R=37.5Ohm
CCOMP
R=37.5Ohm
R=37.5Ohm
C2
R=147 Ohm
NC
+3.3V
C1
0V
3.3V
0V
3.3V
LOCATION
DESCRIPTION
Cc
0.1uF TANTALUM CAPACITOR
C1
10uF
CAPACITOR
C2
0.1uF CERAMIC CAPACITOR
Rio
37.5 ohm 1% RESISTOR
RSET
147 ohm 1% METAL FILM RESISTOR
NOTES
1. Analog and digital supplies should be separated and de-coupled.
2. Supplies are not connected internally
3. All ground pins must be connected. One ground plane is preferred although it depends on the application
SEC ASIC
13 / 15
ANALOG
BW2010D
8BIT 250MSPS Triple DAC
PACKAGE PIN DESCRIPTION
PIN NAME
NO
I/O TYPE
DESCRIPTION
BA<0:7>
GA<0:7>
RA<0:7>
VREFOUT
IRSET
SLEEP
BLANKEN
VSETUP
CLK
I75uA
CCOMP
SENSEZ
IOR
IOG
IOB
VDDA
VSSA
VBBA
VDDA1
VDDA2
VSSA1
VSSA2
1~8
9~16
17~24
43
32
45
26
27
46
36
38
34
35
37
39
48
47
25
30
33,40
29
31,42
DI
DI
DI
AI
AI
DI
DI
DI
DI
AO
AI
AO
AO
AO
AO
DP
DG
AG
AP
AP
AG
AG
Video signal BLUE Digital input
Video signal GREEN Digital input
Video signal RED Digital input
Reference voltage input & monitoring
external resistor connection
Power down mode (hign active)
Blank enable pin
7.5 IRE level enable
Clock
RAM drive (150 [uA] )
External capacitance connection
DAC output sensing
Analog Voltage Output
Analog Voltage Output
Analog Voltage Output
Digital Power
Digital Ground
Bulk Bias Ground
Analog Power
Analog Power
Analog Ground
Analog Ground
NOTES
1.I/O TYPE PP and PG denote PAD Power and PAD Ground respectively.
SEC ASIC
14 / 15
ANALOG
BW2010D
8BIT 250MSPS Triple DAC
FEEDBACK REQUEST
We appreciate your interest in out products. If you have further questions, please specify in
the attached form.
Thank you very much.
DC / AC ELECTRICAL CHARACTERISTIC
Characteristics
Min
Typ
Max
Unit
Supply Voltage
V
Power dissipation
mW
Resolution
Bits
Analog Output Voltage
V
Operating Temperature
ºC
Output Load Capacitor
pF
Output Load Resistor
Ohm
Integral Non-Linearity Error
LSB
Differential Non-Linearity Error
LSB
Maximum Conversion Rate
MHz
Remarks
VOLTAGE OUTPUT DAC
Reference Voltage TOP
BOTTOM
V
Analog Output Voltage Range
Digital Input Format
V
Binary Code or 2's Complement Code
CURRENT OUTPUT DAC
Analog Output Maximum Current
mA
Analog Output Maximum Signal
Frequency
MHz
Reference Voltage
V
External Resistor for Current
Setting(RSET)
Ohm
Pipeline Delay
sec
- Do you want to Power down mode?
- Do you want to Internal Reference Voltage(BGR)?
- Which do you want to Serial Input TYPE or parallel Input TYPE?
SEC ASIC
15 / 15
ANALOG
BW2010D
8BIT 250MSPS Triple DAC
VERSION LIST
Version
Date
Modified Items
Ver 1..0
98.05.01
Original version published
Ver 1.4
99.12.13
1. Test configuration correction 2. Font correction
Ver 1.5
20.02.23
1. font correction 2. layout guide correction
Ver 1.6
02.0420
Add item ( Phantom cell guide )
SEC ASIC
Comments
ANALOG