20MHz ~ 300MHz FSPLL PLL2099X Ver 1.1 ( Nov. 2001 ) General Description The pll299x is a Phase-Locked Loop (PLL) frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macro-functions provide frequency multiplication capabilities. The output clock frequency FOUT is related to the input clock frequency FIN by the following equation: ^ FOUT=(m*FIN) / (p*2 s) F ea ture s • 0.18mm CMOS device technology • 1.8 Volt single power supply • Output frequency range: 20 ~ 300 MHz Where, FOUT is the output clock frequency. FIN is the input clock frequency. m, p and s are the values for programmable dividers. pll2099x consists of a Phase/Frequency Detector(PFD), a Charge Pump, an Internal Loop Filter, a Voltage Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as shown in Figure1. • Jitter ±120ps at 300MHz • Duty ratio 45% to 55% (All tuned range) • Frequency changed by programmable divider • Power down mode FUNCTIONAL BLOCK DIAGRAM FIN Pre Divider PFD Charge PUMP VCO FILTER Main Divider Figure1 : Phase Locked Lock Loop Block Diagram No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The contents of the datasheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD Post Scaler FOUT 20MHZ~300MHZ FSPLL PLL2099X C O RE P IN D E SC RIP TIO N NAME I/O TYPE I/O PAD PIN DESCRIPTION AVDD18D DP vddli_abb_lp Digital power supply AVSS18D DG vssli_abb_lp Digital ground AVDD18A AP vddli_abb_lp Analog power supply AVSS18A AG vssli_abb_lp Analog ground VABB AB/DB vbb_abb_lp Bulk Ground FIN DI picc_abb_lp Reference Frequency Input FILTER AO poar50_abb_lp FOUT DO pot8_abb_lp 20MHz~300MHz clock output picc_abb_lp FSPLL clock power down. -When PWD is High, PLL do not operate. -If Customer don't use this pin, apply it to AVSS18D .Pump out is connected to Filter . A capacitor is connected between the pin and analog ground PWD DI P[5:0] DI picc_abb_lp The values for 6bit programmable pre-divider. M[7:0] DI picc_abb_lp The values for 8bit programmable main divider. S[1:0] DI picc_abb_lp The values for 2bit programmable post scaler. I /O TYP E A BB R. • • • • AI : Analog Input DI : Digital Input AO : Analog Output DO : Analog Output • • • • • • AP AG AB DP DG DB : : : : : : Analog Power Analog Ground Analog Sub Bias Digital Power Digital Ground Digital Sub Vias • BD : Bidirectional Port Table1 : Core pin Configuation CORE CONFIGURATION FIN PWD M[7:0] P[5:0] S[1:0] M7 M6 M5 M4 M3 M2 M1 M0 FOUT pll2099x P5 P4 P3 P2 P1 P0 FILTER S1 S0 Figure2 : Core configuration SEC ASIC 2 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2099X Recommended Operating Conditions Characteristics Symbol Min Supply Voltage Differential AVDD18D-AVDD18A -0.1 External Loop Filter Capacitance LF Operating Temperature Topr Typ Max Unit +0.1 V 320 pF -40 85 ºC NOTES 1. It is strongly recommended that all the supply pins (AVDD18D, AVDD18A) be powered to the same supply voltage to avoid powe r latch-up. DC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit Operating Voltage AVDD18D/AVDD18A 1.65 1.8 1.95 V Digital Input Voltage High V IH - Digital Input Voltage Low VIL - V Dynamic Current Idd 3 mA Power Down Current Ipd 40 uA V AC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Input Frequency FIN Output Clock Frequency Max Unit 4 40 MHz FOUT 20 300 MHz Input Clock Duty Cycle TID 40 60 % Output Clock Duty Cycle (at 300MHz) TOD 45 55 % Input Glitch Pulse Width TIGP 1 ns Locking Time TLT 150 us Jitter,Cycle to Cycle TJCC +120 ps -120 Typ NOTES 1. It is strongly recommended that input signal is not generated glitch, but if c onsumer cannot help generating glitch, Consume r must carefully conside rate the specification. SEC ASIC 3 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2099X Functional Description A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference or input signal in frequency as well as in phase. In this application, it includes the following basic blocks. . The voltage-controlled oscillator to generate the output frequency . The divider P devides the input frequency by p . The divider M devides the VCO output frequency by m . The divider S divides the VCO output frequency by s . The phase frequency detector detects the phase difference between the reference frequency and the output frequency (after division) and controls the charge pump voltage. . The loop filter removes high frequency components in charge pump voltage and does smooth and clean control of VCO The m, p, s values can be programmed by 16bit digital data from the external source. So the PLL can be locked in the desired frequency. Fout = m * Fin / p*s m=M+8 , p=P+2, s=2^S Digital data format: Main Divider Pre Divider Post Scaler M7,M6,M5,M4,M3,M2,M1,M0 P5,P4,P3,P2,P1,P0 S1,S0 NOTES . S[1] - S[0] : Output Frequency Scaler . M[7] - M[0] : VCO Frequency Divider . P[5] - P[0] : Input Frequency Divider NOTE - Please contact SEC application engineer to confirm the proper selection of M, P, S values. SEC ASIC 4 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2099X C O RE E V A LU A T IO N GU I D E For the embedded PLL, we must consider the test circuits for the embedded PLL core in multiple applications. Hence the following requirements should be satisfied. - The FOUT pins must be bypassed for external test. - For PLL test (Below 2 examples), it is needed to control the dividers - M[7:0],P[5:0] and S[1:0] -that generate multiple clocks. #1. Registers can be used for easy control of divider values. #2. N sample bits of 16-bit divider pins can be bypassed for test using MUX. FIN AVDD18D AVS S18D AVDD18A AVS S18A VAB B PWD FOUT pll2099x M[7:0] #1.16bit Resistor Block FILTER P[5:0] 320pF S[1:0] Select pin Figure3 : Core Evaluation Guide Test pins of N sample b its #2.MUX NOTES : 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED Internal d ivid er sign al line : 104 CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED SEC ASIC 5 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2099X CORE LAYOUT GUIDE • The digital power(AVDD18D,AVSS18D) and the analog power(AVDD181,AVSS18A) must be dedicated to PLL only and seperated. If the dedicated AVDD18D and AVSS18D are not allowed, that of the least power consuming block is shared with the PLL. • The FOUT and FILTER pins must be placed far from the internal signals in order to avoid overlapping signal lines. • The blocks having a large digital switching current must be located away from the PLL core. • The PLL core must be shielded by guard ring • For the FOUT pad, you can use a custom drive buffer or pot8_abb buffer considering the drive current. Design Considerations The following design consideratios apply:. * Jitter is affected by the power noise, substrate noise...etc. It increases when the noise level increases. * A CMOS-level input reference clock is recommend for signal compatibility with the PLL circuit. Other levels such as TTL may degrade the tolerances. * The use of two, or more PLLs requires special design considerations. Please consult your application engineer for more information. * The following aplly to the noise level, which can be minimized by using good analog power and ground isolation techniques in the system: - Use wide PCB traces for POWER(AVDD18D/AVSS18D2, AVDD18A/AVSS18A) connections to the PLL core. Separate the traces from the chip's AVDD18D/AVSS18D2, AVDD18A/AVSS18A supplies. - Use proper AVDD18D/AVSS18D2, AVDD18A/AVSS18A de-coupling. - Use good power and ground source on the board. - Use Power VBBA for minimize substrate noise. * The PLL core should be placed as close as possible to the dedicated loop filter and analog Power and ground pins. * It is inadvisable to locate noise-generating signals, such as data buses and high-current outputs, near the PLL I/O cells. * Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined placement restriction SEC ASIC 6 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2099X PACKAGE CONFIURATION NC 1 48 RESET NC 2 47 M7 S0 3 46 M6 S1 4 45 M5 PWD 5 44 M4 FIN 6 43 M3 NC 7 42 M2 NC 8 41 M1 VBBA 9 40 M0 VDDA 10 39 VSSD VSSA 11 38 VDDD FILTER 12 37 P5 VSSA 13 36 P4 VDDD pll2099X VDDA 14 35 NC 15 34 VSSD NC 16 33 P3 NC 17 32 P2 FOUT 18 31 P1 NC 19 30 P0 NC 20 29 NC NC 21 28 NC VSSP 22 27 NC VDDP 23 26 NC INDEX1 24 25 INDEX2 10uF 0.1uF NC : No Connection Pin Figure4 : Package Pin Configuration SEC ASIC 7 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2099X PACKAGE PIN DESCRIPTION NAME PIN NO I/O TYPE PIN DESCRIPTION VDDD 35,38 DP Digital power supply VSSD 34,39 DG Digital ground VBBA 9 AB/DB PWD 5 DI P[0]~P[5] 30~33,35,36 DI Pre-Divider Input RESET 48 DI Divider Reset pin Control(Only test) VDDA 10,14 AP Analog power supply VSSA 11,13 AG Analog ground FIN 6 DI External Input Clock FOUT 18 DO 20MHZ~300MHz clock output FILTER 12 AO Pump out is connected to the FILTER. S[0]~S[1] 3,4 DI Post scaler input M[0]~M[7] 40 ~ 47 DI 8bit main divider input VDDP 23 PP I/O PAD Power VSSP 22 PG I/O PAD Ground Analog / Digital Bulk Bias FSPLL clock power down -PWD is High, PLL do not operating under this condition. - If isn't used this pin, tied to VSSD. Table2 : Package pin configuration NOTES 1. I/O TYPE PP and PG denote PAD power and PAD ground respective ly. SEC ASIC 8 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2099X Phantom Cell Information - Pins of the core can be assigned externally(Package pins) or internally(internal ports) depending on design methods. The term "external" implies that the pins should be assigned externally like power pins. The term "internal/external" implies that these pins are user dependant FILTER AVDD18A:P pll2099x VABB :G AVSS18A:G AVDD18D:P AVSS18D:G VABB :G FIN P0 P5 P2 P3 P1 P4 M0 M2 M3 M4 PWD M7 M5 M1 M6 S0 S1 FOUT Figure5. Phantom cell feature (Chip size : 390.0um*360.um) Pin Name Pin Usage AVDD18D External AVSS18D External AVDD18A External AVSS18A External VABB External FIN FOUT External External/Internal Pin Name Pin Layout Guide -. Us e dedicated power/ground pins for PLL -. Power cuts are required to provide on-chip isolation => between dedicated PLL power/ground and all other power/ground -. Us e good power and ground source on board -. Do not place noisy, high frequency and high power consuming circuitry pads near the FIN. -. Us e proper low jitter reference clock -. Do not place noisy, high frequency and high power consuming circuitry pads near the FOUT. -. Internal routing path should be short. This will minimize loading effect. -. FOUT signals should not be crossed by any signals and should not run next to digital signals. This will minimize capacitive coupling between the two signals. Pin Usage Pin Layout Guide FILTER External -. Do not place noisy, high frequency and high power consuming circuitry pads near the FILTER. -. Ground shielding -. FILTER routing path should not be crossed by any signals and should not run next to digital signals. -. External loop filter pin shoud be placed between analog power and ground to avoid s tray coupling outsidethe chip and magnetic coupling via bond wires. - Closely placed Loop Filter components. PWD Interanl/External M[7]~M[0] Internal/External P[5]~P[0] Internal/External S[1]~S[0] Internal/External Table3. Pin Layout Guide SEC ASIC 9 / 10 ANALOG 20MHZ~300MHZ FSPLL PLL2099X PLL Specification We appreciate your interest in our products. If you have further questions, please specify in the attached form. Thank you very much. Parameter Min Typ Max Unit Remarks Supply Voltage Output frequency range Input frequency range Cycle to Cycle Jitter Lock up time Dynamic current Stand by current Output clock duty ratio Long term jitter Output slew rate • Do you need XTAL driver buffer in PLL Core? If you need it, what's the crystal frequency range? If not, What's the input frequency range? • • • • • • • Do you need the lock detector? Do you need the I/O cell of SEC? Do you need the external pin for PLL test? What's the main frequency & frequency range? How many FSPLLs do you use in your system? What's output loading? Could you external/internal pin configurations as required? Specially requested function list : SEC ASIC 10 / 10 ANALOG