50MHz ~ 300MHz FSPLL PLL2124X Ver 1.0.0. (July, 2002) GENERAL DESCRIPTION FEATURES • 0.13um CMOS device technology The pll2124x is a Phase Locked Loop (PLL) frequency synthesizer. The PLL provides frequency multiplication capabilities. The output clock frequency FOUT is related to the input clock frequency FIN by the following equation: • 1.5 Volt single power supply • Output frequency range: 50M ~ 300MHz • Jitter: ±150ps at 300MHz (typ.) s FOUT=(m*FIN) / (p*2 ) • Duty ratio: 40% to 60% (All tuned range) Where FOUT is the output clock frequency. FIN is the input clock frequency. m, p and s are the values for programmable dividers. pll2124x consists of a Phase Frequency Detector(PFD), a Charge Pump, an Off-chip Loop Filter, a Voltage Controlled Oscillator (VCO), a 6bit Pre-divider, an 8bit Main-divider and 2bit Post-scaler as shown in functional block diagram. • Power down mode • Off-chip loop filter • Frequency is changed by programmable divider NOTE 1. Don't set the P or M value as zero, that is, seting the P=000000, M=00000000 can cause malfunction of the PLL. 2. The proper range of P and M : 1<=P<=62, 1<=M<=248 3. The P and M must be selected considering stability of PLL and VCO output frequency range. 4. Please contact SEC application engineer for proper selection of the P, M, S values of the PLL. No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The contents of the datasheet is subject to change without any notice. FUNCTIONAL BLOCK DIAGRAM AVDD15D Fin/P FIN Pre-Divider (P) FILTER AVSS15D UP Phase Frequency Detector Fvco/M R1 C2 Charge Pump DN 6b M[7:0] P[5:0] Fvco Main-Divider (M) Voltage Controlled Oscillator Vctrl S[1:0] 8b Post - Scaler (S) (1,2,4,8) PWRDN AVDD15A AVSS15A SAMSUNG ELECTRONICS Co. LTD VABB 2b FOUT 50MHz~300MHz FSPLL PLL2124X CORE PIN DESCRIPTION NAME I/O TYPE AVDD15D DP Digital power supply AVSS15D DG Digital ground AVDD15A AP Analog power supply AVSS15A AG Analog ground VABB AB/DB FIN DI PLL clock input FOUT DO 50MHz~300MHz clock output FILTER AO The external loop filter capacitor should be connected between the pin and analog ground PWRDN DI Power down. -If PWRDN is high, power down mode is enabled. P[5:0] DI 6bit programmable pre-divider. M[7:0] DI 8bit programmable main-divider. S[1:0] DI 2bit programmable post-scaler. PIN DESCRIPTION Analog / Digital bulk bias I/O TYPE ABBR. • • • • AI : DI : AO: DO: Analog Digital Analog Digital Input Input Output Output • • • • • • AP : AG: AB : DP : DG: DB : Analog Analog Analog Digital Digital Digital Power Ground Sub Bias Power Ground Sub Bias • BD : Bidirectional Port CORE CONFIGURATION FIN PWRDN M[7:0] P[5:0] S[1:0] SEC ASIC M[7] M[6] M[5] M[4] M[3] M[2] M[1] M[0] FOUT pll2124x P[5] P[4] P[3] P[2] P[1] P[0] FILTER S[1] S[0] 2/10 ANALOG 50MHz~300MHz FSPLL PLL2124X ABSOLUTE MAXIMUM RATING Characteristics Symbol Value Unit Applicable pin Supply Voltage AVDD15D AVDD15A 2.5 V AVDD15D, AVDD15A Digital Input Voltage Vin vdd + 0.2 vss - 0.2 V P[5:0] M[7:0] S[1:0] FIN, PWRDN Storage Temperature Tstg -45 ~ 150 °C - NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5Kohm resistor (Human body model) RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Supply Voltage Differential AVDD15D-AVDD15A -0.1 External Loop Filter Capacitance LF Operating Temperature Topr Typ Max Unit +0.1 V 1.8 -40 nF 85 Remark Capacitance tolerance (+/-5%) °C NOTES 1. It is strongly recommended that all the supply pins (AVDD15D, AVDD15A) be powered to the same supply voltage to avoid power latch-up. SEC ASIC 3/10 ANALOG 50MHz~300MHz FSPLL PLL2124X DC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit Operating Voltage AVDD15D/AVDD15A 1.425 1.50 1.575 V Digital Input Voltage High VIH 0.7VDD Digital Input Voltage Low VIL 0.3VDD V Dynamic Current Idd 3 mA Power Down Current Ipd TBD uA V * Operating voltage Min/Max are prelminary values and expected to be updated. AC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Input Frequency FIN VCO output frequency Max Unit 10 40 MHz Fvco 100 300 MHz Output Frequency FOUT 50 300 MHz Input Clock Duty Ratio TID 40 50 60 % Output Clock Duty Ratio TOD 40 50 60 % Locking Time TLT 300 50M~100MHz TJCC +/-600 TBD ps 100M~200MHz TJCC +/-300 TBD ps 200M-300MHz TJCC +/-150 TBD ps Cycle to Cycle Jitter SEC ASIC 4/10 Typ us ANALOG 50MHz~300MHz FSPLL PLL2124X FUNCTIONAL DESCRIPTION A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference or input signal in frequency as well as in phase. The pll2124x can provide frequency multiplication capabilities, but can't guarantee phase synchronization between FIN and FOUT. pll2124X consists of the following basic blocks. - The phase frequency detector (PFD) detects the phase difference between the reference clock and feedback clock, then generates UP/DOWN error signals. If reference clock leads feedback clock, UP is high and DOWN is low. If reference clock lags feedback clock, UP is low and DOWN is high. - The charge pump charges or discharges the following loop filter according to UP/DOWN signal. - The loop filter suppresses high frequency components in the charge pump voltage (Vctrl), allowing the dc value to control the VCO frequency. - The voltage-controlled oscillator generates the clock signal proportional to control voltage. Required frequency is produced by appropriate selection of P, M and S dividers. Fout = Fin*m/(p*s) m=M+8 , p=P+2 , s=1,2,4,8 - Don't set the value P or M to all zero, that is 000000/ 00000000. - The range of P and M : 1 <= P <= 62, 1 <= M <= 248 - The M and P must be selected considering stability and VCO range. VCO output frequency range of pll2124x is from 100MHz to 200MHz. Digital data format: Main Divider Pre Divider Post Scaler M7,M6,M5,M4,M3,M2,M1,M0 P5,P4,P3,P2,P1,P0 S1,S0 NOTES . M[7] - M[0]: : main-divider . P[5] - P[0] : pre-divider . S[1] - S[0] : post-scaler 1<=M<=248 1<=P<=62 0<=S<=3 IMPORTANT NOTICE - Please consult with SEC application engineer about the proper selection of M, P, S values. SEC ASIC 5/10 ANALOG 50MHz~300MHz FSPLL PLL2124X CORE EVALUATION GUIDE 1.You can generate various output frequencies by changing M/P/S setting. There are two methods of controlling divider values - Method 1: 16 bit register can be used for easy control of divider values. - Method 2: P, M and S pins are bypassed to the external port, and you can control each port directly. It is undesirable to connect P[5:0], M[7:0] and S[1:0] to the internal power or ground directly NOTES : 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED 1.5V AVDD15D GND AVSS15D VABB FILTER 1.8 nF (Chip cap) VABB AVSS15A AVDD15A AVDD15A :P AVSS15 A:G VABB:G FILTER VABB:G AVSS 15 D:G AVDD15 D :P pll2124x S0 S1 FOUT M0 M1 M2 M3 M4 M5 M6 M7 PWRDN FIN P5 P4 P3 P2 P1 P0 FOUT FIN SEC ASIC P[5:0] M[7:0] 6/10 PWRDN S[1:0] ANALOG 50MHz~300MHz FSPLL PLL2124X CORE LAYOUT GUIDE 1. The digital power(AVDD15D,AVSS15D) and the analog power(AVDD15A, AVSS15A) must be dedicated to PLL only and separated. If the dedicated AVDD15D and AVSS15D are not allowed, please consult with SEC application engineer. 2. The FOUT and FILTER pins must be placed far from the internal signals in order to avoid cross-talk between the signal lines. 3. The blocks showing a large amount of digital switching current must be located away from the PLL core. DESIGN CONSIDERATIONS The following design considerations must be applied:. 1. Jitter is affected by the power noise, substrate noise, etc. It goes up when the noise level increases. 2. A CMOS-level input reference clock is recommend for signal compatibility with the PLL circuit. Other levels such as TTL may degrade the tolerances. 3. The use of two, or more PLLs requires special design considerations. Please consult with SEC application engineer for more information. 4. The PLL core should be placed as close as possible to the dedicated loop filter and analog power and ground pins. 5. It is inadvisable to locate noise-generating signals near the PLL and its I/O cells. For example, data buses, high frequency outputs and high current consuming cells, . 6. Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined placement restriction SEC ASIC 7/10 ANALOG 50MHz~300MHz FSPLL PLL2124X PHANTOM CELL INFORMATION - Pins of the core can be assigned externally(package pins) or internally(internal ports) depending on design methods. The term "external" implies that the pins should be assigned externally like power pins. The term "internal/external" implies that these pins are user dependant AVDD15A :P AVSS15 A:G VABB:G FILTER VABB:G AVSS 15 D:G AVDD15 D :P pll2124x 8/10 S0 S1 FOUT SEC ASIC M0 M1 M2 M3 M4 M5 M6 M7 PWRDN FIN P5 P4 P3 P2 P1 P0 ANALOG 50MHz~300MHz FSPLL PLL2124X PIN LAYOUT GUIDE Pin Name Pin Usage AVDD15D External AVSS15D External AVDD15A External AVSS15A External VABB External FIN External Pin Layout Guide -. Use dedicated power/ground pins for PLL -. Power cuts are required to provide on-chip isolation => between dedicated PLL power/ground and all other power/ground -. Use good power and ground source on board -. Do not place noisy, high frequency and high power consuming circuitry pads near the FIN. -. Use proper low jitter reference clock External/Internal -. Do not place noisy, high frequency and high power consuming circuitry pads near the FOUT. -. Internal routing path should be short. This will minimize loading effect. -. FOUT signals should not be crossed by any signals and should not run next to digital signals. This will minimize capacitive coupling between the two signals. FILTER External -. Do not place the noisy, high frequency and high power consuming circuitry pads near the FILTER. -. Ground shielding is needed for internal routing path. -. FILTER routing path should not be crossed by any signals and should not run next to digital signals. -. External loop filter pin should be placed between analog power and ground to avoid stray coupling outside the chip and magnetic coupling via bond wires. - Loop filter components should be placed as close as possible. PWRDN Interanl/External M[7]~M[0] Internal/External P[5]~P[0] Internal/External S[1]~S[0] Internal/External FOUT SEC ASIC 9/10 ANALOG 50MHz~300MHz FSPLL PLL2124X FEEDBACK REQUEST Thanks for taking an interest in our products. If you have any question, Specify your needs in the attached form. Thank you very much.. Parameter Min Typ Max Unit Remarks Supply Voltage Output frequency range Input frequency range Cycle to Cycle Jitter Lock up time Dynamic current Stand by current Output clock duty ratio • • • • Do you need the I/O cells of SEC? How many FSPLLs are you using in your system? What is the PLL output loading condition? What is your p, m and s values ? Specially requested function list : SEC ASIC 10/10 ANALOG