ETC C9811X2AYB

APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
Product Features
•
•
•
•
•
•
•
•
•
•
•
•
Frequency Table (MHz)
Intel’s 810 clock solution
3 copies of CPU Clock (CPU[0:1] and CPU_ITP)
9 copies of SDRAM Clock (SDRAM[0:7] and DCLK)
8 copies of PCI clock
2 copies of 3V66 Clock
2 copies of APIC Clock, synchronous to PCI Clock
1 REF Clock
2 USB Clocks (Non SSC)
Power Down Feature
Spread Spectrum Support
SMBUS Support for turning off unused clocks
56 Pin SSOP Package
Block Diagram
36pF
XOUT
300K
36pF
VDD
REF
1
VDDI
apic
IOAPIC(0:1)
2
VDDC
cpu
CPU(0:2)
3
Rin
SCLK
SDATA
SEL1
SEL0
PD#
i2c-clk
i2c-data
VDDS
s1
s0
sdram
SDRAM(0:7), DCLK
9
VDD
pwr_dwn#
66m
3V66(0:1)
2
VDD
pci
PCI(0:7)
8
PLL1
Rin
SEL0
CPU
SDRAM
PCI
0
0
Tri-state
Tri-state
Tri-state
0
1
1
0
66.6
100
33.3
1
1
100
100
33.3
Test mode (see table2)
Table 1
Note: The following clocks remain fixed frequencies
except in Test Mode.
3V66=66.6MHz, USB/DOT=48MHz, REF=14.318MHz
and IOAPIC=16.6 or 33.3MHz depending on power up
selection.
Pin Configuration
C9811X2
XIN
X
B
U
F
SEL1
VDD
48
1
USB (0:1)
ASEL/REF
VDD
XIN
XOUT
VSS
VSS
3V660
3V661
VDD
VDD
PCI0_ICH
PCI1
PCI2
VSS
PCI3
PCI4
VSS
PCI5
PCI6
PCI7
VDD
VDDA
VSSA
VSS
USB0
USB1
VDD
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VSS
IOAPIC0
IOAPIC1
VDDI
CPU0
VDDC
CPU1
CPU2_ITP
VSS
VSS
SDRAM0
SDRAM1
VDD
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDD
SDRAM6
SDRAM7
VSS
DCLK
VDD
PD#
SCLK
SDATA
SEL1
PD#
i2c-clk
i2c-data
PLL2
Fig.1
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 1 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
Pin Description
PIN No.
Pin Name
ASEL/REF
PWR
VDD
I/O
I/O
TYPE
3
4
11, 12, 13,
15, 16, 18,
19, 20
7, 8
25, 26
28, 29
XIN
XOUT
PCI0/ICH
PCI(1..7)
VDD
VDD
VDD
I
O
O
OSC1
3V66(0,1)
USB (0:1)
SEL(0,1)
VDD
VDD
VDD
O
O
I
30
31
32
SDATA
SCLK
PD#
VDD
VDD
VDD
I
I
I
34
36, 37, 39,
40, 42, 43,
45, 46
49, 50, 52
DCLK
SDRAM(7..0)
VDD
VDDS
O
O
CPU(2)_ITP,
CPU(1,0)
IOAPIC(1,0)
VDDC
O
VDDI
O
1
54, 55
2, 9, 10, 21,
27
22
23
51, 53
5, 6,14, 17,
24, 35, 41,
47, 48, 56
33, 38, 44
Description
3.3V 14.318 MHz clock output. This pin also serves as the
select strap for IOAPIC clock frequency. If strapped low during
power up, IOAPIC clocks run at PCI/2 (16.6 MHz). If not
strapped, it runs at 33 MHz. This pin has a 50K internal pull-up
(+/- 20K).
14.318MHz Crystal input
14.318MHz Crystal output
3.3V PCI clock outputs
3.3V Fixed 66.6 MHz clock outputs
3.3V Fixed 48 MHz clock outputs
3.3V LVTTL compatible inputs for logic selection. Has an
internal pull-up (Typ. 250KΩ)
I²C compatible SDATA input. Has an internal pull-up (>100KΩ)
I²C compatible SCLK input. Has an internal pull-up (>100KΩ)
3.3V LVTTL compatible input. Device enters powerdown mode
When held LOW. Has an internal pull-up (>100KΩ)
3.3V output running 100MHz
3.3V output running 100MHz. All SDRAM outputs can be turned
off through SMBUS.
2.5V Host bus clock outputs. 66 or 100MHz depending on state
of SEL0 and SEL1 pins.
2.5V clock outputs running rising edge synchronous with the
PCI clock frequency. 16.67 MHz or 33.3 MHz dependent on
power up strapping of REF (Pin 1).
3.3V Power Supply
VDD
-
VDDA
VSSA
VDDC, VDDI
VSS
-
P
P
P
P
-
Analog circuitry 3.3V Power Supply
Analog circuitry power supply Ground pins.
2.5V Power Supply’s
Common Ground pins.
VDDS
-
P
-
3.3V power support for SDRAM clock output drivers.
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 2 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
Test Mode Function
Test Mode Functionality
SEL1
SEL0
CPU
0
1
TCLK÷2
SDRAM
TCLK÷2
3V66
TCLK÷3
PCI
TCLK÷6
48 MHz
TCLK÷2
REF
TCLK
IOAPIC
TCLK÷6
Table 2
Note: TCLK is a test clock over driven on the XIN input during test mode.
Power Management Functions
Power Management on this device is controlled by a single pin, PD# (pin32). When PD# is high (default) the device is in
running and all signals are active.
When PD# is asserted (forced) low, the device is in shutdown (or in power down) mode and all power supplies (3.3V and
2.5V except for VDDA/pin 22) may be removed. When in power down, all outputs are synchronously stopped in a low
state (see Fig.2 below), all PLL’s are shut off, and the crystal oscillator is disabled. When the device is shutdown the I²C
function is also disabled.
Power Management Timing
PD#
PCI(1:6)
CPU(1:3)
Fig.2
Power Management Current
PD#, SEL[1..0]
(CPU Clock)
0XX (Power down)
Maximum 2.5 Volt Current
Consumption (VDD2.5 =2.625)
100 µA
110 (66MHz)
70 mA
111 (100MHz)
100 mA
Maximum 3.3 Volt Current Consumption
(VDD3.3 = 3.465 V)
200 µA
280 mA
280 mA
Table 3
When exiting the power down mode, the designer must supply power to the VDD pins first, a minimum of 200mS before releasing
the PD# pin high.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 3 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
Clock Synchronization and Phase Alignment
This device incorporates IOAPIC clock synchronization. With this feature, the IOAPIC clocks are derived from the CPU
clock. The IOAPIC clock lags the CPU clock by the specified 1.5 to 3.5 nSec. Figure 3 shows the relationship between
the CPU and IOAPIC clocks.
Device Clock Phase Relationships
0nS
10nS
20nS
30nS
40nS
CPU Clock 66MHz
2.5nS
CPU Clock100MHz
5nS
7.5nS
Sync
5nS
SDRAM Clock 100MHz
3V66 Clock 66MHz
PCI Clock 33MHz 1.5~3.5nS
IOAPIC Clock 33MHz
Fig.3
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 4 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
Power on Bi-Directional Pins
Power Up Condition:
Pin1 is a Power up bi-directional pin and is used for selecting the IOAPIC frequency in page 1, table 1. During power-up
of the device, this pin is in input mode (see Fig 4, below), therefore; it is considered input select pins internal to the IC.
After a settling time, the selection data is latch into the internal control register and this pin becomes a clock output. If
strapped low the IOAPIC clock is set to ½ of the PCI frequency (16.6 MHz). If strapped high IOAPIC is 33.3 MHz.
VDD RAIL
OWER SUPPLY
AMP
REF / SEL2
(Pin 1)
Hi-Z INPUTS
-
TOGGLE OUTPUTS
SELECT DATA IS LATCHED INTO REGISTER THEN PIN BECOMES A REF CLOCK OUTPUT SIGNAL
Fig.4
V dd
Strapping Resistor Options:
The power up bi-directional pins have a large value pullup each (250KΩ), therefore, a selection “1” is the
default. If the system uses a slow power supply (over
5mS settling time), then it is recommended to use an
external Pull-up (Rup) in order to insure a high
selection. In this case, the designer may choose one of
two configurations, see Fig.5A and B.
S e e D e s c rip tio n
R up
10K
IM I C 9 8 1 1 X 2
Rd
Load
B id ire c tio n a l
JP 1
JU M P E R
F ig . 5 A
Fig. 5A represents an additional pull up resistor 50KΩ
connected from the pin to the power line, which allows a
faster pull to a high level.
If a selection “0” is desired, then a jumper is placed on
JP1 to a 5KΩ resistor as implemented as shown in
Fig.5A. Please note the selection resistors (Rup and
Rdn) are placed before the Damping resistor (Rd)
close to the pin.
Fig. 5B represent a single resistor 10KΩ connected to a
3-way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads 1
and 2.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
R dn
10K
V dd
JP 2
3 W ay Jum per
3
IM I C 9 8 1 1 X 2
2
1
R sel
10K
Rd
Load
B id ire c tio n a l
F ig . 5 B
Document#: 38-07052 Rev. **
05/03/2001
Page 5 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
2-Wire SMBUS Control Interface
The 2-wire control interface implements a write slave only interface according to SMBus specification. (See Fig. 7 / P. 8).
Sub addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The
2-wire control interface allows each clock output to be individually enabled or disabled. 100 Kbits/second (standard
mode) data transfer is supported.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK
is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is an 8-bit address. W#=0 in write mode.
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on
the SDATA wire following reception of each byte. Data is transferred MSB first at a max rate of 100kbits/S. The device
will not respond to any other control interface conditions, and previously set control registers are retained.
SMBUS Test Circuitry
+ 5V
Device under Test
2.2 K
DATAIN
SDATA
+ 5V
SCLK
2.2 K
+ 5V
DATAOUT
2.2 K
CLOCK
Fig.6
Note: Buffer is 7407 with VCC @ 5.0 V
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 6 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up.
Following the acknowledge of the Address Byte, two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the sequence described below (Byte 0, Byte 1,
and Byte2) will be valid and acknowledged.
Byte 0: CPU Clock Register (1=Enable, 0=Disable, Default=07)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
1
1
1
Pin#
26
25
49
Description
Reserved
Reserved
Reserved
Reserved
Spread spectrum mode
USB1
USB0
CPU2_ITP
Byte 2: PCI Clock Register (1=Enable, 0=Disable, Default=FE)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
0
Pin#
20
19
18
16
15
13
12
-
Description
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
Reserved
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Byte 1: SDRAM Clock Register (1=Enable, 0=Disable, Default=FF)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
36
37
39
40
42
43
45
46
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 3: Reserved Register (Default=00)
Byte 4: Reserved Register (Default=00)
Byte 5: SSCG Control Register (Default=00)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Pin#
-
Description
Spread Mode (0=down, 1=center)
Ref. Table 4
Ref. Table 4
Reserved
Reserved
Reserved
Reserved
Reserved
Document#: 38-07052 Rev. **
05/03/2001
Page 7 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
ACK
SDATA IS OUTPUT PIN
SDATA IS INPUT PIN
1
1
0
1
0
0
1
ACK
COMMAND BYTE
(DON’TCARE)
0
SDATA
MSB
LSB
SCLK
8
START CONDITION
CONTINUED
ACK
ACK
COUNT BYTE
(DON’TCARE)
ACK
BYTE 0
(VALID DATA)
BYTE N (LAST
VALID DATA)
CONTINUED
8
8
8
STOP CONDITION
Figure 7
SMBUS Communications Waveforms
Test and Measurement Condition
Output under Test
Probe
Load Cap
2.5V signals
3.3V signals
tDC
tDC
-
-
-
-
3.3V
2.5V
2.4V
2.0V
1.5V
1.25V
0.4V
0.4V
0V
0V
Tr
Tr
Tf
Tf
Fig.8
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 8 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic
Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the
center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore
spreading the same amount of energy over a spectrum. This technique is achieved by modulating the clock down from
(Fig.9A) or around the center (Fig.9B) of its resting frequency by a certain percentage (which also determines the energy
distribution bandwidth). In this device, Spread Spectrum is enabled by setting SMBUS byte0, bit3 = 1. The default of the
device at power up keeps the Spread Spectrum disabled, it is therefore, important to have SMBUS accessibility to turnon the Spread Spectrum function. Once the Spread Spectrum is enabled, the spread bandwidth option is selected by
SST(0:2) in SMBUS byte 5, bits 5, 6 & 7 following tables 4A, and 4B below.
In Down Spread mode the center frequency is shifted down from its rested (non-spread) value by ½ of the total spread
%. (ex.: assuming the center frequency is 100MHz in non-spread mode; when down spread of –0.5% is enabled, the
center frequency shifts to 99.75MHz.).
In Center Spread mode, the Center frequency remains the same as in the non-spread mode.
Down Spread
Center Spread
Fig.9A
Fig.9B
Spread Spectrum Selection Tables
I²C BYTE5
Bit[7:5]
100
101
110
111
Table 4A
Center Frequency
(MHz)
66/100
66/100
66/100
66/100
Spread
%
± 0.25
± 0.35
± 0.5
± 0.7
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
I²C BYTE5
Bit[7:5]
000
001
010
011
Table 4B
Center Frequency
(MHz)
66/100
66/100
66/100
66/100
Document#: 38-07052 Rev. **
Spread
%
- 0.5
- 0.7
- 1.0
- 1.5
05/03/2001
Page 9 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
Maximum Ratings
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
-65ºC to + 150ºC
Operating Temperature:
0ºC to +85ºC
Maximum ESD protection
2KV
Maximum Power Supply:
5.5V
DC Parameters
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
note 1
Input Low Voltage
VIL1
-
-
1.0
Vdc
Input High Voltage
VIH1
2.0
-
-
Vdc
Input Low Voltage
VIL2
-
-
1.0
Vdc
Input High Voltage
-
VIH2
2.2
Input Low Current (@VIL =VSS)
IIL
-66
Input High Current (@VIL =VDD)
IIH
Tri-State leakage Current
Ioz
-
Dynamic Supply Current
Idd3.3V
Dynamic Supply Current
note 2
-
Vdc
-5
µA
5
µA
-
10
µA
-
-
280
mA
Sel1 = Sel0 = 1, note 4
Idd2.5V
-
-
100
mA
Sel1 = Sel0 = 1, note 4
Static Supply Current
Isdd
-
-
3.2
mA
PD# = 0, Sel1 = Sel0 = x, note 4
Input pin capacitance
Cin
-
-
5
pF
Output pin capacitance
Cout
-
-
6
pF
Pin capacitance
Lpin
-
-
7
nH
Crystal pin capacitance
Cxtal
32
34
38
pF
Crystal DC Bias Voltage
VBIAS
0.3Vdd
Vdd/2
0.7Vdd
V
Crystal Startup time
Txs
-
-
40
µS
For internal Pull up resistors, note
1 and note 3
Measured from Pin to Ground.
note 5
From Stable 3.3V power supply.
VDD=VDDS = 3.3V ±5%, VDDC = VDDI = 2.5 ± 5%, TA = 0º to +70ºC
Note1:
Note2:
Note3:
Note4:
Note5:
Applicable to input signals: Sel(0:1), PD#
Applicable to Sdata, and Sclk.
Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K.
All outputs loaded as per table 3.
Although the device will reliably interface with crystals of a 17pF – 20pF CL range, it is optimized to interface with a typical CL = 18pF
crystal specifications.
Clock name
CPU, IOAPIC, REF, USB (0:1)
PCI, SDRAM, 3V66(0,1)
Max Load (in pF)
20
30
Table 5.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 10 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
AC Parameters
66 MHz Host
100 MHz Host
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
TPeriod
Host/CPU CLK period
15.0
15.5
10.0
10.5
nS
2,7
THigh
Host/CPU CLK high time
5.2
-
3.0
-
nS
3
TLow
Host/CPU CLK low time
5.0
-
2.8
-
nS
4
Edge Rate
Rising edge rate
1.0
4.0
1.0
4.0
V/nS
Edge Rate
Failing edge rate
1.0
4.0
1.0
4.0
V/nS
T Rise
Host/CPU CLK rise time
0.4
1.6
0.4
1.6
nS
1
T Fall
Host/CPU CLK fall time
0.4
1.6
0.4
1.6
nS
1
Tperiod
IOAPIC 33 MHz CLK period
30.0
-
30.0
-
nS
2,7
THigh
IOAPIC 33 MHz CLK high time
12.0
-
12.0
-
nS
3
4
TLow
IOAPIC 33 MHz CLK low time
12.0
-
12.0
-
nS
Edge Rate
Rising edge rate
1.0
4.0
1.0
4.0
V/nS
Edge Rate
Failing edge rate
1.0
4.0
1.0
4.0
V/nS
T Rise
IOAPIC 33 MHz CLK rise time
0.4
1.6
0.4
1.6
nS
1
T Fall
IOAPIC 33 MHz CLK fall time
0.4
1.6
0.4
1.6
nS
1
Tperiod
IOAPIC 16.67 MHz CLK period
60.0
64.0
60.00
64.0
nS
2,7
THigh
IOAPIC 16.67 MHz CLK high time
25.5
-
25.5
-
nS
3
4
TLow
IOAPIC 16.67 MHz CLK low time
25.3
-
25.3
-
nS
Edge Rate
Rising edge rate
1.0
4.0
1.0
4.0
V/nS
Edge Rate
Failing edge rate
1.0
4.0
1.0
4.0
V/nS
T Rise
IOAPIC 16.67 MHz CLK rise time
0.4
1.6
0.4
1.6
nS
1
T Fall
IOAPIC 16.67 MHz CLK fall time
0.4
1.6
0.4
1.6
nS
1
Tperiod
3V66 CLK period
15.0
16.0
15.0
16.0
nS
2,7
THigh
3V66 CLK high time
5.25
-
5.25
-
nS
3
TLow
3V66 CLK low time
5.05
-
5.05
-
nS
4
Edge Rate
Rising edge rate
1.0
4.0
1.0
4.0
V/nS
Edge Rate
Failing edge rate
1.0
4.0
1.0
4.0
V/nS
T Rise
3V66 CLK rise time
0.5
2.0
0.5
2.0
nS
1
T Fall
3V66 CLK fall time
0.5
2.0
0.5
2.0
nS
1
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 11 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
AC Parameters (Cont.)
66 MHz Host
100 MHz Host
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
Tperiod
PCI CLK period (and 33 MHz IOAPIC)
30.00
-
30.0
-
nS
2,7
THigh
PCI CLK high time (& 33 MHz IOAPIC)
12.0
-
12.0
-
nS
3
4
TLow
PCI CLK low time (& 33 MHz IOAPIC)
12.0
-
12.0
-
nS
Edge Rate
Rising edge rate
1.0
4.0
1.0
4.0
V/nS
Edge Rate
Failing edge rate
1.0
4.0
1.0
4.0
V/nS
T Rise
PCI CLK rise time (& 33 MHz IOAPIC)
0.5
2.0
0.5
2.0
nS
1
T Fall
PCI CLK fall time (& 33 MHz IOAPIC)
0.5
2.0
0.5
2.0
nS
1
Tperiod
SDRAM CLK period
10.0
10.5
10.0
10.5
nS
2,7
THigh
SDRAM CLK high time
3.0
-
3.0
-
nS
3
TLow
SDRAM CLK low time
2.8
-
2.8
-
nS
4
Edge Rate
Rising edge rate
1.5
4.0
1.5
4.0
V/nS
Edge Rate
Failing edge rate
1.5
4.0
1.5
4.0
V/nS
T Rise
SDRAM CLK rise time
0.4
1.6
0.4
1.6
nS
1
T Fall
SDRAM CLK fall time
0.4
1.6
0.4
1.6
nS
1
2
Tjc-c
48 MHz Clock Cycle to Cycle Jitter
-
500
-
500
pS
tpZL,tpZH
Output enable delay (all outputs)
1.0
10.0
1.0
10.0
nS
tpLZ,tpZH
Output disable delay (all outputs)
1.0
10.0
1.0
10.00
nS
tstable
All clock Stabilization from power-up
3
3
mS
5
Notes:
1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels.
2. Period, jitter, offset and skew measured on rising edge @ 1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.
3. THigh is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
4. TLow is measured at 0.4V for all outputs.
5. The time specified is measured from when Vddq achieves its nominal operating level (typical condition Vddq = 3.3V)
the frequency output is stable and operating within specification.
6. Trise and Tfall are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V
7. The average period over any 1 uS period of time must be greater than the minimum specified period.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 12 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
Output Buffer Characteristics
Buffer Characteristics for CPU
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current
IOH1
13
-
-
mA
Vout =VDDC - 0.5V
Pull-Up Current
IOH2
25
-
-
mA
Vout = 1.2 V
Pull-Down Current
IOL1
11
-
-
mA
Vout = 0.4 V
Pull-Down Current
IOL1
25
-
-
mA
Vout = 1.2 V
Z0
Tr
13.5
0.4
-
45
-
Ω
nS
20pF Load
Tf
-
-
1.6
nS
20pF Load
Dynamic Output Impedance
Rise Time Min
Between 0.4 and 2.0 V
Fall Time Max
Between 0.4 and 2.0 V
Buffer Characteristics for PCI and 3V66
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
-
-
mA
Vout =VDDC – 0.5V
Pull-Up Current
IOH1
14
Pull-Up Current
IOH2
35
-
-
mA
Vout = 1. 5 V
Pull-Down Current
IOL1
13
-
-
mA
Vout = 0.4 V
Pull-Down Current
IOL1
40
-
-
mA
Vout = 1.5 V
Z0
Tr
12
0.5
-
55
-
Ω
nS
30pF Load
Tf
-
-
2.0
nS
30pF Load
Dynamic Output Impedance
Rise Time Min
Between 0.4 and 2.4 V
Fall Time Max
Between 0.4 and 2.4 V
Buffer Characteristics for USB (0:1) and REF
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current
IOH1
6
-
-
mA
Vout =VDD - 1.0 V
Pull-Up Current
IOH2
15
-
-
mA
Vout = 1. 5 V
Pull-Down Current
IOL1
6
-
-
mA
Vout = 0.4 V
Pull-Down Current
IOL1
22
-
-
mA
Vout = 1.5 V
Z0
Tr
20
0.4
-
60
-
Ω
nS
20pF Load
Tf
-
-
4.0
nS
20pF Load
Dynamic Output Impedance
Rise Time Min
Between 0.4 and 2.4 V
Fall Time Max
Between 0.4 and 2.4 V
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 13 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
Output Buffer Characteristics (Cont.)
Buffer Characteristics for IOAPIC
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current
IOH1
13
-
-
mA
Vout =VDDI - 0.5V
Pull-Up Current
IOH2
25
-
-
mA
Vout = 1. 0 V
Pull-Down Current
IOL1
11
-
-
mA
Vout = 0.4 V
Pull-Down Current
IOL1
25
-
-
mA
Vout = 1.4 V
Dynamic Output Impedance
Z0
13.5
45
Ω
Rise Time Min
Between 0.4 and 2.0 V
Tr
1.0
-
-
nS
20pF Load
Fall Time Max
Between 0.4 and 2.0 V
Tf
-
-
1.6
nS
20pF Load
Buffer Characteristics for SDRAM
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current
IOH1
19
-
-
mA
Vout =VDD - 1. 0 V
Pull-Up Current
IOH2
62
-
-
mA
Vout = 1. 4 V
Pull-Down Current
IOL1
18
-
-
mA
Vout = 0.4 V
Pull-Down Current
IOL1
59
-
-
mA
Vout = 1.5 V
Dynamic Output Impedance
Z0
10
24
Ω
Rise Time Min
Between 0.4 and 2.4 V
Tr
0.4
-
-
nS
30pF Load
Fall Time Max
Between 0.4 and 2.4 V
Tf
-
-
1.33
nS
30pF Load
VDD=VDDS=3.3V ±5%, VDDC=VDDI=2.5±5%, TA=0 to 70ºC
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 14 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
Suggested Crystal Oscillator Parameters
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Frequency
Fo
12.00
14.31818
16.00
MHz
Tolerance
TC
-
-
+/-100
PPM
Note 1
TS
-
-
+/- 100
PPM
Stability (Ta -10 to +60C) Note 1
TA
-
-
5
PPM
Aging (first year @ 25C) Note 1
Mode
OM
-
-
-
Load Capacitance
CL
-
18
-
pF
Effective Series
resistance (ESR)
R1
-
40
-
Ohms
Power Dissipation
DL
-
-
0.10
mW
Parallel Resonant, Note 1
The crystal’s rated load. Note 1
Note 1
Note 1
Crystal’s
internal package
Shunt Capacitance
CO
-8
pF
capacitance (total)
Note1: For best performance and accurate Center frequencies of this device, It is recommended but not mandatory that
the chosen crystal meets these specifications
For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the
effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit
traces, the clock generator and any onboard discrete load capacitors.
Budgeting Calculations
Device pin capacitance: Cxtal = 36pF
In order to meet the specification for CL = 18pF following the formula:
CL =
C XIN xC XOUT
C XIN + C XOUT
Then the board trace capacitance between Xin and the crystal should be no more than 2pF. (same is applicable to the trace
between Xout and the crystal)
In this case the total capacitance from the crystal to Xin will be 36pF. Similarly the total capacitance between the crystal and Xout
will be 36pF. Hence using the above formula:
CL =
36 pFx36 pF
= 18 pF
36 pF + 36 pF
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 15 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
Package Drawing and Dimensions
56 Pin SSOP Outline Dimensions
INCHES
SYMBOL
C
L
H
E
D
a
A2
MIN
NOM
MAX
MIN
NOM
MAX
A
0.095
0.102
0.110
2.41
2.59
2.79
A1
0.008
0.012
0.016
0.20
0.31
0.41
A2
0.088
0.090
0.092
2.24
2.29
2.34
B
0.008
0.010
0.0135
0.203
0.254
0.343
C
0.005
-
0.010
0.127
-
0.254
D
.720
.725
.730
18.29
18.42
18.54
E
0.292
0.296
0.299
7.42
7.52
7.59
e
A
A1
MILLIMETERS
0.025 BSC
0.635 BSC
H
0.400
0.406
0.410
10.16
10.31
10.41
a
0.10
0.013
0.016
0.25
0.33
0.41
L
0.024
0.032
0.040
0.61
0.81
1.02
a
0º
5º
8º
0º
5º
8º
X
0.085
0.093
0.100
2.16
2.36
2.54
e
B
Ordering Information
Part Number
Package Type
Production Flow
C9811X2AYB
56 PIN SSOP
Commercial, 0 to 70ºC
Marking: Example:
Cypress
C9811X2
Date Code, Lot #
C9811X2AYB
Flow
B = Commercial, 0 to 70ºC
Package
Y = SSOP
Revision
Device Number
Notice
Cypress Semiconductor Corporation reserves the right to change or modify the information contained in this data sheet, without
notice Cypress Semiconductor Corporation does not assume any liability arising out of the application or use of any product or
circuit described herein. Cypress Semiconductor Corporation does not convey any license under its patent rights nor the rights of
others Cypress Semiconductor Corporation does not authorize its products for use as critical components in life-support systems or
critical medical instruments, where a malfunction or failure may reasonably be expected to result in significant injury to the user.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 16 of 17
APPROVED PRODUCT
C9811x2
Low EMI Clock Generator for Intel 810 Chipset Systems
Document Title: C9811x2 Low EMI Clock Generator for Intel® 810 Chipset Systems
Document Number: 38-07052
Rev.
**
ECN
No.
107060
Issue
Date
06/11/01
Orig. of
Change
IKA
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Description of Change
Convert from IMI to Cypress
Document#: 38-07052 Rev. **
05/03/2001
Page 17 of 17