ETC IMIC9630

APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Product Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports PentiumâIII, K6, and Socket 7 CPU’s
Designed to SiS630 & SiS540 Chipset requirements
3 copies of CPU Clock (CPU[0:2] )
14 copies of SDRAM Clock (SDRAM[0:13]
7 copies of PCI Clock
2 REF(0:1) Clock outputs
1 USB Clock (Non SSC), 48MHz
1 programmable SIO (Non SSC), 24/48MHz
133 MHz SDRAM support
Cypress Spread Spectrum for best EMI reduction
SMBus Support with read back capabilities.
Dial-a-Frequency™ Feature
48 Pin SSOP package.
Block Diagram
30pF
Xin
VDD
300K
1
REF1
30pF
VDDcpu
3
CPU(0:2)
VDD
s3
s2
s1
s0
14
sdram
SDRAM(0:13)
VDD
5
SDATA
SCLK
sdata
sclk
PCI(2:6)
VDD
pci
PLL1
PCI0/S1
1
VDD
1
Rin
48
1
PCI1/S2
48MHz/S0
VDD
VDD
i2c-clk
i2c-data
24 or 48
1
PLL2
FS2
FS1
FS0
CPU
SDRAM
PCICLK
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.6
100.0
150.0
133.3
66.8
100.0
100.0
133.3
66.9
97.2
70.0
95.0
95.0
112.0
97.0
96.0
100.0
100.0
100.0
100.0
133.6
133.3
150.0
133.3
66.9
97.2
105.0
95.0
126.7
112.0
129.3
96.0
33.3
33.3
37.5
33.3
33.4
33.3
37.5
33.3
33.4
32.4
35.0
31.6
31.6
37.3
32.4
32.0
Table 1
Note: *Programmable to 48 MHz via SMBus
REF0/S3
1
cpu
FS3
Pin Configuration
VDD
Xout
Rin
Frequency Table (MHz)
24_48MHz
VDD
S3 / REF0
VSS
XIN
XOUT
VDD
S1/ PCI0
S2 / PCI1
PCI2
VSS
PCI3
PCI4
PCI5
PCI6
VDD
VSS
SDRAM0
SDRAM1
VDD
SDRAM2
SDRAM3
VSS
SDATA
SCLK
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
REF1
VDDC
CPU0
CPU1
VSS
CPU2
VDD
SDRAM13
SDRAM12
VSS
SDRAM11
SDRAM10
VDD
SDRAM9
SDRAM8
VSS
SDRAM7
SDRAM6
VDD
SDRAM5
SDRAM4
VDD
S0 / 48MHz
24_48MHz
Fig.1
Fig.2
Cypress Semiconductor Corporation
3901 North First St.
San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
Document #: 38-07035 Rev. *A
12/18/2002
Page 1 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Pin Description
PIN No.
2
Pin Name
S3/ REF0
PWR
VDD
I/O
I/O
48
REF1
VDD
O
4
5
7
XIN
XOUT
S1/ PCI0*
VDD
VDD
VDD
I
O
I/O
8
S2/ PCI1*
VDD
I/O
9,11,12,13,
14
25
PCI(2:6)
VDD
O
24/48MHz
VDD
O
S0 / 48MHz*
VDD
I/O
28
29
17,18,20,21,
28,29,31,32,
34,35,37,38,
40,41
43,45,46
SDATA
SCLK
SDRAM(0:13)
VDD
VDD
VDD
I
I
O
VDDC
O
1,6,15,19,
27, 30,36,42
47
3,10,16,22,
33,39,44
VDD
-
2.5V or 3.3V Host bus clock outputs. See table 1, page 1 for
frequency selection.
3.3V Common Power Supply
VDDC
VSS
-
2.5V or 3.3V Power Supply’s for CPU (0:2) clock outputs.
Common Ground pin.
26
CPU(0:2)
Description
3.3V 14.318 MHz clock output. This Is a power on bi-directional pin.
During power up, this pin is an input “S3” for setting the CPU
frequency (see table1, page 1) (see app note, page 5). When the
power reaches the rail, this pin becomes a buffered output of the
signal applied at Xin (typically 14.318 MHz).
This pin is a buffered output of the signal applied at Xin (typically
14.318)
14.318MHz Crystal input
14.318MHz Crystal output
This is a power on bi-directional pin. During power up, this pin is an
input “S1” for setting the CPU frequency (see table1, page 1) (see
app not, page 5). When the power reaches the rail, this pin becomes
a PCI0 clock output.
This is a power on bi-directional pin. During power up, this pin is an
input “S2” for setting the CPU frequency (see table1, page 1) (see
app not, page 5). When the power reaches the rail, this pin becomes
a PCI1 clock output.
3.3V PCI clock outputs.
This pin is programmable to 24MHz or 48 MHz clock output through
SMBus. It defaults to 24MHz at power up.
This is a power on bi-directional pin. During power up, this pin is an
input “S0” for setting the CPU frequency (see table1, page 1) (see
app note, page 5). When the power reaches the rail, this pin becomes
a 48MHz clock output. This clock conforms to the USB spec. of
+167ppm.
SMBus compatible SDATA input. Has an internal pull-up (>100KΩ)
SMBus compatible SCLK input. Has an internal pull-up (>100KΩ)
3.3V SDRAM clock outputs. See table1, p.1 for frequency selection.
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
*Note: These pins have pulldown resistors, typical value 250 Ω.
Cypress Semiconductor Corporation
3901 North First St.
San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
Document #: 38-07035 Rev. *A
12/18/2002
Page 2 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Device Clock Phase Relationships
Condition 1: CPU Frequency = SDRAM Frequency
Applicable to the follow ing selections: S(4:0) = 00001, 00111, 01000, 01001, 01011, 01101, 01111, 10001, 10111,11010, 11011, 11100, 11101, 11110, 11111
Internal VCO
SDRAM
to CPU
CPU
or
to SDRAM
TSkew 3
Condition 2: CPU Frequency = 1.5 X SDRAM Frequency or SDRAM Frequency = 1.5 X CPU Frequency
Applicable to the follow ing selections: S(4:0) = 00000, 00010, 00110, 01010, 10000, 10010, 10101
Internal VCO
SDRAM
to CPU
CPU
or
to SDRAM
TSkew 3
Condition 3: CPU Frequency = 1.3 X SDRAM Frequency or SDRAM Frequency = 1.3 X CPU Frequency
Applicable to the follow ing selections: S(4:0) = 00011, 00101, 01100, 01110, 10011, 10100, 10110, 11000, 11001
Internal VCO
SDRAM
to CPU
CPU
or
to SDRAM
TSkew 3
Condition 4: SDRAM Frequency = 2 X CPU Frequency
Applicable to the follow ing selection: S(4:0) = 00100
Internal VCO
SDRAM
CPU
TSkew 3
Fig.3
Frequency Smooth Switching Groups
Group
S(4:0)
1
2
3
00001, 00010, 00111, 01101, 10001, 10010, 10111, 11010, 11011, 11100, 11101, 11110, 11111
00000, 00011, 00110, 01010, 10000, 10101
00100, 00101, 01000, 01001, 01011, 01100, 01110, 01111, 10011, 10100, 10110, 11000, 11001
Table 2
Table 2 above describes 3 different groups of frequencies. Within the same group, frequency may be switched through
SMBus byte 0 without causing any glitching or clock discontinuity at the CPU(0:2) outputs, therefore allowing frequency
smooth switching of the clock.
Switching frequency from one group to another is permitted but will cause the CPU(0:2) clocks to jump immediately to
the next frequency. (non smooth switching.).
Cypress Semiconductor Corporation
3901 North First St.
San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
Document #: 38-07035 Rev. *A
12/18/2002
Page 3 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Power on Bi-Directional Pins
Power Up Condition:
Pins 2,7,8,and 26 are Power up bi-directional pins used for selecting the host frequency in page 1, table 1. During
power-up of the device, these pins are in input mode (see Fig 4, below), therefore; they are considered input select pins
internal to the IC. After a settling time, the selection data is latch into the internal control register and these pins become
a clock outputs.
VDD Rail
Power Supply
Ramp
REF0 / S3
PCI0 / S1
PCI1 / S2
48MHZ / S0
Hi-Z Input
-
Toggle Outputs
Select data is latched into register, then pin becomease ref clock output signal.
Fig.4
VDD
Strapping Resistor Options:
The power up bi-directional pins have a large value pulldown each (250KΩ), therefore, a selection “0” is the
default. If the system uses a slow power supply (over
5mS settling time), then it is recommended to use an
external Pull-Down (Rdn) in order to insure a Low
selection. In this case, the designer may choose one of
two configurations, see Fig.5A and B.
Fig. 5A represents an additional pull down resistor Rdn
= 50KΩ connected from the pin to the ground plane,
which allows a faster pull to a low level.
If a selection “1” is desired, then a jumper is placed on
JP1 to a Rup = 10KΩ resistor as implemented as
shown in Fig.5A. Please note the selection resistors
(Rup and Rdn) are placed before the Damping resistor
(Rd) close to the pin.
10K
JP1
IMIC9630
Load
Bidirectional
Rd
50K
Fig.5A
JP2
VDD
Fig. 5B represent a single resistor 10KΩ connected to a
3-way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads 3
and 2.
1
IMIC9630
2
3
10K
Load
Bidirectional
Rd
Fig.5B
Cypress Semiconductor Corporation
3901 North First St.
San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
Document #: 38-07035 Rev. *A
12/18/2002
Page 4 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
2-Wire SMBus Control Interface
The 2-wire control interface implements a read/write slave only interface according to SMBus specification (IC12, 1996).
The device can be read back by using standard SMBus command bytes. Sub addressing is not supported, thus all
preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock
output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported.
During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is
high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 1 in read mode. R/W# = 0 in write mode.
A maximum of 10 bytes of data may be written/Read Data is transferred MSB first at a max rate of 100kbits/S.The
device will not respond to any other control interface conditions.
In the Write mode (See fig6A, p.9), the clock gen. acknowledges Address Byte, D2, then receives two additional bytes:
1) “Command Code “ byte, and
2) “Byte Count” byte. Must be programmed to FF for correct operation.
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.
Subsequently, the below-described sequence (Byte 0, Byte 1, Byte2,) will be valid and acknowledged.
In the Read Mode (See fig6B, p.9), the clock gen. acknowledges Address D3, and immediately transmits data starting
with Byte count, then Byte 0, 1, 2, ... After each transmitted byte, this device waits for an acknowledge before
transmitting the next byte.
Serial Control Registers
NOTE: Power up conditions for each bit are listed in the “@Pup” column.
Byte 0: Frequency, Function Select Register
Bit @Pup Pin# Description, see page 8 for SSCG description.
7
0
n/a
S4 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1
6
0
n/a
S2 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1
5
0
n/a
S1 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1
4
0
n/a
S0 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1
3
0
n/a
0 = frequency selected by hardware, pins
1 = frequency selection via SMBus byte0.
2,7,8,26
bits 4,5,6,2,7
2
0
n/a
S3 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1
1
0
n/a
0 = Spread Spectrum disabled
1 = Spread spectrum enabled
0
0
n/a
0 = Running
1 = Test mode.
Cypress Semiconductor Corporation
3901 North First St.
San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
Document #: 38-07035 Rev. *A
12/18/2002
Page 5 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
S4
S3
S2
S1
S0
Description
Bit7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
66.6
100.0
150.0
133.3
66.8
100.0
100.0
133.3
66.8
97.0
70.0
95.0
95.0
112.0
97.0
96.2
66.8
100.2
166.0
100.2
75.0
83.3
105.0
133.6
110.3
115.0
120.0
138.0
140.0
145.0
147.5
160.0
SDRAM
100.0
100.0
100.0
100.0
133.6
133.3
150.0
133.3
66.8
97.0
105.0
95.0
126.7
112.0
129.3
96.2
100.2
100.2
110.7
133.6
100.0
125.0
140.0
133.6
147.0
153.3
120.0
138.0
140.0
145.0
147.5
160.0
Table 3.
PCI
33.3
33.3
37.5
33.3
33.4
33.3
37.5
33.3
33.4
32.3
35.0
31.7
31.7
37.3
32.3
32.1
33.4
33.4
33.3
33.4
37.5
31.3
35.0
33.4
36.8
38.3
30.0
34.5
35.0
36.3
29.5
32
Spread Spectrum, MBS0 = MBS1 = 1, SSTS = 1
0 to –0.5%
0 to –0.5%
+/- 0.25%
0 to –0.5%
0 to –0.5%
0 to –0.5%
+/- 0.25%
0 to –0.5%
+/- 0.25%
0 to –0.5%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
0 to –0.5%
0 to –0.5%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
TEST Function Table: Applicable only when bit0=1 in Byte0.
CPU (0:2)
= Xin / 3
PCI (0:6)
= Xin / 6
SDRAM (0:13)
= Xin / 2
REF(0,1)
= Xin
48MHz
= Xin
24_48MHz
= Xin / 2
Test Clock should be applied at Xin pin.
Cypress Semiconductor Corporation
3901 North First St.
San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
Document #: 38-07035 Rev. *A
12/18/2002
Page 6 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Serial Control Registers (Cont.)
Byte 1: CPU Clock Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
1
Selects Frequency at pin 25
1 = selects 24MHz (default)
0 = selects 48MHz
6
1
SSTS, See Table 4, p 11
5
1
Reserved for IMI test^
4
1
Reserved for IMI test^
3
1
43
CPU2 enable/Stopped
2
1
45
CPU1 enable/Stopped
1
1
46
CPU0 enable/Stopped
0
1
Reserved for IMI test^
Byte 2: PCI Clock Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
1
Reserved
6
1
14
PCI6 enable/Stopped
5
1
13
PCI5 enable/Stopped
4
1
12
PCI4 enable/Stopped
3
1
11
PCI3 enable/Stopped
2
1
9
PCI2 enable/Stopped
1
1
8
PCI1 enable/Stopped
0
1
7
PCI0 enable/Stopped
Byte 3: SDRAM Clock Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
1
32
SDRAM7 enable/Stopped
6
1
31
SDRAM6 enable/Stopped
5
1
29
SDRAM5 enable/Stopped
4
1
28
SDRAM4 enable/Stopped
3
1
21
SDRAM3 enable/Stopped
2
1
20
SDRAM2 enable/Stopped
1
1
18
SDRAM1 enable/Stopped
0
1
17
SDRAM0 enable/Stopped
Byte 4: Additional SDRAM Clock Register (1=enable, 0=Stopped)
Bit
@Pup
Pin#
Description
7
1
25
24_48MHz enable/Stopped
6
1
26
48 MHz enable/Stopped
5
1
41
SDRAM13 enable/Stopped
4
1
40
SDRAM12 enable/Stopped
3
1
38
SDRAM11 enable/Stopped
2
1
37
SDRAM10 enable/Stopped
1
1
35
SDRAM9 enable/Stopped
0
1
34
SDRAM8 enable/Stopped
Cypress Semiconductor Corporation
3901 North First St.
San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
Byte 5: Peripheral Control (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
1
MBS1, See table 4, p. 11 for
Spread Spectrum
6
1
MBS0, See table 4, p.11 for
Spread Spectrum
5
1
S3# *
4
1
S2# *
3
1
S1# *
2
1
S0# *
1
1
48
REF1 enable/Stopped
0
1
2
REF0 enable/Stopped
*Inverted read back of hardware settings.
Byte 6: Reserved Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
0
Reserved for IMI test^
6
0
5
0
4
0
Reserved for IMI test^
3
0
Reserved for IMI test
2
1
Reserved for IMI test
1
0
N9, MSB
0
0
N8
Byte 7: Dial-a-Frequency® N Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
0
N7
6
0
N6
5
0
N5
4
0
N4
3
0
N3
2
0
N2
1
0
N1
0
0
N0, LSB
Byte 8: Dial-a-Frequency® R Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
0
R6, MSB
6
0
R5
5
0
R4
4
0
R3
3
0
R2
2
0
R1
1
0
R0, LSB
0
0
1 = Enable SMBus N and R
Document #: 38-07035 Rev. *A
12/18/2002
Page 7 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Dial-a-Frequency™ Feature
™
SMBus Dial-a-frequency feature is available in this device via byte7, and byte 8
These bytes allow the user to enter the N and R values that will allow them to program any CPU frequency
desired following the formula:
Fcpu =
P× N
R
Where N and R values are programmed in binary into byte 7 for N and byte 8 for R. See table below for min and max
allowed values.
R
42
43
44
45
46
47
48
49
50
51
Min N
44
45
46
47
48
49
50
51
52
53
Max N
87
90
92
94
96
98
100
102
104
107
P is a large value PLL constant that depends on the last frequency selection achieved through the hardware selectors
(S3, S2, S1, S0) or through the software selectors (byte0 , bits 7,6,5,4,2). P value may be determined from the following
table:
S(4:0)
00001, 00010, 00111, 01101, 10001,
10010, 10111, 11010, 11011, 11100,
11101, 11110, 11111
P
96016000
00000, 00011, 00110, 01010, 10000,
10101
64010667
00100, 00101, 01000, 01001, 01011,
01100, 01110, 01111, 10011, 10100,
10110, 11000, 11001
48008000
6
Therefore, if a 145MHz (use 145x10 )value is desired, then we should apply 145 into equation 1, and start by choosing
R to be 47 (assume the last frequency selection has the value P = 96016000):
6
145X10 = 96016000 X N
47
=> N = 70.97775371
Cypress Semiconductor Corporation
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Document #: 38-07035 Rev. *A
12/18/2002
Page 8 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Dial-a-Frequency™ Feature (Cont.)
Since this N number must be entered in Binary, it can only be an integer, so it must be rounded up or down. Here we
can rounded it up to 71, which will give us an exact CPU frequency of:
Fcpu = 96016000 X N = 145.045 MHz (accuracy + 310 ppm)
47
If the above frequency is not accurate enough, then you must choose another R value and start from the beginning. For
example choose R = 49 and this will yield an N = 73.99808365, which is rounded to 74. If the 74 is applied in the
formula 1, then Fcpu = 145.0038 MHz (accuracy + 26 ppm).
Other R values within the above limits may also be evaluated.
SMBus Communication Waveform
IMI Device
Master Device
1
1
0
1
0
0
1
ACK
0
ACK
MSB
(Don't Care)
8
8
START
ACK
BYTE 0
BYTE N
(Valid)
(Valid)
1
8
8
STOP CONDITION
Fig.6a (WRITE)
IMI Device
1
ACK
LSB
SCLK
Master Device
BYTE COUNT
COMMAND BYTE
(Don't Care)
SDATA
ACK
0
1
0
0
1
ACK BYTE COUNT
ACK
1
(Valid)
SDATA
MSB
START CONDITION
Cypress Semiconductor Corporation
3901 North First St.
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ACK
BYTE N
NO ACK
ACK
(Valid)
(Valid)
8
8
(Valid)
LSB
8
SCLK
BYTE1
BYTE 0
8
STOP CONDITION
Fig.6b (READ)
Document #: 38-07035 Rev. *A
12/18/2002
Page 9 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
SMBus Test Circuitry
+ 5V
Device under Test
2.2 K
DATAIN
SDATA
+ 5V
SCLK
2.2 K
+ 5V
DATAOUT
2.2 K
CLOCK
Fig.7
Note: Buffer is 7407 with VCC @ 5.0 V
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic
Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the
center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore
spreading the same amount of energy over a spectrum. This technique is achieved by modulating the clock down from
(Fig.8A) or around the center (Fig.8B) of its resting frequency by a certain percentage (which also determines the energy
distribution bandwidth). In this device, Spread Spectrum is enabled by setting I²C byte0, bit1 = 1. The default of the
device at power up keeps the Spread Spectrum disabled, it is therefore, important to have I²C accessibility to turn-on the
Spread Spectrum function. Once the Spread Spectrum is enabled, the spread bandwidth option is selected by MBS(0:1)
in I²C byte 5, bit6 and bit 7, and SSTS Byte1, Bit6 following table 4 below.
In Down Spread mode the center frequency is shifted down from its rested (non-spread) value by ½ of the total spread
%. (eg.: assuming the center frequency is 100MHz in non-spread mode; when down spread of –0.5% is enabled, the
center frequency shifts to 99.75MHz.).
Cypress Semiconductor Corporation
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Document #: 38-07035 Rev. *A
12/18/2002
Page 10 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Spread Spectrum Clock Generation (SSCG) (Cont.)
In Center Spread mode, the Center frequency remains the same as in the non-spread mode.
Down Spread
Center Spread
Fig.8A
Fig.8B
Spread Spectrum Selection Table
SSTS
0
0
0
0
1
1
1
1
MBS 1
0
0
1
1
0
0
1
1
MBS 0
0
1
0
1
0
1
0
1
Table 4
Spread%
- 0.5
+/- 0.125
+/- 0.5
+/- 0.25
-0.5
+/- 0.125
+/- 0.5
See table 3, (default)
Maximum Ratings1
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum ESD protection
Maximum Power Supply:
-65ºC to + 150ºC
0ºC to +70ºC
2KV
5.5V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
1
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Cypress Semiconductor Corporation
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San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
Document #: 38-07035 Rev. *A
12/18/2002
Page 11 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
DC Parameters
Characteristic
Symbol
Input Low Voltage
Input High Voltage
Input Low Current (@VIL = VSS)
Input High Current (@VIL =VDD)
Min
Typ
2.2
-
Max
Units
Conditions
1.0
-5
5
Vdc
Vdc
µA
µA
Note 2
VIL2
VIH2
IIL
IIH
66
Tri-State leakage Current
Ioz
-
-
10
µA
Dynamic Supply Current
Idd3.3V
-
-
400
mA
S(3:0) = 0101, Note 4
Dynamic Supply Current
Idd2.5V
-
-
100
mA
S(3:0) = 0111, Note 4
Input pin capacitance
Cin
-
-
5
pF
Output pin capacitance
Cout
-
-
6
pF
Pin inductance
Lpin
-
-
7
nH
Crystal pin capacitance
Xin/Xout
30
32
34
pF
Crystal DC Bias Voltage
VBIAS
0.3Vdd
Vdd/2
0.7Vdd
V
Crystal Startup time
Txs
-
-
40
µS
For internal Pull down resistors,
Notes 1,3
Measured from Pin to Ground.
Note 5
From Stable 3.3V power supply.
VDD = 3.3V ±5%, VDDC = 2.5 ± 5%, TA = 0º to +70ºC
Note1:
Note2:
Note3:
Note4:
Note5:
Applicable to S(0:3).
Applicable to Sdata, and Sclk.
Although internal pull-down resistors have a typical value of 250K, this value may vary between 200K and 500K.
All outputs loaded as per table 5 below.
Although the device will reliably interface with crystals of a 15pF – 20pF CL range, it is optimized to interface with a typical CL = 16pF
crystal specifications.
Clock Name
CPU, REF
PCI, SDRAM
24MHz, 48MHz
Max Load (in pF)
20
30
15
Table 5
Cypress Semiconductor Corporation
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Document #: 38-07035 Rev. *A
12/18/2002
Page 12 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
AC Parameters
133 MHz Host
100 MHz Host
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
TPeriod
CPU(0:2) period
7.45
8.0
9.98
10.5
nS
5, 6, 8
THIGH
CPU(0:2) high time
1.87
-
3.0
-
nS
6,10
TLOW
CPU(0:2) low time
1.67
-
2.8
-
nS
6, 11
Tr / Tf
CPU(0:2) rise and fall times
0.4
1.9
0.4
2.1
nS
6, 7
TSKEW0
Any CPU to Any CPU Skew time
-
175
-
175
pS
6, 8, 9
TCCJ
CPU(0:2) Cycle to Cycle Jitter
-
250
-
250
pS
6,8,9,14
TPeriod
SDRAM[0:13] period
7.46
8.0
9.89
10.5
nS
5, 6, 8
THIGH
SDRAM[0:13] high time
1.87
-
3.0
-
nS
6,10
TLOW
SDRAM[0:13] low time
1.67
-
2.63
-
nS
6, 11
Tr / Tf
SDRAM[0:13] rise and fall times
0.4
1.69
0.4
1.88
nS
6, 7
TSKEW1
Any SDRAM to Any SDRAM
-
500
-
500
pS
6, 8, 9
TCCJ
SDRAM[0:13] Cycle to Cycle Jitter
-
250
-
250
pS
6,8,9,14
TPeriod
PCI(0:6) period
29.93
-
29.94
-
nS
5, 6, 8
THIGH
PCI(0:6) period
12.0
-
12.0
-
nS
6,10
TLOW
PCI(0:6) low time
12.0
-
12.0
-
nS
6, 11
Tr / Tf
PCI(0:6) rise and fall times
0.5
2.9
0.5
2.9
nS
6, 7
TSKEW2
(Any PCI clock) to (Any PCI clock)
-
500
-
500
pS
6, 8, 9
TCCJ
PCI(0:6) Cycle to Cycle Jitter
-
500
-
500
pS
6, 8, 9
TPeriod
48MHz period ( conforms to
+167ppm max)
20.8212
20.8333
20.8299
20.8442
nS
5, 6, 8
Tr / Tf
48MHz rise and fall times
1.0
4.0
1.0
4.0
nS
6, 7
TCCJ
48MHz Cycle to Cycle Jitter
-
500
-
500
pS
6, 8, 9
TPeriod
24MHz period
41.6087
41.6666
41.6026
41.6666
nS
5, 6, 8
Tr / Tf
24MHz rise and fall times
1.0
4.0
1.0
4.0
nS
6, 7
TCCJ
24 MHz Cycle to Cycle Jitter
-
500
-
500
pS
6, 8, 9
TPeriod
REF(0:1) period
69.8167
71.0
69.8017
71.0
nS
5, 6, 8
Tr / Tf
REF0 rise and fall times
1.0
4.0
1.0
4.0
nS
6, 7
Tr / Tf
REF1 rise and fall times
1.0
4.0
1.0
4.0
nS
6, 7
TCCJ
REF(0:1) Cycle to Cycle Jitter
-
1000
-
1000
pS
6, 8
tpZL, tpZH
Output enable delay (all outputs)
1.0
10.0
1.0
10.0
nS
13
tpLZ, tpHZ
Output disable delay (all outputs)
1.0
10.0
1.0
10.0
nS
13
tstable
All clock Stabilization from power-up
3
mS
12
TSKEW3
CPU to SDRAM (see fig.3, p.3)
354
pS
5, 6, 8
Cypress Semiconductor Corporation
3901 North First St.
San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
3
0
340
0
Document #: 38-07035 Rev. *A
12/18/2002
Page 13 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Note 5: This parameter is measured as an average over 1uS duration, with a crystal center frequency of 14.31818MHz
Note 6: All outputs loaded as per table 5.
Note 7: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V
and 2.0V for 2.5V signals (see Fig.9A and Fig.9B)
Note 8: Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V signals. (see
Figs.9A & 9B)
Note 9: This measurement is applicable with Spread ON or Spread OFF.
Note 10:Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals, (see
Figs. 9A & 9B)
Note 11:Probes are placed on the pins, and measurements are acquired at 0.4V.
Note 12:The time specified is measured from when all VDD’s reach their respective supply rail (3.3V and 2.5V) till the frequency
output is stable and operating within the specifications
Note 13:Measured from when both SEL1 and SEL0 are low
Note 14:Guaranteed by design in system Application (CPU frequency = SDRAM frequency)
Test and Measurement Condition
Output under Test
Probe
Load Cap
3.3V signals
2.5V signals
tDC
tDC
-
-
-
-
3.3V
2.5V
2.4V
2.0V
1.5V
1.25V
0.4V
0.4V
0V
0V
Tf
Tr
Fig. 9A
Cypress Semiconductor Corporation
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Tr
Tf
Fig. 9B
Document #: 38-07035 Rev. *A
12/18/2002
Page 14 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Output Buffer Characteristics
CPU(0:2), VDDC = 2.5V +/-5%
Characteristic
Symbol
Min
Pull-Up Current
IOH1
-14.8
-25
-35.5
mA
Vout =VDDC - 0.5V
Pull-Up Current
IOH2
-28.4
-58
-79.5
mA
Vout = 1.25 V
Pull-Down Current
IOL1
11.7
20
29.3
mA
Vout = 0.4 V
Pull-Down Current
IOL2
27
56
67.6
mA
Vout = 1.2 V
45
Ω
Dynamic Output Impedance
Z0
CPU(0:2), VDDC = 3.3V +/-5%
Characteristic
Symbol
Typ
13.5
Max
Units
Min
Typ
Max
Units
Conditions, VDDC = 2.5V
Conditions, VDDC= 3.3V
Pull-Up Current
IOH1
17
28
40
mA
Vout =VDDC - 0.5V
Pull-Up Current
IOH2
53
100
138
mA
Vout = 1.25 V
Pull-Down Current
IOL1
13
22
32
mA
Vout = 0.4 V
Pull-Down Current
IOL2
35
68
83
mA
Vout = 1.2 V
Z0
10.4
37
Ω
Max
Units
Dynamic Output Impedance
PCI(0:6), and REF0
Characteristic
Symbol
Min
Typ
Pull-Up Current
IOH1
-33
-58
-194
mA
Vout =VDD - 1.0 V
Pull-Up Current
IOH2
-30
-54
-184
mA
Vout = 1. 5 V
Pull-Down Current
IOL1
9.4
18
38
mA
Vout = 0.4 V
Pull-Down Current
IOL2
28
55
148
mA
Vout = 1.5 V
Z0
12
55
Ω
Max
Units
Dynamic Output Impedance
24MHz, 48MHz, and REF1
Characteristic
Conditions
Symbol
Min
Typ
Pull-Up Current
IOH1
-29
-46
-99
mA
Vout =VDD - 1.0 V
Pull-Up Current
IOH2
-27
-43
-92
mA
Vout = 1. 5 V
Pull-Down Current
IOL1
9
13
27
mA
Vout = 0.4 V
Pull-Down Current
IOL2
26
39
79
mA
Vout = 1.5 V
Z0
20
60
Ω
Max
Units
Dynamic Output Impedance
Buffer Characteristics for SDRAM(0:13)
Characteristic
Symbol
Min
Typ
Conditions
Conditions
Pull-Up Current
IOH1
-72
-116
-198
mA
Vout =VDD - 1. 0 V
Pull-Up Current
IOH2
-68
-110
-188
mA
Vout = 1. 4 V
Pull-Down Current
IOL1
23
34
53
mA
Vout = 0.4 V
Pull-Down Current
IOL1
64
98
159
mA
Vout = 1.5 V
Z0
10
24
Ω
Dynamic Output Impedance
VDD=3.3V ±5%, TA=0 to 70ºC
Cypress Semiconductor Corporation
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San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
Document #: 38-07035 Rev. *A
12/18/2002
Page 15 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Suggested Oscillator Crystal Parameters
Characteristic
Symbol
Min
Typ
Max
Units
Frequency
Fo
12.00
14.31818
16.00
MHz
Tolerance
TC
-
-
+/-100
PPM
Note 1
TS
-
-
+/- 100
PPM
Stability (TA -10 to +60C) Note 1
TA
-
-
5
PPM
Aging (first year @ 25C) Note 1
-
-
-
-
CXTAL
-
16
-
Operating Mode
Load Capacitance
Conditions
Parallel Resonant, Note 1
pF
The crystal’s rated load. Note 1
Effective Series
RESR
40
Ohms
Note 2
Resistance (ESR)
Note1: For best performance and accurate frequencies from this device, It is recommended but not mandatory that the
chosen crystal meets or exceeds these specifications
Note 2: Larger values may cause this device to exhibit oscillator startup problems
To obtain the maximum accuracy, the total circuit loading capacitance should be equal to CXTAL. This loading
capacitance is the effective capacitance across the crystal pins and includes the clock generating device pin
capacitance (CFTG), any circuit traces (CPCB), and any onboard discrete load capacitors (CDISC).
The following formula and schematic may be used to understand and calculate either the loading specification of a crystal for a
design or the additional discrete load capacitance that must be used to provide the correct load to a known load rated crystal.
CL = (CXINPCB + CXINFTG + CXINDISC) X (CXOUTPCB + CXOUTFTG + CXOUTDISC)
(CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB + CXOUTFTG + COUTDISC)
Where:
CXTAL
CXOUTFTG
CXOUTFTG
CXINPCB
CXOUTPCB
CXINDISC
CXOUTDISC
=
=
=
=
=
=
=
the load rating of the crystal
the clock generators XIN pin effective device internal capacitance to ground
the clock generators XOUT pin effective device internal capacitance to ground
the effective capacitance to ground of the crystal to device PCB trace
the effective capacitance to ground of the crystal to device PCB trace
any discrete capacitance that is placed between the XIN pin and ground
any discrete capacitance that is placed between the XOUT pin and ground
CXINPCB
CXINDISC
CXOUTPCB
CXOUTDISC
XIN
CXINFTG
XOUT
CXOUTFTG
Clock Generator
As an example, and using this formula for this datasheet’s device, a design that has no discrete loading capacitors
(CDISC) and each of the crystal to device PCB traces has a capacitance (CPCB) to ground of 2pF (typical value) would
calculate as:
CL = (2pF + 30pF + 0pF) X (2pF + 30pF + 0pF)
(2pF + 30pF + 0pF) + (2pF + 30pF + 0pF)
= 32 X 32
32 + 32
= 16 pF
Therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design
example, you should specify a parallel cut crystal, with CL = 16pF.
Cypress Semiconductor Corporation
3901 North First St.
San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
Document #: 38-07035 Rev. *A
12/18/2002
Page 16 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Package Drawing and Dimensions
48 Pin SSOP Outline Dimensions
INCHES
SYMBOL
C
MIN
MILLIMETERS
NOM
MAX
MIN
NOM
MAX
A
0.095
0.102
0.110
2.41
2.59
2.79
A1
0.008
0.012
0.016
0.203
0.305
0.406
A2
0.088
-
0.092
2.24
-
2.34
B
0.008
-
0.0135
0.203
-
0.343
C
0.005
-
0.010
0.127
-
0.254
D
0.620
0.625
0.630
15.75
15.88
16.00
E
0.291
0.295
0.299
7.39
7.49
7.60
L
H
E
D
a
A2
A
e
A1
B
e
0.025 BSC
0.635 BSC
H
0.395
-
0.420
10.03
-
10.67
L
0.020
-
0.040
0.508
-
1.016
a
0º
-
0º
-
8º
8º
Ordering Information
Part Number
Package Type
Production Flow
C9630CY
48 PIN SSOP
Commercial, 0° to 70°C
Marking: Example:
Cypress
C9630CY
Date Code, Lot #
C9630CY
Package
Y = SSOP
Revision
Device Number
Notice
Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design,
performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in
life supporting and medical applications where the failure or malfunction of the product could cause failure of the life
supporting and medical systems. Products are not authorized for use in such applications unless a written approval is
requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of
its products in the life supporting and medical applications.
Cypress Semiconductor Corporation
3901 North First St.
San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
Document #: 38-07035 Rev. *A
12/18/2002
Page 17 of 18
APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Document Title: C9630 PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications
Document Number: 38-07035
Rev. ECN
No.
**
106963
*A
122728
Issue
Date
06/11/01
12/18/02
Cypress Semiconductor Corporation
3901 North First St.
San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
Orig. of
Change
IKA
RBI
Description of Change
Convert from IMI to Cypress
Added power-up requirements to maximum ratings
information.
Document #: 38-07035 Rev. *A
12/18/2002
Page 18 of 18