ETC C9706AY

C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Product Features
•
•
•
•
•
•
•
•
•
•
•
1 differential pair and 1 single ended open drain
CPU clocks
6 PCI clocks
2 REF (3.3V) clocks at 14.318 MHz
1 48 MHz (3.3V), and one 24/48 MHz clock
Power Management through PWR_DN#
13 SDRAM clocks for 3 DIMMs
Cypress Spread Spectrum for best EMI reduction
8 Spread Spectrum settings each frequency
48 Pin SSOP Package
SMBus clock control with readback capability
Fine resolution frequency programming via Dial-a®
Frequency Function
Product Description
The C9706 is a main clock synthesizer chip for VIA
VT8371 (KX133) chipset and AMD Athlon (K7) CPU
based systems. This device provides all clocks required
with spread spectrum for EMI reduction.
It also
includes a comprehensive SMBus control interface to
permit individual clock enable, frequency, and spread
controls via system software.
VDD
REF0/(CPU_STP#)
REF1/S0
OSC
PWR_DN#
CPU-OD
S0
PLL1
Stop
Clock
control
CPU
CPU#
VDD
PCI0/MODE
S3 S2 S1
PCI1/S1
PCI2
SDATA
SCLK
PCI3
I2C
Logic
PCI4
PCI5
VDD
PLL2
SDRAMIN
S3
S2
S1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
S0
CPU
PCI
Spread
Spectrum
+/- .5%
+/- .5%
+/- .5%
+/- .5%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Table 1
133.3
75
100.2
66.8
79
110
115
120
133.3
83.3
100.2
66.8
124
129
138
143
33.3
37.5
33.3
33.4
39.5
36.7
38.3
30
33.3
27.7
33.3
33.4
31.0
32.3
34.5
35.8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1/S0
VSS
CPU-OD
VSS
CPU#
CPU
VDD
PWR_DN#
SDRAM12
VSS
SDRAM0
SDRAM1
VDDS
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDDS
SDRAM6
SDRAM7
VDD
48MHz/S2
24_48MHz/S3
Pin Configuration
Block Diagram
XIN
XOUT
Frequency Table
48M/S2
/2
VDD
REF0/(CPU_STP#)
VSS
XIN
XOUT
VDD
PCI0/MODE
PCI1/S1
VSS
PCI2
PCI3
PCI4
PCI5
VDD
SDRAMIN
VSS
SDRAM11
SDRAM10
VDDS
SDRAM9
SDRAM8
VSS
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
24_48M/S3
VDDS
SDRAM(0:12)
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
Page 1 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Pin Description
PIN No.
Pin Name
TYPE
Description
I/O
This is a bi-directional pin with an internal pull-up. The direction of this pin is determined by
the state of signal MODE (pin 7).
If Mode = 0, this pin is a CPU_STP# input pin. When CPU_STP# is asserted low, CPU and
CPU-OD are forced LOW and CPU# is in Tristate.
If Mode = 1, this pin is REF0, a buffer output of the signal applied at Xin.
This is the input pin to the crystal oscillator, which is an internal amplifier. It is typically
connected to a parallel resonant crystal. It may also be driven from an alternative clock
source.
This is the output pin of the crystal oscillator, which is an internal amplifier. It is typically
connected to a parallel resonant crystal. If Xin is driven from an alternative clock source, then
this pin should be unconnected.
This is a power on bi-directional strapping pin with an internal pull-up (see app note, page 4).
During power up, this pin is an input “Mode” for setting the direction of Pin 2. When the power
reaches the rail, this pin becomes a PCI0 clock output.
This is a power on bi-directional strapping pin with an internal pull-up (see app note, page 4).
During power up, this pin is an input “S1” for frequency selection, see table 1, p.1. When the
power reaches the rail, this pin becomes a PCI1 clock output.
PCI clock outputs. Synchronous to CPU clocks.
LVTTL Input pin to the SDRAM(0:12) distribution buffers.
SDRAM Buffered Outputs. They are buffered outputs of the signal applied at SDRAMIN.
When PWR_DN# is low. These signals are forced low regardless of the signal at SDRAMIN.
2
REF0 /
CPU_STP#
4
XIN
I
5
XOUT
O
7
PCI0 /
MODE
I/O
8
PCI1 /
S1
I/O
10,11,12,13
15
40,38,37,35,
34,32,31,29,
28,21,20,18,17
23
PCI(2:5)
SDRAMIN
SDRAM (0:12)
OUT
IN
OUT
SDATA
I/O
24
25
SCLK
24_48MHz / S3
I
I/O
26
48MHz /
S2
I/O
41
PWR_DN#
IN
43, 44
CPU, CPU#
O
46
CPU-OD
O
48
REF1 / S0
IN/OUT
1,6,14,27, 42
19, 36, 30
3, 9, 16, 22, 33, 39,
45, 47
VDD
VDDS
VSS
PWR
PWR
GND
Serial data input pin. Conforms to the SMBus specification of a Slave Receiver/Transmitter
device. This pin is an input when receiving data. It is an open drain output when
acknowledging or transmitting. See SMBus function description, p.8.
Serial clock input pin. Conforms to the SMBus 100KHz Specification
This is a power on bi-directional strapping pin with an internal pull-down (see app note, page
4). During power up, this pin is an input “S3” for frequency selection, see table 1, p.1. When
the power reaches the rail, this pin becomes a SIO clock output programmed to 24MHz or
48MHz via byte3, bit6 in the SMBus table. It defaults to 24MHz.
This is a power on bi-directional strapping pin with an internal pull-up (see app note, page 4).
During power up, this pin is an input “S2” for frequency selection, see table 1, p.1. When the
power reaches the rail, this pin becomes a 48MHz, USB clock output.
LVTTL input with an internal pull-up. When this pin is asserted low, the device is in power
down condition, all clocks are stopped in a Low state except CPU# will be in tristate.
Open Drain Differential CPU outputs. They require external pull-up to 1.5V. See table 1 page
1 for frequency selection.
Open Drain single ended CPU clock. It requires an external pull-up to 3.3V. It is in phase with
CPU clock (pin 43).
This is a power on bi-directional strapping pin with an internal pull-up (see app note, page 4).
During power up, this pin is an input “S0” for frequency selection, see table 1, p.1. When the
power reaches the rail, this pin becomes a REF1, a buffered clock output of the signal applied
at Xin.
Common 3.3V Power Supply.
Power supply for SDRAM. Nominally 3.3V
Ground
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
Page 2 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Power on Bi-Directional Pins
Power Up Condition:
Pins 7, 8, 25, 26, and 48, are Power up bi-directional pins and are used for different features in this device (see Pin
description, Page 2). During power-up, these pins are in input mode (see Fig 2, below), therefore, they are considered
input select pins internal to the IC. After a settling time, the Selection data is latch into internal control registers and these
pins become toggling clock outputs.
VDD Rail
Power Supply
Ramp
S0 / REF1
S1 / PCI1
S2 / 48 MHZ
MODE/PCI0
S3/24_48 MHz
Hi-Z Inputs
-
Toggle Outputs
Select Data is latched into register then pin becomes clock output signal.
Fig. 2
Vdd
Strapping Resistor Options for pins with internal
Pull-ups:
The power up bidirectional pins have a large value pullup each (250KΩ), therefore, a selection “1” is the
default. If the system uses a slow power supply (over
3mS settling time), then it is recommended to use an
external Pullup (Rup) in order to insure a high selection.
In this case, the designer may choose one of two
configurations, see Fig. 3A and Fig. 3B.
Rd
Load
Bidirectional
JP1
JUMPER
Fig.3A
Fig. 3A represents an additional pull up resistor 50KΩ
connected from the pin to the power line, which allows a
faster pull to a high level.
If a selection “0” is desired, then a jumper is placed on
JP1 to a 5KΩ resistor as implemented as shown in
Fig.4A. Please note the selection resistors (Rup, and
Rdn) are placed before the Damping resistor (Rd)
close to the pin.
Fig. 3B represent a single resistor 10KΩ connected to a
3 way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads 1
and 2.
Rup
50K
IMI C9706
Rdn
5K
Vdd
IMI C9706
JP2
3 Way Jumper
Rsel
10K
Rd
Load
Bidirectional
Fig.3B
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
Page 3 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Strapping Resistor Options for pins with internal
Pull-downs:
The power up bi-directional pins have a large value pull-down (50KΩ+/−20KΩ), therefore, a selection “0” is the default. If
the system uses a slow power supply (over 10mS settling time), then it is recommended to use an external Pull-down
(Rdn) in order to insure a low selection. In this case, the designer may choose one of two configurations, see Fig.6A
and B.
Fig. 4A represents an additional pull down resistor 5KΩ connected from the pin to the power line, which allows a faster
down to a high level.
If a selection “1” is desired, then a jumper is placed on JP1 to a 1 KΩ resistor as shown in Fig.5A. Please note the
selection resistors (Rup and Rdn) are placed before the Damping resistor (Rd) close to the pin.
Fig. 4B represent a single resistor 5KΩ connected to a 3-way jumper, JP2. When a “1” selection is desired, a jumper is
placed between leads1 and 3. When a “0” selection is desired, a jumper is placed between leads 1 and 2.
V dd
R up
1K
IM I C 9 7 0 6
Rd
Load
B id ire c tio n a l
JP 1
JU M P E R
F ig . 4 A
R dn
5K
V dd
JP 2
3 W ay Jum per
3
IM I C 9 7 0 6
2
1
R sel
5K
Rd
Load
B id ire c tio n a l
F ig . 4 B
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
Page 4 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Power Management Functions
Power Management on this device is controlled by CPU_STP# (pin2) and PWR_DN# (pin41).
When CPU_STP# is forced low, all CPU signals are synchronously (no glitch) disabled to a low state and CPU# signals
are in tristate. The CPU_STP# signal does not directly gate the CPU clocks, the CPU clocks will toggle one to three
complete cycles before stopping on a falling edge. When CPU_STP# is released to high, the CPU clocks are
synchronously re-enabled. The clocks will wait the equivalent of one to three cycles after CPU_STP# is asserted high
then will start toggling on the rising edge.
When PWR_DN# is forced low, CPU-OD, CPU, PCI(0:5), SDRAM(0:12), 48MHz, 48_24MHz, and REF(0:1) signals are
synchronously forced low (CPU# is placed in tristate), all internal circuitry (including the crystal buffer) is shutdown and
the device is placed in low power (or in power down) mode. After PWR_DN# is forced low, all power supplies (3.3V and
2.5V) may be removed. All power supplies must be re-applied 200mS before releasing PWR_DN# (to high),
consequently, the device must then be allowed 1mS before the clock outputs settle to their preset frequencies. (see
Fig.4, and table 2 below)
Power Management Timing
PCI(0:5)
PWR_DWN#
CPU#
Tristate
CPU
CPU-OD
Fig. 5
All functionality is referenced to the edge of PWR_DN#. If the tss timing is met, with respect to the next occurring PCI_F
low to high transition, then all clocks that are controlled by CPU_STP# are guaranteed to stay low (stopped) or to rise
(run) at the next rising edge of PCI_F. See the AC parameters for tss time. CPU# clocks are stopped in a high state.
Power Management Function Table
CPU_STP#
X
0
1
PWR_DN#
0
1
1
CPU-OD
LOW
LOW
RUN
CPU
LOW
LOW
RUN
CPU#
Hi-Z
Hi-Z
RUN
REF(0:1)
PCI(0:5)
LOW
LOW
RUN
RUN
RUN
RUN
Table 2
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
48M, 48_24M
LOW
RUN
RUN
SDRAM (0:12)
LOW
RUN
RUN
Document#: 38-07041 Rev. **
XTAL, PLLS
OFF
RUN
RUN
05/02/2001
Page 5 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Power Down Timing
Power down (asserting the PWR_DN# pin) is an asynchronous event in the device. When PWR_DN is brought low, the
device internally removes power from all control logic. All outputs are driven to a logic low level. The exception is the
CPU# pins which are released to a high (floating) state. It is the designer’s responsibility to ensure all system timing and
sequencing needs are met before applying and releasing this pin. It is intended to be used as a system power savings
feature and will put the device into its lowest power consumption mode while still retaining the minimum control logic
functionally needed to produce an orderly startup when PWR_DN# is released to a high state.
Spectrum Spread Clocking
Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic
Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the
center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore
distributing an even amount of energy over a wider spectrum. In this device, Spread Spectrum is enabled by setting
SMBus byte0, bit3 = 1. The default of the device at power up keeps the Spread Spectrum disabled, it is therefore,
important to have SMBus accessibility to turn-on the Spread Spectrum function. See Table 3 for Spread selection.
Center Spread
Down Spread
Fig.6A
Fig. 6B
SBW2
0
0
0
0
1
1
1
1
SBW1
0
0
1
1
0
0
1
1
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
SBW0
0
1
0
1
0
1
0
1
Table 3
Spread
± 0.25%
± 0.12%
± 0.37%
± 0.50%
- 0.50%
- 0.25%
- 0.75%
+ 0.25%, - 0.75%
Document#: 38-07041 Rev. **
05/02/2001
Page 6 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
2-Wire SMBus Control Interface
The 2-wire control interface implements a read/write slave only interface according to SMBus specification. (see fig6,
page 7) . The device can be read back by using standard SMBus command bytes. Sub-addressing is not supported,
thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows
each clock output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported.
During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is
high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an “acknowledge” is generated. The first byte of a
transfer cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 1 in read mode. R/W# = 0 in write
mode.
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the “acknowledge” (low) signal
on the SDATA wire following reception of each byte. If the device should be read then an address D3 must be sent.
Data is transferred MSB first at a max rate of 100kbits/S.
The device will not respond to any other control interface conditions, and previously set control registers are retained.
Transmit
Receive
1
1
0
1
0
0
1
ACK
0
ACK
ACK
BYTE 0
BYTE N
(Valid)
(Valid)
(Don't Care)
8
8
SCLK
START CONDITION
1
0
1
0
0
1
ACK
(Valid)
START CONDITION
BYTE1
ACK
BYTE N
ACK
(Valid)
(Valid)
8
8
ACK
(Valid)
LSB
8
SCLK
8
STOP CONDITION
BYTE 0
ACK BYTE COUNT
1
SDATA
MSB
8
Fig.7a (WRITE)
Transmit
1
ACK
LSB
MSB
Receiv
BYTE COUNT
COMMAND BYTE
(Don't Care)
SDATA
ACK
8
STOP CONDITION
Fig.7b (READ)
Figure 7
SMBus Communications Waveforms
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
Page 7 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Serial Control Registers
NOTE: The Pin # column lists the affected pin number where applicable. The @Pup column gives the state of the
control register at power up. Bytes are set to the values shown only on true power up.
Following the acknowledge of the Address Byte , two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1,
Byte2,…) will be valid and acknowledged.
Byte 0: Frequency Control Register (1 = Enable, 0 = Low)
Bit
@Pup
Pin#
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
-
Pin Description
Spread Spectrum extension (1= on, 0 = off) see table 4, pg. 10
S2
S1
S0
1 = enable byte 0, bits 6, 5, 4, 2, 1 for frequency selection table 4
S4
S3
See Table 3 below
Byte 1: CPU / SDRAM Clock Register (1=Enable, 0=Low)
Bit
@Pup
Pin#
Pin Description
7
6
5
4
3
2
1
0
0
0
0
0
1
0
1
1
40
43,44
46
SBW2 (See SST Page 6, Table 3)
SBW1 (See SST Page 6, Table 3)
SBW0 (See SST Page 6, Table 3)
Reserved
SDRAM12
Reserved
CPU,CPU# (0 = disabled, CPU in low and CPU# in Hi-Z mode)
CPU-OD
Byte0, Bit 7
0
0
1
1
Byte0, Bit 0 Modes
0
Normal operation
1
Tri-state
0
Spread Spectrum On
1
Test mode (Spread Spectrum On)
Table 3
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
Page 8 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Byte 2: PCI Control Register (1=Enable,
0=Stopped)
Bit
@Pup
Pin#
7
6
5
4
3
2
1
0
0
1
0
1
1
1
1
1
7
13
12
11
10
8
Pin Description
Reserved
PCI0
Reserved
PCI5
PCI4
PCI3
PCI2
PCI1
Byte 5: Register
Bit
@Pup
Pin#
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
46
2
Pin Description
S3 Readback
S2 Readback
S0 Readback
MODE Readback
S1 Readback
Reserved
REF1
REF0
Byte 6: Reserved Register
Byte 3: SDRAM Control Register (1=Enable,
0=Stopped)
Bit
@Pup
Pin#
Pin
Description
7
6
0
0
25
5
4
3
2
1
0
1
1
0
1
1
1
26
25
17,18,20,21
28,29,31,32
34,35,37,38
Reserved
0 = output 24MHz.
1 = output 48MHz.
48MHz
24_48MHZ
Reserved
SDRAM(8:11)
SDRAM(4:7)
SDRAM(0:3)
®
Byte 4: Dial-a-Frequency Register
Bit
@Pup
Pin#
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
-
Pin Description
N7, MSB
N6
N5
N4
N3
N2
N1,
N0, LSB
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Bit
@Pup
Pin#
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
-
Pin Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
®
Byte 7: Dial-a-Frequency Register
Bit
@Pup
Pin#
Pin Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
-
R6, MSB
R5
R4
R3
R2
R1
R0, LSB
Enable SMBus N&R
Document#: 38-07041 Rev. **
05/02/2001
Page 9 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset
Systems
Approved Product
Frequency Selection Table
Bit2
S4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Input Conditions
Data Byte 0, Bit 3 = 1
Bit 1
Bit 6
Bit 5
S3
S2
S1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Bit 4
S0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Output
Frequency
CPU
PCI
133.3
33.3
75
37.5
100.2
33.3
66.8
33.4
79
39.5
110
36.7
115
38.3
120
30
133.3
33.3
83.3
27.7
100.2
33.3
66.8
33.4
124
31.0
129
32.3
138
34.5
143
35.8
85
28.3
87.5
29.2
90
30
92.5
30.8
95
31.7
147
36.8
152
30.4
154
30.8
157
31.4
159
31.8
162
32.4
166
33.2
171
34.2
180
36
190
38
200
40
Table 4.
Spread%
Byte0, Bit7 = 0
Byte0, Bit7 = 1
+/-0.5
+/-0.5
+/-0.5
+/-0.5
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
See table 3, Page 6
®
Dial-a-Frequency Feature
SMBus Dial-a-frequency feature is available in this device via byte7, and byte4.
These bytes allow the user to enter the N and R values that will allow them to program any CPU frequency
desired following the formula:
Fcpu =
P× N
R
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
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Document#: 38-07041 Rev. **
05/02/2001
Page 10 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
®
Dial-a-Frequency Feature (Cont.)
Where N and R values are programmed in binary into byte 4 for N and byte 7 for R. See table below for min
and max allowed values.
R
42
43
44
45
46
47
48
49
50
51
Min N
44
45
46
47
48
49
50
51
52
53
Max N
87
90
92
94
96
98
100
102
104
107
P is a large value PLL constant that depends on the frequency selection achieved through the hardware
selectors (S3, S2, S1, S0) or through the software selectors (byte0, bits 6,5,4,2,1). P value may be
determined from the following table:
S(4:0)
0100X, 00XXX
01010, 100XX,
10111,11000,11111
01011, 011XX, 10101, 10110,
11001, 1101X, 11101, 11110
10100, 11100
P
96016000
64010666.67
48008000
38406400
6
Therefore, if a 145MHz (use 145x10 ) value is desired, then we should apply 145 into equation 1, and start
by choosing R to be 47 (assume the last frequency selection has the value P = 96016000):
6
145X10 = 96016000 X N
47
=> N = 70.97775371
Since this N number must be entered in Binary, it can only be an integer, so it must be rounded up or down.
Here we can rounded it up to 71, which will give us an exact CPU frequency of:
Fcpu = 96016000 X N = 145.045 MHz (accuracy + 310 ppm)
47
If the above frequency is not accurate enough, then you must choose another R value and start from the
beginning. For example choose R = 49 and this will yield an N = 73.99808365, which is rounded to 74. If the
74 is applied in the formula 1, then Fcpu = 145.0038 MHz(accuracy + 26 ppm).
Other R values within the above limits may also be evaluated.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
Page 11 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Maximum Ratings
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
-65ºC to + 150ºC
0ºC to +85ºC
Maximum ESD protection
Maximum Power Supply:
2000V
5.5V
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Note 2
Input Low Voltage
VIL2
-
-
1.0
Vdc
Input High Voltage
VIH2
2.2
-
-
Vdc
Input Low Current (@VIL = VSS)
IIL
-66
Input High Current (@VIL =VDD)
IIH
Input Low Current (@VIL = VSS)
IIL
Input High Current (@VIL =VDD)
IIH
66
-5
µA
5
µA
-5
µA
5
µA
Tri-State leakage Current
Ioz
-
-
10
µA
Dynamic Supply Current
Idd3.3V
-
-
260
mA
Cin
-
-
5
pF
Cout
-
-
6
pF
Input pin capacitance
Output pin capacitance
Pin inductance
Lpin
-
-
7
nH
Crystal pin capacitance
Cxtal
30
36
34
pF
Crystal DC Bias Voltage
VBIAS
0.3Vdd
Vdd/2
0.7Vdd
V
Crystal Startup time
Txs
-
-
40
µS
For internal Pull up resistors,
Notes 1,3
For internal Pull down resistors,
Notes 1,3
S(3:0) = 0111, Note 4
Measured from Pin to VSS. Note 5
From Stable 3.3V power supply.
VDD = 3.3V ±5%, TA = 0º to +70ºC
Note1:
Note2:
Note3:
Note4:
Note5:
Pull-down applicable to pin 25 (S3). Pull-up applicable to pins 2, 7, 8, 26, 41, 48.
Applicable to Sdata, and Sclk.
Although internal pull-down/up resistors have a typical value of 250K, this value may vary between 200K and 500K.
All outputs loaded as per table 5 below.
Although the device will reliably interface with crystals of a 15pF – 20pF CL range, it is optimized to interface with a typical CL = 16pF
crystal specifications.
Clock Name
CPU, REF
PCI, SDRAM
24MHz, 48MHz
Max Load (in pF)
20
30
15
Table 5
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
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Document#: 38-07041 Rev. **
05/02/2001
Page 12 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
AC Parameters
Symbol
TPeriod
Tf
TSKEW0
TCCJ
TPeriod
THIGH
TLOW
Tr / Tf
TDelay
TSKEW1
TCCJ
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW2
TCCJ
TPeriod
Tr / Tf
TCCJ
TPeriod
Tr / Tf
TCCJ
TPeriod
Tr / Tf
TCCJ
tpZL, tpZH
tpLZ, tpHZ
tstable
Parameter
CPU, CPU#, CPU-OD period
CPU, CPU#, CPU-OD fall times
CPU to CPU-OD Skew time
CPU Cycle to Cycle Jitter
SDRAM[0:12] period
SDRAM[0:12] high time
SDRAM[0:12] low time
SDRAM[0:12] rise and fall times
SDRAMIN to Any SDRAM[0:12]
Any SDRAM to Any SDRAM
SDRAM[0:12] Cycle to Cycle Jitter
PCI(0:5) period
PCI(0:5) period
PCI(0:5) low time
PCI(0:5) rise and fall times
(Any PCI clock) to (Any PCI clock)
PCI(0:5) Cycle to Cycle Jitter
48MHz period ( conforms to
+167ppm max)
48MHz rise and fall times
48MHz Cycle to Cycle Jitter
24MHz period
24MHz rise and fall times
24 MHz Cycle to Cycle Jitter
REF(0:1) period
REF(0:1) rise and fall times
REF(0:1) Cycle to Cycle Jitter
Output enable delay (all outputs)
Output disable delay (all outputs)
All clock Stabilization from power-up
133 MHz Host
Min
Max
7.5
8.0
1
175
250
7.5
8.0
1.87
1.67
0.4
1.6
3.5
250
250
29.93
12.0
12.0
0.5
2.0
500
500
20.8299 20.8333
100 MHz Host
Min
Max
9.98
10.5
1
175
250
10.0
10.5
3.0
2.8
0.4
1.6
3.5
250
250
29.94
12.0
12.0
0.5
2.0
500
500
20.8299 20.8333
1.0
41.6598
1.0
69.8413
1.0
1.0
1.0
1.0
41.6598
1.0
69.8413
1.0
1.0
1.0
4.0
500
41.6666
4.0
500
71.0
4.0
1000
10.0
10.0
3
4.0
500
41.6666
4.0
500
71.0
4.0
1000
10.0
10.0
3
Units
nS
V/nS
pS
pS
nS
nS
nS
nS
nS
pS
pS
nS
nS
nS
nS
pS
pS
nS
Notes
5, 6, 8
6
6, 8, 9
6, 8, 9
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
6, 8, 9
6, 8, 9
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
6, 8, 9
5, 6, 8
nS
pS
nS
nS
pS
nS
nS
pS
nS
nS
mS
6, 7
6, 8, 9
5, 6, 8
6, 7
6, 8, 9
5, 6, 8
6, 7
6, 8
13
13
12
Note 5:
Note 6:
Note 7:
Note 8:
This parameter is measured as an average over 1uS duration, with a crystal center frequency of 14.31818MHz
All outputs loaded as per table 5.
Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V. (see fig.7.)
Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals (fig.7) and as in fig.9 for differential
CPU clocks
Note 9: This measurement is applicable with Spread ON or Spread OFF.
Note 10:Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals (see fig.7)
Note 11:Probes are placed on the pins, and measurements are acquired at 0.4V.
Note 12:The time specified is measured from when all VDD’s reach their respective supply rail (3.3V) till the frequency output is
stable and operating within the specifications
Note 13:Measured from when Byte0, bit0 is toggled.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
Page 13 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Test and Measurement Setup for Non Differential Clocks
3 .3 V s ig n a ls
tD C
-
-
3 .3 V
O u tp u t u n d e r T e s t
P ro b e
2 .4 V
Load C ap
1 .5 V
0 .4 V
0V
Tr
Tf
Fig.8
Test and Measurement Setup for CPU Differential Clocks
VDDCPU
VTR
Vdif
VCP
Vx
VSS
Fig. 9
VDDCPU(1.5V)
3.3V
60.4 Ohm
CPU
47 Ohm
52 Ohm 5"
500 Ohm
Measurement Point
52 Ohm 3"
680 pF
20 pF
500 Ohm
301 Ohm
47 Ohm
CPU#
VDDCPU(1.5V)
52 Ohm 3"
500 Ohm
52 Ohm 5"
680 pF
60.4 Ohm
500 Ohm
Measurement Point
20 pF
3.3V
Fig. 10
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
Page 14 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Output Buffer Characteristics
CPU, CPU#, CPU-OD
CPU = 133M
CPU = 100M
Characteristic
Output Low Current
Symbol
Min
Typ
IOL
18
23
Max
Min
Typ
Max
Units
Conditions
VDL = 0.3V
Output Rise Edge Rate
tr
1.0
1.0
V/ns
Output Fall Edge Rate
tf
1.0
1.0
V/ns
Duty Cycle
tD
Jitter, Cycle to Cycle
tJC
45
55
45
Output Skew
tSK
TBD
TBD
AC Output Impedance
ZO
50
50
250
55
%
250
ps
Measured at 50% point
Measured on rising edge
at 750mV
Ω
VO = VX
PCI(0:5)
Characteristic
Symbol
Min
Typ
Pull-Up Current
IOH1
-33
-58
-194
mA
Vout =VDD - 1.0 V
Pull-Up Current
IOH2
-30
-54
-184
mA
Vout = 1. 5 V
Pull-Down Current
IOL1
9.4
18
38
mA
Vout = 0.4 V
Pull-Down Current
IOL2
28
55
148
mA
Vout = 1.5 V
Dynamic Output Impedance
Z0
24MHz, 48MHz, and REF(0:1)
Characteristic
Symbol
12
55
Ω
Max
Units
Min
Typ
Max
Units
Conditions
Conditions
Pull-Up Current
IOH1
-29
-46
-99
mA
Vout =VDD - 1.0 V
Pull-Up Current
IOH2
-27
-43
-92
mA
Vout = 1. 5 V
Pull-Down Current
IOL1
9
13
27
mA
Vout = 0.4 V
Pull-Down Current
IOL2
26
39
79
mA
Vout = 1.5 V
Z0
20
60
Ω
Max
Units
Dynamic Output Impedance
SDRAM(0:12)
Characteristic
Symbol
Min
Pull-Up Current
IOH1
-72
-116
-198
mA
Vout =VDD - 1. 0 V
Pull-Up Current
IOH2
-68
-110
-188
mA
Vout = 1. 4 V
Pull-Down Current
IOL1
23
34
53
mA
Vout = 0.4 V
Pull-Down Current
IOL1
64
98
159
mA
Vout = 1.5 V
Z0
10
24
Ω
Dynamic Output Impedance
Typ
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Conditions
Document#: 38-07041 Rev. **
05/02/2001
Page 15 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Suggested Oscillator Crystal Parameters
Characteristic
Symbol
Min
Typ
Max
Units
Frequency
Fo
12.00
14.31818
16.00
MHz
Tolerance
TC
-
-
+/-100
PPM
Note 1
TS
-
-
+/- 100
PPM
Stability (TA -10 to +60C) Note 1
TA
-
-
5
PPM
Ageing (first year @ 25C) Note 1
-
-
-
-
Load Capacitance
CXTAL
-
20
-
pF
Effective Series
Resistance (ESR)
RESR
-
40
-
Ohms
Operating Mode
Conditions
Parallel Resonant, Note 1
The crystal’s rated load. Note 1
Note 2
Note1:
For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen
crystal meets or exceeds these specifications
Note 2: Larger values may cause this device to exibit oscillator startup problems
To obtain the maximum accuracy, the total circuit loading capacitance should be equal to CXTAL. This loading capacitance is the
effective capacitance across the crystal pins and includes the clock generating device pin capacitance (CFTG), any circuit traces
(CPCB), and any onboard discrete load capacitors (CDISC).
The following formula and schematic may be used to understand and calculate either the loading specification of a crystal for a
design or the additional discrete load capacitance that must be used to provide the correct load to a known load rated crystal.
CL = (CXINPCB + CXINFTG + CXINDISC) X (CXOUTPCB + CXOUTFTG + CXOUTDISC)
(CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB + CXOUTFTG + COUTDISC)
Where:
CXTAL
CXOUTFTG
CXOUTFTG
CXINPCB
CXOUTPCB
CXINDISC
CXOUTDISC
=
=
=
=
=
=
=
the load rating of the crystal
the clock generators XIN pin effective device internal capacitance to ground
the clock generators XOUT pin effective device internal capacitance to ground
the effective capacitance to ground of the crystal to device PCB trace
the effective capacitance to ground of the crystal to device PCB trace
any discrete capacitance that is placed between the XIN pin and ground
any discrete capacitance that is placed between the XOUT pin and ground
CXINPCB
CXINDISC
CXOUTPCB
CXOUTDISC
XIN
CXINFTG
XOUT
CXOUTFTG
Clock Generator
As an example, and using this formula for this datasheet’s device, a design that has no discrete loading capacitors (CDISC) and each
of the crystal to device PCB traces has a capacitance (CPCB) to ground of 4pF (typical value) would calculate as:
CL = (4pF + 36pF + 0pF) X (4pF + 36pF + 0pF)
(4pF + 36pF + 0pF) + (4pF + 36pF + 0pF)
= 40 X 40
40 + 40
= 1600
80
= 20pF
Therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you
should specify a parallel cut crystal that is designed to work into a load of 20pF.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
Page 16 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Package Drawing and Dimensions
48 Pin SSOP Outline Dimensions
INCHES
SYMBOL
C
L
H
E
D
a
A2
A
e
NOM
MAX
MIN
NOM
MAX
A
0.095
0.102
0.110
2.41
2.59
2.79
A1
0.008
0.012
0.016
0.203
0.305
0.406
A2
0.088
-
0.092
2.24
-
2.34
B
0.008
-
0.0135
0.203
-
0.343
C
0.005
-
0.010
0.127
-
0.254
D
0.620
0.625
0.630
15.75
15.88
16.00
E
0.291
0.295
0.299
7.39
7.49
7.60
e
A1
B
MIN
MILLIMETERS
0.025 BSC
0.635 BSC
H
0.395
-
0.420
10.03
-
10.67
L
0.020
-
0.040
0.508
-
1.016
a
0º
-
0º
-
8º
8º
Ordering Information
Part Number
Package Type
C9706A
48 Pin SSOP
Marking: Example:
Production Flow
Commercial, 0ºC to +70ºC
Cypress
C9706A
Date Code, Lot #
C9706AY
Package
Y = SSOP
Revision
Device Number
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
Page 17 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Notice
Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design,
performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in
life supporting and medical applications where the failure or malfunction of the product could cause failure of the life
supporting and medical systems. Products are not authorized for use in such applications unless a written approval is
requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of
its products in the life supporting and medical applications.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
Page 18 of 19
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Document Title:C9706 Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Document Number: 38-07041
REV.
ECN NO.
Issue Date
Orig. of Change
Description of Change
**
109131
08/29/01
NDP
Convert from IMI to Cypress
Cypress Semiconductor Corporation
525 Los Coches St.
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http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
Page 19 of 19