EDI8F81027C 1Mx8 CMOS SRAM MONOLITHIC FEATURES DESCRIPTION n 1 Mx8 bit CMOS Static RAM The EDI8F81027C is an 8Mb CMOS Static RAM based on two 512Kx8 Static RAMs mounted on a multi-layered epoxy laminate (FR4) substrate. Access Times 55 through 100ns Data Retention Function (EDI8F81027LP ) A low power version with data retention (EDI8F81027LP) is also available. TTL Compatible Inputs and Outputs Fully Static, No Clocks All inputs and outputs are TTL compatible and operate from a single 5V supply. n High Density Packaging Fully asynchronous, the EDI8F81027C requires no clocks or refreshing for operation. 32 Pin DIP, No. 352 n Single +5V (±10%) Supply Operation PIN CONFIGURATIONS AND BLOCK DIAGRAM July 2002 Rev. 3A ECO #15405 PIN NAMES 1 AØ-A19 Address Inputs E Chip Enable W Write Enable DQØ-DQ7 Common Data Input/Output VCC Power (+5V±10%) VSS Ground NC No Connection White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F81027C A BSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Industrial Storage Temperature Power Dissipation Output Current RECOMMENDED DC OPERATING CONDITIONS -0.5V to 7.0V Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage 0°C to +70°C -40°C to +85°C -55°C to +125°C 1 Watt 20 mA Sym VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 --- Max 5.5 0 6.0 0.8 Units V V V V AC TEST CONDITIONS *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VSS to 3.0V 5ns 1.5V 1TTL, CL =100pF (note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF) DC ELECTRICAL CHARACTERISTICS Parameter Operating Power Supply Current Symbol ICC1 Standby (TTL) Power Supply Current ICC2 Full Standby Power Supply Current (CMOS) ICC3 Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage ILI ILO VOH VOL Conditions W, E = VIL, II/O = 0mA, Min Cycle E ³ VIH, VIN £ VIL VIN ³ VIH E ³ VCC-0.2V VIN ³ VCC-0.2V or VIN £ 0.2V VIN = 0V to VCC V I/O = 0V to VCC IOH = -1.0mA IOL = 2.1mA C LP Min -- Typ* 85 Max 140 Units mA -- 25 55 mA ---10 -10 2.4 -- 1.5 190 ----- 2 300 10 10 -0.4 mA µA µA µA V V *Typical: TA = 25°C, VCC = 5.0V CAPACITANCE TRUTH TABLE G X H L X E H L L L W X H H L Mode Standby Output Deselect Read Write (f=1.0MHz, VIN=VCC or VSS) Output High Z High Z DOUT DIN Power ICC2, ICC3 ICC1 ICC1 ICC1 Parameter Address Lines Data Lines Chip Enable Line Write and Output Enable Lines Sym CI CD/Q CC CW Max 30 43 10 32 Unit pF pF pF pF These parameters are sampled, not 100% tested. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 2 July 2002 Rev. 3A ECO #15405 EDI8F81027C AC CHARACTERISTICS READ CYCLE Symbol JEDEC Alt. 55ns Min Max 70ns Min Max Min Read Cycle Time TAVAV TRC 55 70 85 Address Access Time TAVQV TAA Chip Enable Access Time TELQV TACS Chip Enable to Output in Low Z (1) TELQX TCLZ Chip Disable to Output in High Z (1) TEHQZ TCHZ Output Hold from Address Change TAVQX Parameter 55 55 85 70 5 25 85 5 5 35 5 ns ns 100 ns ns 40 5 Units 100 5 30 5 100ns Min Max 100 70 5 TOH 85ns Max ns ns Note 1: Parameter guaranteed, but not tested. READ CYCLE 1 - W HIGH, E LOW TAVAV A ADDRESS 1 ADDRESS 2 TAVQV TAVQX Q DATA 1 DATA 2 READ CYCLE 2 - W HIGH TAVAV A TAVQV E TELQV TEHQZ TELQX G TGLQV TGHQZ TGLQX Q July 2002 Rev. 3A ECO #15405 3 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F81027C AC CHARACTERISTICS WRITE CYCLE Write Cycle Parameter Symbol JEDEC Alt. 55ns Min Max 70ns Min Max Min Write Cycle Time TAVAV TWC 55 70 85 100 ns Chip Enable to End of Write TELWH TELEH TCW TCW 50 50 65 65 70 70 80 80 ns ns Address Setup Time TAVWL TAVEL TAS TAS 0 0 0 0 0 0 0 0 ns ns Address Valid to End of Write TAVWH TAVEH TAW TAW 50 50 65 65 70 70 80 80 ns ns Write Pulse Width TWLWH TWLEH TWP TWP 45 45 65 65 70 70 80 80 ns ns Write Recovery Time TWHAX TEHAX TWR TWR 5 5 5 5 5 5 5 5 ns ns Data Hold Time TWHDX TEHDX TDH TDH 0 0 0 0 0 0 0 0 ns ns Write to Output in High Z (1) TWLQZ TWHZ 25 0 Data to Write Time TDVWH TDVEH TDW TDW 25 25 30 30 35 35 40 40 ns ns Output Active from End of Write (1) TWHQX TWLZ 5 5 5 5 ns 30 85ns Max 0 35 100ns Min Max 0 40 Units ns Note 1: Parameter guaranteed, but not tested. WRITE CYCLE 1 - W CONTROLLED TAVAV A E TELWH TWHAX TAVWH TWLWH W TAVWL TDVWH D DATA VALID TWHQX TWLQZ HIGH Z Q White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com TWHDX 4 July 2002 Rev. 3A ECO #15405 EDI8F81027C WRITE CYCLE 2 E CONTROLLED TAVAV A TAVEL TELEH E TAVEH TEHAX TWLEH W TDVEH D TEHDX DATA VALID HIGH Z Q DATA RETENTION CHARACTERISTICS (LP VERSION ONLY) Characteristic Sym Data Retention Voltage Test Conditions VDD VDD Data Retention Quiescent Current ICCDR Chip Disable to Data Retention Time Operation Recovery Time TCDR(1) TR (1) Min 2 E ³ VDD -0.2V VIN ³ VDD -0.2V or VIN £ 0.2V 2V 3V --0 TAVAV* Typ -- Max 85°C -- Unit 70°C -- --- 100 160 --- 130 210 --- µA µA ns ns V Note: Parameter guaranteed, but not tested * Read Cycle Time DATA RETENTION - E CONTROLLED 4.5V CC VDD TCDR E July 2002 Rev. 3A ECO #15405 4.5V TR E=VDD-0.2V 5 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F81027C ORDERING INFORMATION Standard Power EDI8F81027C55B6C EDI8F81027C70B6C EDI8F81027C85B6C EDI8F81027C100B6C Low Power with Data Retention EDI8F81027LP55B6C EDI8F81027LP70B6C EDI8F81027LP85B6C EDI8F81027LP100B6C Speed (ns) 55 70 85 100 Package No. 352 352 352 352 Note: To order an Industrial grade product substitute the letter C in the Suffix with the letter I, eg. EDI8F81027C70B6C becomes EDI8F81027C70B6I. PACKAGE DESCRIPTION PACKAGE NO. 352: 32 PIN DIP ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 6 July 2002 Rev. 3A ECO #15405