Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Datasheet Product Features ■ ■ ■ ■ High Performance Processor based on Intel® XScale™ Microarchitecture — 7-8 stage Intel® Superpipelined Technology — 32-Entry Instruction Memory Management Unit — 32-Entry Data Memory Management Unit — 32 KByte, 32-way Set Associative Instruction Cache — 32 KByte, 32-way Set Associative Data Cache — 2 KByte, 2-way Set Associative Mini-Data Cache — 128-Entry Branch Target Buffer — 8-Entry Write Buffer — 4-Entry Fill and Pend Buffers Intel® Dynamic Voltage Management — Core Voltage Range: 0.95 V to 1.55 V — Internal Clock Scalable by Software up to 733 MHz — Input Clock: 33-66 MHz ARM* Version 5TE Compliant Application-Code Compatible with Intel® StrongARM* SA-110 August 2002 ■ ■ ■ ■ ■ Power Management — Core Power is ~500mW at 600MHz — Core Voltage Operation Down to 0.95 V — Idle and Sleep Modes Intel® Media Processing Technology — Multiply-Accumulate Coprocessor High Performance External Bus — 64- or 32-Bit Data Interface — Optional ECC Protection — Frequency up to 100 MHz — Asynchronous to Processor Clock Performance Monitoring Unit — Two 32-Bit Event Counters — One 32-Bit Clock Counter — Monitors Occurrence and Duration Events Debug Unit — Accessible through JTAG Port — Hardware Breakpoints — 256-Entry Trace Buffer Reference Number: 273414-004 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. 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Copyright© Intel Corporation, 2002 AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 2 August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Contents 1.0 About this Document ..........................................................................................................5 2.0 Functional Overview........................................................................................................... 5 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 3.0 Package Information ........................................................................................................13 3.1 3.2 3.3 4.0 Package Introduction........................................................................................... 13 3.1.1 Functional Signal Definitions ..................................................................13 3.1.1.1 Signal Pin Descriptions ............................................................. 13 3.1.2 241 Lead PBGA Package ...................................................................... 17 Package Thermal Specifications .........................................................................22 Package Thermal Resistance ............................................................................. 22 Electrical Specifications.................................................................................................... 24 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 Datasheet Superpipeline ........................................................................................................ 7 Branch Target Buffer (BTB)................................................................................... 8 Instruction Memory Management Unit (IMMU) ..................................................... 8 Data Memory Management Unit (DMMU) .............................................................9 Instruction Cache (I-Cache) .................................................................................. 9 Data Cache (D-Cache)........................................................................................ 10 Mini-Data Cache.................................................................................................. 10 Fill Buffer (FB) and Pend Buffer (PB) ..................................................................11 Write Buffer (WB) ................................................................................................ 11 Multiply-Accumulate Coprocessor (CP0) ............................................................ 11 Clock and Power Management ........................................................................... 12 Performance Monitoring Unit (PMU) ................................................................... 12 Debug Unit .......................................................................................................... 12 Absolute Maximum Ratings................................................................................. 24 VCCA Pin Requirements ...................................................................................... 25 Targeted DC Specifications................................................................................. 26 Targeted AC Specifications................................................................................. 27 4.4.1 Clock Signal Timings ..............................................................................27 4.4.2 Bus Signal Timings................................................................................. 28 4.4.3 Boundary Scan Test Signal Timings ...................................................... 29 AC Timing Waveforms ........................................................................................ 30 Power Sequence .................................................................................................32 Reset Timing ....................................................................................................... 34 AC Test Conditions ............................................................................................. 34 Typical Power Dissipation ................................................................................... 35 August 2002 3 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Intel® 80200 Processor Block Diagram ................................................................. 6 241-Lead PBGA Package ................................................................................... 17 Case Temperature with No Air Flow ................................................................... 23 Case Temperature at Nominal Power Dissipation .............................................. 23 VCCA Lowpass Filter............................................................................................ 25 CLK Waveform .................................................................................................... 30 MCLK Waveform ................................................................................................. 30 TOV Output Delay Waveform .............................................................................. 31 Correct Power Sequence for VCC, VCCP ............................................................. 32 Another Correct Power Sequence for VCC, VCCP ............................................... 32 Incorrect Power Sequence for VCC, VCCP ........................................................... 32 Preferred Power Sequence for VCC, VCCa ....................................................... 33 Correct Power Sequence for VCC, VCCa........................................................... 33 Pins’ State at Reset............................................................................................. 34 AC Test Load ...................................................................................................... 34 Typical Pin Power Dissipation ............................................................................. 35 Typical Core Power Dissipation .......................................................................... 35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Related Documentation......................................................................................... 5 Pin Description Nomenclature............................................................................. 13 Power Pins .......................................................................................................... 14 Signal Pin Description ......................................................................................... 14 JTAG Pins ........................................................................................................... 16 241-Lead PBGA Pinout — Ballpad Number Order ............................................. 18 241-Lead PBGA Pinout — Signal Name Order .................................................. 20 Package Thermal Resistance — °C/Watt ........................................................... 22 Operating Conditions .......................................................................................... 24 Voltage Range Requirements for Intel® 80200 Processor Product Options ....... 24 DC Characteristics .............................................................................................. 26 ICC Characteristics .............................................................................................. 26 Input Clock Timings............................................................................................. 27 Output Timings .................................................................................................... 28 Input Timings....................................................................................................... 28 Boundary Scan Test Signal Timings ................................................................... 29 Tables 4 August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture About this Document 1.0 About this Document This is the Advance Information data sheet for the Intel® 80200 processor based on Intel® XScale™ microarchitecture (ARM* architecture compliant). This data sheet contains a functional overview, mechanical data (package signal locations and simulated thermal characteristics), targeted electrical specifications (simulated), and bus functional waveforms. Detailed functional descriptions other than parametric performance is published in the Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Developer’s Manual. Table 1. Related Documentation Document Title Intel ® Intel ® ™ Microarchitecture Developer’s Manual 273411 ® ™ Microarchitecture Specification Update 273415 80200 Processor based on Intel XScale 80200 Processor based on Intel XScale Intel® 80310 I/O Processor Chipset Design Guide 273354 ® 273410 ® 273425 ® 273416 Intel 80312 I/O Companion Chip Developer’s Manual Intel 80312 I/O Companion Chip Datasheet Intel 80312 I/O Companion Chip Specification Update 2.0 Document # ® Functional Overview The Intel® 80200 processor technology is compliant with the ARM* Version 5TE instruction set architecture (ISA). The Intel® 80200 processor is designed with Intel state-of-the-art 0.18 micron production semiconductor process technology. This process technology, along with the compactness of the ARM RISC ISA, enables the Intel® 80200 processor to operate over a wide speed/power range, producing industry-leading mW/MIPS performance. • 7-8 stage Superpipeline promotes high speed, efficient core performance • 128-entry Branch Target Buffer keeps pipeline filled with statistically correct branch choices • 32-entry Instruction Memory Management Unit for logical-to-physical address translation, access permissions, I-Cache attributes • 32-entry Data Memory Management Unit for logical-to-physical address translation, access permissions, D-Cache attributes • 32 KB Instruction Cache can hold entire programs, preventing core stalls caused by multicycle memory accesses • 32 KB Data Cache reduces core stalls caused by multicycle memory accesses • 2 KB Minidata Cache for frequently changing data streams avoids “thrashing” of the D-Cache • 4-entry Fill and Pend Buffers promote core efficiency by allowing “hit-under- miss” operation with Data Caches • Power Management Unit gives power savings via idle, and sleep modes • 8-entry Write Buffer allows the core to continue execution while data is written to memory • Multiply-Accumulate Coprocessor can do two simultaneous 16-bit SIMD multiplies with 40-bit accumulation for efficient, high quality audio Datasheet August 2002 5 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Functional Overview • Performance Monitoring Unit furnishes two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc. • JTAG Debug Unit uses Hardware Breakpoints and 256-entry Trace History Buffer (for flow change messages) to debug programs • Dynamic clocking allows optimized performance Figure 1. Intel® 80200 Processor Block Diagram Branch Target Cache FIQ# IRQ# BCU Registers FIQ# Interrupt Controller IRQ# Interrupt Request Instruction Execution Core Data Address MAC Performance Monitor Data System Management Instruction M Cache M 32 Kb U Data Cache M 32 Kb M Mini-Data U Cache: 2 Kb Bus Control Unit External Bus JTAG A8158-01 6 August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Functional Overview 2.1 Superpipeline The Superpipeline is composed of Integer, Multiply-Accumulate (MAC), and memory pipes. The Integer pipe has seven stages: • • • • • • • Branch Target Buffer (BTB)/Fetch 1 Fetch 2 Decode Register File/Shift ALU Execute State Execute Integer Writeback The Memory pipe has eight stages: • the first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute) . . . then finish with Memory stages: • Data Cache 1 • Data Cache 2 • Data Cache Writeback The MAC pipe has six to nine stages: • the first four stages of the Integer pipe (BTB/Fetch 1 through Register File/ Shift) . . . then finish with MAC stages: • • • • • MAC1 MAC2 MAC3 MAC4 Register Writeback The MAC pipe supports a data-dependent early terminate where stages MAC2, MAC3, and/or MAC4 are by-passed. Deep pipes promote high instruction execution rates only when a means exists to successfully predict the outcome of branch instructions. The Branch Target Buffer provides such a means. Datasheet August 2002 7 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Functional Overview 2.2 Branch Target Buffer (BTB) Each entry of the 128-entry BTB contains the address of a branch instruction, the target address associated with the branch instruction, and a previous history of the branch being taken or not taken. The history is recorded as one of four states: strongly taken, weakly taken, weakly not-taken, or strongly not-taken. The BTB can be enabled or disabled via coprocessor 15, register 1. When the address of the branch instruction hits in the BTB and its history is strongly or weakly taken, the instruction at the branch target address is fetched; when its history is strongly or weakly not-taken, the next sequential instruction is fetched. In either case the history is updated. Data associated with a branch instruction enters the BTB the first time the branch is taken. This data enters the BTB in a slot with a history of strongly not-taken (overwriting previous data when present). Successfully predicted branches avoid any branch-latency penalties in the superpipeline. Unsuccessfully predicted branches result in a 4-5 cycle branch-latency penalty in the superpipeline. 2.3 Instruction Memory Management Unit (IMMU) For instruction prefetches the IMMU controls logical-to-physical address translation, memory access permissions, memory domain identifications, and attributes (governing operation of the instruction cache). The IMMU contains a 32-entry, fully associative Instruction Translation Look-A-Side Buffer (ITLB) that has a round-robin replacement policy. ITLB entries 0-30 can be locked. When an instruction prefetch misses in the ITLB, the IMMU invokes an automatic table-walk mechanism that fetches an associated descriptor from memory and loads it into the ITLB. The descriptor contains information for logical-to-physical address translation, memory access permissions, memory domain identifications, and attributes governing operation of the i-cache. The IMMU then continues the instruction prefetch by using the address translation just entered into the ITLB. When an instruction prefetch hits in the ITLB, the IMMU continues the prefetch using the address translation already resident in the ITLB. Access permissions for each of up to sixteen memory domains can be programmed. When an instruction prefetch is attempted to an area of memory in violation of access permissions, then the attempt is aborted and a prefetch abort is sent to the core for exception processing. The IMMU and DMMU can be enabled or disabled together. 8 August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Functional Overview 2.4 Data Memory Management Unit (DMMU) For data fetches, the DMMU controls logical-to-physical address translation, memory access permissions, memory domain identifications, and attributes (governing operation of the data cache or mini-data cache and write buffer). The DMMU contains a 32-entry, fully associative data translation look-a-side buffer (DTLB) that has a round-robin replacement policy. DTLB entries 0-30 can be locked. When a data fetch misses in the DTLB, the DMMU invokes an automatic table-walk mechanism that fetches an associated descriptor from memory and loads it into the DTLB. The descriptor contains information for logical-to-physical address translation, memory access permissions, memory domain identifications, and attributes (governing operation of the d-cache or mini-data cache and write buffer). The DMMU then continues the data fetch by using the address translation just entered into the DTLB. When a data fetch hits in the DTLB, the DMMU continues the fetch using the address translation already resident in the DTLB. Access permissions for each of up to sixteen memory domains can be programmed. When a data fetch is attempted to an area of memory in violation of access permissions, then the attempt is aborted and a data abort is sent to the core for exception processing. The IMMU and DMMU can be enable or disable together. 2.5 Instruction Cache (I-Cache) The I-Cache can contain high-use multiple code segments or entire programs, allowing the core access to instructions at core frequencies. This prevents core stalls caused by multicycle accesses to external memory. The 32 KByte i-cache is 32-set/32-way associative, where each set contains 32-ways and each way contains a tag address, a cache line (eight 32-bit words and one parity bit per word) of instructions, and a line-valid bit. For each of the 32 sets, 0-28 ways can be locked. Unlocked ways are replaceable via a round robin policy. The i-cache can be enabled or disabled. Attribute bits within the descriptors contained in the ITLB of the IMMU provide some control over an enabled i-cache. When a needed line (eight 32-bit words) is not present in the i-cache, the line is fetched (critical word first) from memory via a two-level-deep fetch queue. Datasheet August 2002 9 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Functional Overview 2.6 Data Cache (D-Cache) The D-Cache can contain high-use data such as lookup tables and filter coefficients, allowing the core access to data at core frequencies. This prevents core stalls caused by multicycle accesses to external memory. The 32 KByte d-cache is 32-set/32-way associative, where each set contains 32-ways and each way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirty bits (one for each of two 8-byte groupings in a line), and one valid bit. For each of the 32 sets, 0-28 ways can be locked, unlocked, or used as local SRAM. Unlocked ways are replaceable via a round robin policy. The d-cache (together with the mini-data cache) can be enabled or disabled. Attribute bits within the descriptors contained in the DTLB of the DMMU provide significant control over an enabled d-cache. These bits specify cache operating modes such as read and write allocate, write-back, write-through, and d-cache versus mini-data cache targeting The d-cache (and mini-data cache) work with the load buffer and pend buffer to provide “hit-under- miss” capability that allows the core to access other data in the cache after a “miss” is encountered (see Section 2.8, “Fill Buffer (FB) and Pend Buffer (PB)” on page 11 for more information). The d-cache (and mini-data cache) works in conjunction with the write buffer for data that is to be stored to memory (see Section 2.9, “Write Buffer (WB)” on page 11 for more information). 2.7 Mini-Data Cache The Mini-data Cache can contain frequently changing data streams such as MPEG video, allowing the core access to data streams at core frequencies. This prevents core stalls caused by multicycle accesses to external memory. The mini-data cache relieves the d-cache of data “thrashing” caused by frequently changing data streams. The 2 KByte mini-data cache is 32-set/2-way associative, where each set contains 2-ways and each way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirty bits (one for each of two 8-byte groupings in a line), and a valid bit. The mini-data cache uses a round robin replacement policy, and cannot be locked. The mini-data cache (together with the d-cache) can be enabled or disabled. Attribute bits contained within a coprocessor register specify operating modes write and/or read allocate, write-back, and write-through. The mini-data cache (and d-cache) work with the load buffer and pend buffer to provide “hit-under-miss” capability that allows the core to access other data in the cache after a “miss” is encountered (see Section 2.8, “Fill Buffer (FB) and Pend Buffer (PB)” on page 11 for more information). The mini-data cache (and d-cache) works in conjunction with the write buffer for data that is to be stored to memory (see Section 2.9, “Write Buffer (WB)” on page 11 for more information). 10 August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Functional Overview 2.8 Fill Buffer (FB) and Pend Buffer (PB) The 4-entry Fill Buffer works with the core to hold loads until the bus controller can act on them. The FB and the 4-entry Pend Buffer work with the d-cache and mini-data cache to provide “hit-under-miss” capability, allowing the core to seek other data in the caches while “miss” data is being fetched from memory. The FB can contain up to four unique “miss” addresses (logical), allowing four “misses” before the core is stalled. The PB holds up to four addresses (logical) for additional “misses” to those addresses that are already in the FB. A coprocessor register can specify draining of the Fill and Pend (Write) Buffers. 2.9 Write Buffer (WB) The Write Buffer holds data for storage to memory until the bus controller can act on it. The WB is 8-entries deep, where each entry holds 16 bytes. The WB is constantly enabled, and accepts data from the core, d-cache, or mini-data cache. Coprocessor 15, register 1 specifies whether WB coalescing is enabled or disabled. When coalescing is disabled, stores to memory occur in program order regardless of the attribute bits within the descriptors located in the DTLB. When coalescing is enabled, the attribute bits within the descriptors located in the DTLB are examined to determine when coalescing is enabled for the destination region of memory. When coalescing is enabled in both CP15, R1 and the DTLB, then data entering the WB can coalesce with any of the 8-entries (16 bytes) and then be stored to the destination memory region, but possibly out of program order. Stores to a memory region specified to be non-cacheable and non-bufferable by the attribute bits within the descriptors located in the DTLB causes the Core to stall until the store completes. A coprocessor register can specify draining of the write buffer. 2.10 Multiply-Accumulate Coprocessor (CP0) For efficient processing of high-quality audio algorithms, CP0 provides 40-bit accumulation of 16x16, dual-16x16 (SIMD), and 32x32 signed multiplies. Special MAR and MRA instructions are implemented to Move 40-bit Accumulator to Two Core General Registers (MAR) and Move Two Core General Registers to 40-bit Accumulator (MRA). The 40-bit accumulator can be stored or loaded to or from d-cache, mini-data cache, or memory using two STC or LDC instructions. 16x16 signed multiply-accumulates (MIAxy) multiply either the high/high, low/low, high/low, or low/high 16 bits of a 32-bit core general register (multiplier) and another 32-bit core general register (multiplicand) to produce a full 32-bit product which is sign-extended to 40 bits and then added to the 40-bit accumulator. Dual signed 16x16 (SIMD) multiply-accumulates (MIAPH) multiply the high/high and low/low 16-bits of a packed 32-bit core general register (multiplier) and another packed 32-bit core general register (multiplicand) to produce two 16-bits products which are both sign-extended to 40 bits and then both added to the 40-bit accumulator. 32x32 signed multiply-accumulates (MIA) multiply a 32-bit core general register (multiplier) and another 32-bit core general register (multiplicand) to produce a 64-bit product where the 40 LSBs are added to the 40-bit accumulator. 16x32 versions of the multiply-accumulate instructions complete in a single cycle. Datasheet August 2002 11 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Functional Overview 2.11 Clock and Power Management The Intel® 80200 processor was designed with power saving techniques that power-up a functional block only when it is needed. Low power modes are selectable by programming CP 14, register 6. The Intel® 80200 processor was designed to allow dynamic clocking. The core clock frequency is set by programming CP14, Register 7. This enables software to conserve power by matching the core clock frequency to the current workload. 2.12 Performance Monitoring Unit (PMU) The Performance Monitoring Unit contains two 32-bit event counters and one 32-bit clock counter. The event counters can be programmed to monitor i-cache hit rate, data caches hit rate, ITLB hit rate, DTLB hit rate, pipeline stalls, BTB prediction hit rate, and instruction execution count. 2.13 Debug Unit The Debug Unit is accessed through the JTAG port. The industry-standard IEEE1149.1 JTAG port consists of a Test Access Port (TAP) controller, Boundary-Scan register, instruction and data registers, and dedicated signals TDI, TDO, TCK, TMS, and TRST#. The debug unit, when used with debugger application code running on a host system outside of the Intel® 80200 processor, allows a program running on the Intel® 80200 processor to be debugged. It allows the debugger application code or a debug exception to stop program execution and re-direct execution to a debug handling routine. Debug exceptions are instruction breakpoint, data breakpoint, software breakpoint, external debug breakpoint, exception vector trap, and trace buffer full breakpoint. Once execution has stopped, the debugger application code can examine or modify the core’s state, co-processor state, or memory. The debugger application code can then restart program execution. The debug unit has two hardware instruction breakpoint registers, two hardware data breakpoint registers, and a hardware data breakpoint control register. The second data breakpoint register can be alternatively used as a mask register for the first data breakpoint register. A 256-entry trace buffer provides the ability to capture control flow messages or addresses. A JTAG instruction (LDIC) can be used to download a debug handler via the JTAG port to the mini-instruction cache (the i-cache has a 2 KByte mini-instruction cache, like the mini-data cache, that is used only to hold a debug handler). 12 August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Package Information 3.0 Package Information 3.1 Package Introduction The Intel® 80200 processor is offered in a Plastic Ball Grid Array (PBGA) package. See Figure 2 “241-Lead PBGA Package” on page 17. 3.1.1 Functional Signal Definitions This section defines the pins and signals in the following tables: • • • • Table 2 “Pin Description Nomenclature” on page 13 Table 3 “Power Pins” on page 14 Table 4 “Signal Pin Description” on page 14 Table 5 “JTAG Pins” on page 16 3.1.1.1 Signal Pin Descriptions Table 2. Pin Description Nomenclature Symbol I Description Input pin only O Output pin only I/O Pin can be either an input or output - Pin must be connected as described N/C NO CONNECT. Do not make electrical connections to these balls. Rst(...) While the RESETOUT# pin is asserted, the pin: • Rst(1) Is driven to Vcc • Rst(0) Is driven to Vss • Rst(X) Is driven to unspecified state (1 or 0, buses may contain a mix of 1 and 0 signals) • Rst(H) Is pulled up to Vcc • Rst(L) Is pulled down to Vss • Rst(Z) Floats • Rst(Q) Is a valid output Hld(...) While the Intel® 80200 processor is in HOLD mode (HOLD asserted and took effect), the pin: • Hld(Z) Floats • Hld(Q) is a valid output • Hld(1) is driven to Vcc Since RESET# is asynchronous, these are asynchronous events. Note: When both HLDA and RESETOUT# are asserted, then HOLD mode takes priority; the output pins assume the state specified by Hld(...). The HOLD pin is also honored during Idle and Sleep modes; the output pins assume the state specified by Hld(...). Slp(...) Datasheet While the Intel® 80200 processor is in Idle or Sleep mode (software selected), pin: • Slp(1) Is driven to Vcc • Slp(0) Is driven to Vss • Slp(X) Is driven to unspecified state • Slp(Q) Is a valid output August 2002 13 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Package Information Table 3. Table 4. Power Pins Name Count Description VCC 17 Positive supply for the core. V SS 70 Ground. VCCP 25 Positive supply for the I/O pins. V CCA 1 Positive supply for the analog circuitry (PLL). Signal Pin Description (Sheet 1 of 2) Name Count Type 16 O Rst(X) Hld(Z) Slp(X) A[15:0] 1 I 1 O Rst(1) Hld(Z) Slp(1) 8 BE[7:0]# CLK O Rst(Z) Hld(Q)1 Slp(Z) Byte Enable: Signifies which bytes are valid during a write transaction. When not in use, this bus is floated (Z). CLK: Clock input for the core logic. 1 I Critical Word First: When active during a data read transaction, CWF informs the core of the data wrap order. DBusWidth: While RESET# is asserted, this pin is sampled by the Intel® 80200 processor to determine when the data bus is to be configured as 32-bits or 64-bits. When the pin is sampled as ‘0’ during reset, the 80200 assumes a 64-bit bus. When the pin is ‘1’ at reset, a 32-bit bus is assumed. 64 I/O Rst(Z) Hld(Q)1 Slp(Z) Data Bus: Carries data to/from the processor during a bus transaction. When not in use, this bus is floated (Z). 8 I/O Rst(Z) Hld(Q)1 Slp(Z) Data Check Byte: Carries the optional ECC information associated with the data on the Data bus. When not in use, this bus is floated (Z). 1 I Data Valid: Asserted when the Data bus carries valid data. 1 I Fast Interrupt Request: When FIQs are enabled, the processor responds to a low level on this input by taking the FIQ interrupt exception. 1 O Rst(0) Hld(1) Slp(0) DCB[7:0] FIQ# 14 During the second cycle of the issue phase, this signal is the MSB of a value which indicates the length of the transaction. I D[63:0] HLDA Address Strobe/Length: During the first cycle of the issue phase, this signal indicates the start of a bus request. 1 CWF/ DBusWidth (Config. Pin) DVALID Address Bus: Conveys either the upper or lower half of a 32-bit address during the issue phase of a bus transaction. Abort Transaction: When asserted during the data phase of a transaction, this signal causes the remainder of that transaction to be aborted. ABORT ADS#/LEN[2] Description HLDA: This output is asserted when the 80200 has floated the shared bus signals in response to HOLD. August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Package Information Table 4. Signal Pin Description (Sheet 2 of 2) Name Count Type 1 I HOLD: Requests the Intel® 80200 processor to float shared bus signals. 1 I Interrupt Request: When IRQs are enabled, the processor responds to a low level on this input by taking the IRQ interrupt exception. 1 O Rst(X) Hld(Z) Slp(X) Atomic Transaction Indicator/Length: During the first cycle of the issue phase, this signal indicates the current transaction is part of an atomic read-write pair. During the second cycle of the issue phase, this signal is the middle bit of a value which indicates the length of the transaction. 1 I Pad Voltage Level: When tied to the same level as VCCP, indicates voltage for the device pins (VCCP) is less than 2.5V. When tied to VSS, indicates voltage at the device pins is greater than or equal to 2.5V. 1 I Core Voltage Level: When tied to the same level as VCCP, indicates voltage for the core (VCC) is less than 1.0V. When tied to VSS, indicates voltage for the core is greater than or equal to 1.0V. MCLK 1 I Memory Clock: all bus signals must be synchronous to this clock. N/C 8 N/C NO CONNECT. Do not make electrical connections to these balls. 1 I PLL Configuration: While RESET# is asserted, this pin is sampled by the 80200 to select the initial clock multiplier value. When tied high, the initial clock multiplier is 6. When tied low, the initial clock multiplier is 3. This signal must be tied to a valid level at all times. When using the Intel 80312 I/O companion chip, this signal must be tied high. 2 O Rst(0) Hld(Q) Slp(Q) Power Status Indicator: Indicates the current power mode of the Intel® 80200 processor. This signal contains an encoded value to indicate the current power state: HOLD IRQ# LOCK/LEN[1] LOWVPP LOWVCC PLLCFG (Config. Pin) PWRSTATUS[1: 0] Description 00 for Normal 01 for Idle 10 for Reserved (Do Not Use) 11 for Sleep 1 I 1 O Rst(0) Hld(Q) Slp(1) 1 O Rst(X) Hld(Z) Slp(X) RESET# RESETOUT# W_R#/LEN[0] Reset: When asserted, this signal resets the processor. This signal must be asserted for at least 32 consecutive MCLK cycles to achieve a valid reset. Reset Status Output: This signal is asserted when the processor detects RESET#, and deasserts when the processor has completed resetting. Address Strobe/Length: During the first cycle of the issue phase, this signal indicates that the current transaction is a read (W_R# = 0) or a write (W_R# = 1). During the second cycle of the issue phase, this signal is the LSB of a value which indicates the length of the transaction. 1. For signals D, DCB, BE# during Hold mode, these continue to carry valid data until all pending transactions from the 80200 have been completed. Then these signals float. Datasheet August 2002 15 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Package Information Table 5. JTAG Pins Name Count Type Description 1 I TEST CLOCK is an input which provides the clocking function for the IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data are clocked into the component on the rising edge and data is clocked out of the component on the falling edge. 1 I TEST DATA INPUT is the serial input pin for the JTAG feature. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port. This signal has a weak internal pullup to ensure proper operation when this signal is unconnected. 1 O TEST DATA OUTPUT is the serial output pin for the JTAG feature. TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At other times, TDO floats. 1 I TEST RESET asynchronously resets the Test Access Port (TAP) controller function of IEEE 1149.1 Boundary Scan Testing (JTAG). This signal has a weak internal pullup to ensure proper operation when this signal is unconnected. TRST# must be driven low during processor reset to ensure proper operation. Additionally, before performing JTAG test, the processor should be reset and should have a valid clock at CLK to ensure it does not enter a low-power mode. 1 I TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of the test logic for IEEE 1149.1 Boundary Scan testing. This signal has a weak internal pullup to ensure proper operation when this signal is unconnected. TCK TDI TDO TRST# TMS 16 August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Package Information 3.1.2 241 Lead PBGA Package Figure 2. 241-Lead PBGA Package A8276-01 Datasheet August 2002 17 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Package Information Table 6. 241-Lead PBGA Pinout — Ballpad Number Order (Sheet 1 of 2) Ball # 18 Signal Ball # Signal Ball # Signal A1 VSS C8 BE1# E17 FIQ# A2 V CCP C9 BE4# F1 D32 A3 V CC C10 ADS# F2 D6 A4 DCB1 C11 W/R# F3 D7 A5 DCB2 C12 ABORT F4 VSS A6 DCB6 C13 PWRSTATUS1 F5 VSS A7 BE0# C14 VSS F13 VSS A8 BE3# C15 VSS F14 VSS A9 BE5# C16 VSS F15 VSS A10 BE6# C17 NC F16 VSS A11 LOCK D1 D0 F17 VCC A12 NC D2 D1 G1 D33 A13 RESETOUT# D3 D2 G2 VSS A14 PWRSTATUS0 D4 NC G3 D34 A15 VSS D5 VSS G4 D35 A16 VCCP D6 VSS G5 VCC A17 VSS D7 DCB5 G13 VCC B1 VCCP D8 VSS G14 VSS B2 VSS D9 VCCP G15 VSS B3 VSS D10 VSS G16 VCCP B4 DVALID D11 HOLD G17 RESET# B5 VSS D12 VCC H1 D36 B6 DCB4 D13 VSS H2 D37 B7 VCCP D14 VSS H3 D38 B8 BE2# D15 NC H4 VSS B9 VSS D16 LOWVCC H8 VSS B10 BE7# D17 VCCP H9 VSS B11 VCCP E1 D3 H10 VSS B12 CWF E2 VCC H14 VCCP B13 VSS E3 D4 H15 VSS B14 HLDA E4 D5 H16 PLLCFG B15 VCC E5 VCCP H17 NC B16 VSS E6 VSS J1 D39 B17 VCC E7 VCC J2 VCCP C1 VCC E9 VSS J3 D8 C2 VCCP E11 VSS J4 D9 C3 VSS E12 VSS J5 VCCP C4 VCCP E13 VCCP J8 VSS C5 DCB0 E14 VSS J9 VSS C6 DCB3 E15 IRQ# J10 VSS C7 DCB7 E16 VSS J13 VCCP August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Package Information Table 6. 241-Lead PBGA Pinout — Ballpad Number Order (Sheet 2 of 2) Ball # Datasheet Signal Ball # Signal Ball # Signal J14 VSS N7 VCC R16 VCC J15 NC N9 VCCP R17 A0 J16 VSS N11 VCC T1 D18 J17 NC N12 VSS T2 D19 K1 D10 N13 VCCP T3 VCC K2 D11 N14 VSS T4 D50 K3 D12 N15 VSS T5 VSS K4 VSS N16 VSS T6 D53 K8 VSS N17 VCCP T7 VCCP K9 VSS P1 D45 T8 D28 K10 VSS P2 D46 T9 VSS K14 VCCA P3 D16 T10 D58 K15 VSS P4 VSS T11 VCCP K16 CLK P5 D21 T12 D63 K17 MCLK P6 VSS T13 VSS L1 D13 P7 D55 T14 A10 L2 VSS P8 VSS T15 VSS L3 D14 P9 D56 T16 A3 L4 D40 P10 VSS T17 A1 L5 VCC P11 A13 U1 D20 L13 VCC P12 A8 U2 D23 L14 VSS P13 A4 U3 D48 L15 TRST# P14 VSS U4 D49 L16 VCCP P15 TMS U5 D51 L17 TCK P16 NC U6 D24 M1 D15 P17 TD0 U7 D25 M2 D41 R1 D47 U8 D27 M3 D42 R2 VSS U9 D30 M4 VCC R3 D17 U10 D57 M5 VSS R4 D22 U11 D60 M13 VSS R5 D52 U12 D62 M14 VCCP R6 D54 U13 A15 M15 VSS R7 D26 U14 A14 M16 LOWVPP R8 D29 U15 A11 M17 TDI R9 D31 U16 A7 N1 D43 R10 D59 U17 A5 N2 VCCP R11 D61 N3 D44 R12 A12 N4 VSS R13 A9 N5 VCCP R14 A6 N6 VSS R15 A2 August 2002 19 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Package Information Table 7. 241-Lead PBGA Pinout — Signal Name Order (Sheet 1 of 2) Signal 20 Ball # Signal Ball # Signal Ball # A0 R17 D14 L3 D55 P7 A1 T17 D15 M1 D56 P9 A2 R15 D16 P3 D57 U10 A3 T16 D17 R3 D58 T10 A4 P13 D18 T1 D59 R10 A5 U17 D19 T2 D60 U11 A6 R14 D20 U1 D61 R11 A7 U16 D21 P5 D62 U12 A8 P12 D22 R4 D63 T12 A9 R13 D23 U2 DCB0 C5 A10 T14 D24 U6 DCB1 A4 A11 U15 D25 U7 DCB2 A5 A12 R12 D26 R7 DCB3 C6 A13 P11 D27 U8 DCB4 B6 A14 U14 D28 T8 DCB5 D7 A6 A15 U13 D29 R8 DCB6 ABORT C12 D30 U9 DCB7 C7 BE0# A7 D31 R9 DVALID B4 BE1# C8 D32 F1 HLDA B14 BE2# B8 D33 G1 HOLD D11 BE3# A8 D34 G3 LOCK A11 BE4# C9 D35 G4 LOWVCC D16 BE5# A9 D36 H1 LOWVPP M16 BE6# A10 D37 H2 MCLK K17 BE7# B10 D38 H3 ADS# C10 CLK K16 D39 J1 NC A12 CWF B12 D40 L4 NC C17 D0 D1 D41 M2 NC D4 D1 D2 D42 M3 NC D15 D2 D3 D43 N1 NC J15 D3 E1 D44 N3 NC J17 D4 E3 D45 P1 NC H17 D5 E4 D46 P2 NC P16 D6 F2 D47 R1 FIQ# E17 D7 F3 D48 U3 IRQ# E15 D8 J3 D49 U4 RESET# G17 D9 J4 D50 T4 RESETOUT# A13 D10 K1 D51 U5 TRST# L15 D11 K2 D52 R5 PLLCFG H16 D12 K3 D53 T6 PWRSTATUS0 A14 D13 L1 D54 R6 PWRSTATUS1 C13 August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Package Information Table 7. 241-Lead PBGA Pinout — Signal Name Order (Sheet 2 of 2) Signal Datasheet Ball # Signal Ball # Signal Ball # TCK L17 VCC L5 VSS H15 TD0 P17 VCC M4 VSS H4 TDI M17 VCC N11 VSS H8 TMS P15 VCC N7 VSS H9 VCCA K14 VCC R16 VSS J10 VCCP A16 VCC T3 VSS J14 VCCP A2 VSS A1 VSS J16 VCCP B1 VSS A15 VSS J8 VCCP B11 VSS A17 VSS J9 VCCP B7 VSS B13 VSS K10 VCCP C2 VSS B16 VSS K15 VCCP C4 VSS B2 VSS K4 VCCP D17 VSS B3 VSS K8 VCCP D9 VSS B5 VSS K9 VCCP E13 VSS B9 VSS L14 VCCP E5 VSS C14 VSS L2 VCCP G16 VSS C15 VSS M13 VCCP H14 VSS C16 VSS M15 VCCP J13 VSS C3 VSS M5 VCCP J2 VSS D10 VSS N12 VCCP J5 VSS D13 VSS N14 VCCP L16 VSS D14 VSS N15 VCCP M14 VSS D5 VSS N16 VCCP N13 VSS D6 VSS N4 VCCP N17 VSS D8 VSS N6 VCCP N2 VSS E11 VSS P10 VCCP N5 VSS E12 VSS P14 VCCP N9 VSS E14 VSS P4 VCCP T11 VSS E16 VSS P6 VCCP T7 VSS E6 VSS P8 VCC A3 VSS E9 VSS R2 VCC B15 VSS F13 VSS T13 VCC B17 VSS F14 VSS T15 VCC C1 VSS F15 VSS T5 VCC D12 VSS F16 VSS T9 VCC E2 VSS F4 W/R# C11 VCC E7 VSS F5 VCC F17 VSS G14 VCC G13 VSS G15 VCC G5 VSS G2 VCC L13 VSS H10 August 2002 21 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Package Information 3.2 Package Thermal Specifications 3.3 Package Thermal Resistance The Intel® 80200 processor is specified for operation when TC (case temperature) is within the range of 0°C to 90°C. Case temperature may be measured in any environment to determine whether the device is within its specified operating range. The case temperature should be measured at the center of the top surface, opposite the pins. θCA is the thermal resistance from case to ambient. Use the following equation to calculate TA, the maximum ambient temperature to conform to a particular case temperature: TA = TC - P (θCA) Junction temperature (TJ) is commonly used in reliability calculations. TJ can be calculated from θJC (thermal resistance from junction to case) using the following equation: TJ = TC + P (θJC) Similarly, when TA is known, the corresponding case temperature (TC) can be calculated as follows: TC = TA + P (θCA) Table 8. Package Thermal Resistance — °C/Watt Airflow — ft./min (m/sec) Parameter θJC (Junction-to-Case) θCA (Case-to-Ambient) (No Heatsink) θJA θJC 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 1.5 1.5 1.5 1.5 28.5 20.0 18.1 17.1 θCA NOTES: 1. This table applies to an PBGA device soldered directly into a board with all VSS connections. 2. θJA = θJC + θCA Figure 3 and Figure 4 show an application of the supplied thermal data. Here, we plot the case temperature under several conditions. 22 August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Package Information Figure 3. Case Temperature with No Air Flow Case Temperature withNoAir Flow, Various Ambient Temperatures Case Temperature (degrees C) 140 120 100 Ta =0C 80 Ta =30C 60 Ta =60C 40 20 0 0.00 1.00 2.00 3.00 Total Power Dissipation Figure 4. Case Temperature at Nominal Power Dissipation Case Temperature vs. Air Flow, Various Ambient Temperatures, Nominal Power Dissipation (1 W) Case Temperature (degrees C) 100 90 80 70 60 Ta = 0C 50 Ta = 30C 40 Ta = 60C 30 20 10 0 0 100 200 300 400 500 Air Flow (LFM) Datasheet August 2002 23 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Electrical Specifications 4.0 Electrical Specifications 4.1 Absolute Maximum Ratings Parameter Maximum Rating Storage Temperature –55°C to + 125°C Case Temperature Under Bias 0°C to + 90°C Supply Voltage VCC wrt. VSS 2.1V Supply Voltage VCCP wrt. VSS 5.0V Supply Voltage VCCA wrt. VSS 2.1V NOTICE: This data sheet contains information on products in the design phase of development. Do not finalize a design with this information. Revised information is published when the product becomes available. The specifications are subject to change without notice. Contact your local Intel representative before finalizing a design. –0.5 V to Voltage on Any Ball wrt. VSS VCCP + 0.5 V †WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Table 9. Operating Conditions Symbol Table 10. Parameter Min Max Units VCC Core Supply Voltage 0.95 1.55 V VCCP Periphery Supply Voltage 3.0 3.6 V VCCA Analog Supply Voltage 0.95 1.55 V FP_CLK Input Clock Frequency 33.33 66.66 MHz TC Case Temperature Under Bias 0 90 °C Notes Voltage Range Requirements for Intel® 80200 Processor Product Options Product Options Operating @ 333MHz Operating @ 400MHz Operating @ 600MHz Operating @ 733MHz 80200M733 1.0v — 1.5v 1.1v — 1.5v 1.3v — 1.5v 1.5v ±5% 80200M600 1.1v — 1.5v 1.3v —1.5v 1.5v ±5% — 80200M400 1.1v — 1.3v 1.3v ±5% — — NOTES: 1. Processor operation beyond the voltage and frequency (as marked on the device) is not guaranteed. 2. Includes VCC and VCCA. 24 August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Electrical Specifications 4.2 VCCA Pin Requirements To reduce voltage supply noise on the Intel® 80200 processor, the VCC A pin for the Phase Lock Loop (PLL) circuit is isolated on the pinout. The lowpass filter, as shown in Figure 5, reduces noise induced clock jitter and its effects on timing relationships in system designs. The trace lengths between the 4.7µF capacitor, the 0.01µF capacitor, and VCCA must be as short as possible. Figure 5. VCCA Lowpass Filter 10Ω, 5%, 1/8W VCC (Board Plane) 4.7µF Datasheet VCCA + August 2002 0.01µF (On Intel® 80200 Processor) 25 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Electrical Specifications 4.3 Targeted DC Specifications Table 11. DC Characteristics Symbol VIL Parameter Min Input Low Voltage Max Units -0.5 0.8 V 2.4 VCCP + 0.5 V 2.1 V CCP + 0.5 V IH Input High Voltage V OL Output Low Voltage V OH Output High Voltage C IN Input Capacitance 5 pF C OUT I/O or Output Capacitance 5 pF C CLK CLK Capacitance 5 pF LPIN Ball Inductance TBD nH 0.3 VCCP - 0.3 Notes A-1 step D-0 step V 1 V 2 NOTES: 1. VOL measured at IOL = 3mA 2. VOH measured at IOH = 2mA Table 12. ICC Characteristics Max Units ILO Symbol Output Leakage Current Parameter Typ 220 µA 0.4 ≤ VOUT ≤ VCC Notes ILI Input Leakage Current 220 µA 0 ≤ VIN ≤ VCC Icc 720 mA Icca 95 mA Icc 520 mA Icca 65 mA Icc 410 mA Icca 13 mA 165 mA Icc 190 mA Icca 700 µA Icc 135 mA Icca 600 µA TBD mA Core and Analog Current 733MHz at 1.5v 600MHz at 1.3v ICC Active (Power Supply) 400MHz at 1.3v For typical power dissipation, see section 4.9 Periphery Current 100MHz at 3.6v Iccp Idle Mode at 1.5v ICC Active (Idle Mode) ICC Active (Sleep Mode) 26 at 1.3v TBD Sleep Mode August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Electrical Specifications 4.4 Targeted AC Specifications 4.4.1 Clock Signal Timings Table 13. Input Clock Timings Symbol Parameter Min Max Units 33.33 66.66 MHz Notes TF CLK Frequency TC CLK Period TCS CLK Period Stability TCH CLK High Time TCL CLK Low Time TCR CLK Rise Slew Rate 1.5 3.5 V/ns 0.4 V to 2.4 V (2) TCF CLK Fall Slew Rate 1.5 3.5 V/ns 2.4 V to 0.4 V (2) TMF MCLK Frequency 0 100 MHz TMC MCLK Period TMCS MCLK Period Stability TMCH MCLK High Time 2.5 TMCL MCLK Low Time 2.5 TMCR MCLK Rise Slew Rate 1.5 4.5 V/ns 0.4 V to 2.4 V (2) TMCF MCLK Fall Slew Rate 1.5 4.5 V/ns 2.4 V to 0.4 V (2) 15 30 ns (1) 20 ps Adjacent Clocks (2) 5 ns Measured at 1.5 V (2) 5 ns Measured at 1.5 V (2) 10 250 ns (1) ps Adjacent Clocks (2) ns Measured at 1.5 V (2) ns Measured at 1.5 V (2) NOTES: 1. See Figure 6 and Figure 7. 2. Not tested. Datasheet August 2002 27 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Electrical Specifications 4.4.2 Bus Signal Timings Table 14. Output Timings Symbol Parameter Min Max Units TOV1 Output valid delay from MCLK -D[63:0], DCB, and BE# 1.5 6.9 ns TOF1 Output float delay from MCLK -D[63:0], DCB, and BE# 1.1 6.0 ns TOS1 Output Slew Rate -- D[63:0], DCB, and BE# 1.0 4.0 V/ns Output valid delay from MCLK -A[15:0], HLDA, W/R#, LOCK, and ADS# 1.5 6.8 ns TOV2 Output float delay from MCLK -A[15:0], HLDA, W/R#, LOCK, ADS#, RESETOUT#, and PWRSTATUS 1.1 TOF2 Output Slew Rate -- A[15:0], HLDA, W/R#, LOCK, ADS#, RESETOUT#, and PWRSTATUS 1.0 TOS2 Notes (1, 2) (1, 2, 3) 0.4 V to 2.4 V (1, 2, 4) (1, 2, 4) 6.0 ns (1, 2, 3, 4) 4.0 V/ns 0.4 V to 2.4 V (1, 2, 4) NOTES: 1. Minimum values characterized with a 10 pF load at 3.6 V, 0°C 2. Maximum values characterized with a 30 pF load at 2.9 V., 110°C 3. Pin is floating when its output falls to ILO 4. Not tested Table 15. Input Timings Symbol 28 Parameter Min Max Units Input setup time to MCLK -ABORT, CWF, DVALID, D, and DCB 1.2 ns TIS Input hold time from MCLK -ABORT, CWF, DVALID, D, and DCB 1.5 ns TIH TISH Input setup time to MCLK -HOLD 1.3 ns TIHH Input hold time from MCLK -HOLD 0.9 ns August 2002 Notes Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Electrical Specifications 4.4.3 Boundary Scan Test Signal Timings Table 16. Boundary Scan Test Signal Timings Symbol Datasheet Parameter Min Max Units 40.0 MHz Notes TBSF TCK Frequency 0.0 TBSCH TCK High Time 12.5 ns Measured at 1.5 V TBSCL TCK Low Time 12.5 ns Measured at 1.5 V TBSCR TCK Rise Time ns 0.8 V to 2.0 V TBSCF TCK Fall Time ns 2.0 V to 0.8 V TBSIS1 Input Setup to TCK — TDI, TMS 4.0 ns TBSIH1 Input Hold from TCK — TDI, TMS 6.0 ns TBSIS2 Input Setup to TCK — TRST# 25.0 ns TBSIH2 Input Hold from TCK — TRST# 3.0 ns 5.0 5.0 TBSOV1 TDO Valid Delay 1.5 6.9 ns Relative to falling edge of TCK TOF1 TDO Float Delay 1.1 5.4 ns Relative to falling edge of TCK TOV12 All Outputs (Non-Test) Valid Delay 1.5 6.9 ns TOF2 All Outputs (Non-Test) Float Delay 1.1 5.4 ns TIS10 Input Setup to TCK — All Inputs (Non-Test) 4.0 ns TIH8 Input Hold from TCK — All Inputs (Non-Test) 6.0 ns August 2002 Relative to falling edge of TCK Relative to falling edge of TCK 29 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Electrical Specifications 4.5 AC Timing Waveforms Figure 6. CLK Waveform TCR TCF 2.4V 1.5V 0.4V TCH TCL TC Figure 7. MCLK Waveform TMCR TMCF 2.4V 1.5V 0.4V TMCH TMCL TMC 30 August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Electrical Specifications Figure 8. TOV Output Delay Waveform MCLK 1.5V 1.5V TOVX Minimum TOVX Max Output Datasheet 1.5V August 2002 Valid 1.5V 31 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Electrical Specifications 4.6 Power Sequence Power must be supplied to the component’s pads (VCCP) before or concurrently with power to the components core (V CC). Power must not be applied to VCC prior to VCCP. Figure 9 and Figure 10 show correct power sequences. Figure 11 shows an incorrect power sequence; do not allow this. Correct Power Sequence for VCC, VCCP VCCP VCC 1.3 Voltage 3.3 Figure 9. Time Another Correct Power Sequence for VCC, VCCP VCCP VCC 1.3 Voltage 3.3 Figure 10. Time Incorrect Power Sequence for VCC, VCCP VCCP VCC 1.3 Voltage 3.3 Figure 11. Time 32 August 2002 Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Electrical Specifications VCC and VCCA (PLL supply) should be brought up concurrently. When this cannot be attained, VCC should be brought up before VCCA. Figure 12 shows the preferred method where VCC and VCCA are brought up at the same time. Figure 13 shows the alternative. Preferred Power Sequence for VCC, VCCa VCC and VCCA Voltage 1.3 Figure 12. Time Correct Power Sequence for VCC, VCCa VCC Voltage 1.3 Figure 13. VCCA Time Datasheet August 2002 33 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Electrical Specifications 4.7 Reset Timing Figure 14 shows the sequence of pin states that may be assumed at processor reset. See the Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Developer’s Manual for more information on reset timing. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ PWRSTATUS ~ ~ ~ ~ ~ ~ ~ ~ ADS# ~ ~ ~ ~ ~ ~ ~ ~ 4.8 ~ ~ ~ ~ ~ ~ HLDA ~ ~ HOLD ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ RESETOUT# ~ ~ RESET# ~ ~ ~ ~ MCLK ~ ~ CLK ~ ~ Pins’ State at Reset ~ ~ Figure 14. AC Test Conditions The AC specifications in Section 4.4, “Targeted AC Specifications” on page 27 are tested with a 30 pF load indicated in Figure 15. Figure 15. AC Test Load Output Ball CL 34 August 2002 CL = 30 pF Datasheet Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Electrical Specifications 4.9 Typical Power Dissipation The total dissipated power is the sum of the power requirements from the device pins and the internal logic. Both are dependent on the operating frequency, voltage, and activity. Because the device pins are operating under different conditions than the internal logic, the typical power dissipation curves for both are in this section. Figure 16. Typical Pin Power Dissipation1 Bus Speed vs. Power (M oderate Bus Utilization) 0.60 Pin Power (Watts) 0.50 0.40 66 MHz bus 0.30 100MHz bus 0.20 0.10 0.00 3.00 3.10 3.20 3.30 3.40 3.50 3.60 Vccp (Volts) 1. Assume system driving one PC-100 DIMM and a companion chip with 10pF/pin capacitance. Figure 17. Typical Core Power Dissipation C or e P o we r ( on D h r y st on e 2 . 1: h i g h c o r e a c t i v i t y ) 0.700 Core Power (Watts) 0.600 0.500 0.400 400 MHz 600 MHz 0.300 0.200 0.100 0.000 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 Vcc (Volts) Datasheet August 2002 35 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Electrical Specifications This Page Intentionally Left Blank 36 August 2002 Datasheet