NTLTD7900ZR2 Power MOSFET 9 Amps, 20 Volts, Logic Level N–Channel Micro–8 Leadless EZFETs are an advanced series of Power MOSFETs which contain monolithic back–to–back zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc–dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. http://onsemi.com 9 AMPERES 20 VOLTS RDS(on) = 26 m (VGS = 4.5 V, ID = 6.5 A) RDS(on) = 31 m (VGS = 2.5 V, ID = 5.8 A) Applications • Zener Protected Gates Provide Electrostatic Discharge Protection • Designed to Withstand 4000 V Human Body Model • Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery • • • Life Logic Level Gate Drive – Can be Driven by Logic ICs Micro–8 Leadless Surface Mount Package – Saves Board Space IDSS Specified at Elevated Temperature Symbol Steady State 10 Secs 20 V Gate–to–Source Voltage VGS ±12 V Pulsed Drain Current (tp 10 s) ID Continuous Source–Diode Conduction (Note 1) Is Total Power Dissipation (Note 1) TA = 25°C TA = 85°C PD Operating Junction and Storage Temperature Range TJ, Tstg Thermal Resistance (Note 1) Junction–to–Ambient A IDM RJA 6.0 4.3 30 G1 G2 S2 1.4 3.2 1.7 1.5 0.79 1 1 Micro–8 Leadless CASE 846C A Y WW A W °C –55 to 150 °C/W 82 1. When surface mounted to 1″ x 1″ FR–4 board. N–Channel MARKING DIAGRAM A 2.9 38 2.4 k Unit VDSS 9.0 6.4 2.4 k N–Channel Drain–to–Source Voltage Continuous Drain Current (Note 1) TA = 25°C TA = 85°C D S1 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating D 7900 AYWW = Assembly Location = Year = Work Week PIN ASSIGNMENT Drain 8 Drain 7 Drain 6 Drain 5 1 Source 1 2 Gate 1 3 Source 2 4 Gate 2 Drain (Top View) ORDERING INFORMATION Semiconductor Components Industries, LLC, 2002 September, 2002 – Rev. 2 1 Device Package NTLTD7900ZR2 Micro–8 LL Shipping 2500 Tape & Reel Publication Order Number: NTLTD7900ZR2/D NTLTD7900ZR2 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Drain–to–Source Breakdown Voltage (Note 2) (VGS = 0 Vdc, ID = 250 Adc) V(BR)DSS Min Typ Max 20 24 – – – – – 1.0 20 – – – – 1.0 10 0.4 0.67 1.0 – – 21 27 26 31 Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 85°C) IDSS Gate–Body Leakage Current (VGS = 4.5 Vdc, VDS = 0 Vdc) (VGS = 12 Vdc, VDS = 0 Vdc) IGSS Vdc Adc Adc mAdc ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (Note 2) (VDS = VGS, ID = 250 Adc) VGS(th) Static Drain–to–Source On–Resistance (Note 2) (VGS = 4.5 Vdc, ID = 6.5 Adc) (VGS = 2.5 Vdc, ID = 5.8 Adc) RDS(on) Vdc m DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 16 Vdc, Vd VGS = 0 V, V f = 1.0 MHz) Output Capacitance Transfer Capacitance Ciss – 7.4 15 Coss – 237 400 Crss – 4.1 10 td(on) – 0.55 1.0 pF SWITCHING CHARACTERISTICS (Note 3) Turn–On Delay Time Rise Time Turn–Off Delay Time (VGS = 4.5 Vdc, VDD = 10 Vdc, ID = 1 1.0 0 Adc Adc, RG = 9 9.1 1 ) (Note 2) Fall Time Gate Charge (VGS = 4.5 Vdc, ID = 6.5 Adc, VDS S = 10 Vdc) (N t 2) (Note tr – 1.17 2.0 td(off) – 1.87 3.0 tf – 4.8 7.0 QT – 12 18 Q1 – 0.7 – Q2 – 3.7 – VSD – – 0.69 0.62 0.8 – s nC SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (IS = 1.0 Adc, VGS = 0 Vdc) IS = 1.0 Adc, VGS = 0 Vdc, TJ = 85°C) (Note 2) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 Vdc NTLTD7900ZR2 TYPICAL ELECTRICAL CHARACTERISTICS 10,000 IGSS, GATE–CURRENT (A) IGSS, GATE–CURRENT (mA) 8 6 4 2 1000 100 TJ = 150°C 10 1 TJ = 25°C 0.1 0.01 0 0 3 6 9 12 15 VGS, GATE–TO–SOURCE VOLTAGE (V) 18 Figure 1. Gate–Current versus Gate–Source Voltage 15 Figure 2. Gate–Current versus Gate–Source Voltage 30 30 2.4 V 2.8 V 3.5 V 24 18 ID, DRAIN CURRENT (A) 2.2 V 2.0 V 4.5 V 10 V 1.8 V 12 1.6 V 1.4 V 6 24 18 12 TC = 25°C 6 VGS = 1.2 V TC = 125°C 0 TC = –55°C 0 0 2 4 6 8 10 0 0.4 0.8 1.2 1.6 2.0 VDS, DRAIN–TO–SOURCE VOLTAGE (V) VGS, GATE–TO–SOURCE VOLTAGE (V) Figure 3. On–Region Characteristics Figure 4. Transfer Characteristics RDS(on), DRAIN–TO–SOURCE RESISTANCE () ID, DRAIN CURRENT (A) 3 6 9 12 VGS, GATE–TO–SOURCE VOLTAGE (V) 0 0.06 0.05 0.04 VGS = 2.5 V 0.03 0.02 VGS = 4.5 V 0.01 0 0 6 12 18 24 ID, DRAIN CURRENT (A) Figure 5. On–Resistance versus Drain Current http://onsemi.com 3 30 2.4 NTLTD7900ZR2 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG – VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1200 TJ = 25°C VGS = 0 V C, CAPACITANCE (pF) 1000 800 Coss 600 400 200 Ciss and Crss are below 10 pF 0 0 5 10 15 GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (V) Figure 6. Capacitance Variation http://onsemi.com 4 20 10,000 5 TJ = 25°C ID = 6.5 A tf 4 td(off) t, TIME (ns) VGS, GATE–TO–SOURCE VOLTAGE (V) NTLTD7900ZR2 3 tr 1000 2 td(on) VDS = 10 V ID = 6.5 A VGS = 4.5 V 1 100 0 0 2 4 6 8 10 Qg, TOTAL GATE CHARGE (nC) 12 1 14 Figure 7. Gate–to–Source 1.8 RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) TJ = 25°C VGS = 0 V 1 TJ = 150°C 0 0.2 0.4 0.6 ID = 9 A VGS = 4.5 V 1.6 1.4 1.2 1.0 –0.8 TJ = 25°C 0.6 –50 0.1 0.8 1 –25 0 ID = 250 A 0.1 0 –0.1 –0.2 –0.3 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 150 RDS(on), DRAIN–TO–SOURCE RESISTANCE () 0.2 –25 50 75 125 100 150 Figure 10. On–Resistance Variation with Temperature Figure 9. Diode Forward Voltage versus Current –0.4 –50 25 TJ, JUNCTION TEMPERATURE (°C) VSD, SOURCE–TO–DRAIN VOLTAGE (V) VGS(th), THRESHOLD VARIANCE (V) 100 Figure 8. Resistive Switching Time Variation versus Gate Resistance 10 IS, SOURCE CURRENT (A) 10 RG, GATE RESISTANCE () 0.040 0.035 TJ = 125°C 0.030 0.025 TJ = 25°C 0.020 TJ = –55°C 0.015 0.010 0.005 0 0 Figure 11. Threshold Voltage 5 10 15 20 25 ID, DRAIN CURRENT (A) Figure 12. On–Resistance versus Drain Current and Temperature http://onsemi.com 5 30 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) NTLTD7900ZR2 1 D = 0.5 0.2 0.1 0.1 0.05 P(pk) t1 0.02 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 0.01 10–4 10–3 10–2 10–1 t, TIME (seconds) 1 Figure 13. Thermal Response http://onsemi.com 6 10 100 1000 NTLTD7900ZR2 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177–189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 “RAMP” 200°C STEP 2 STEP 3 VENT HEATING “SOAK” ZONES 2 & 5 “RAMP” DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 “SOAK” 160°C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205° TO 219°C “SPIKE” PEAK AT 170°C SOLDER JOINT 150°C 150°C 100°C 140°C 100°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5°C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 14. Typical Solder Heating Profile http://onsemi.com 7 NTLTD7900ZR2 PACKAGE DIMENSIONS Micro–8 Leadless CASE 846C–01 ISSUE O ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ PIN 1 I.D. INDEX AREA 2 PL –T– W Y A M NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 4. DIMENSION D APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 MM AND 0.30 MM FROM TERMINAL TIP. DIMENSION L1 IS THE TERMINAL PULL BACK FROM PACKAGE EDGE, UP TO 0.1 MM IS ACCEPTABLE. L1 IS OPTIONAL. 5. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. SEATING PLANE J AA N B 0.15 T K AA C 2 PL 8 PL TOP VIEW 0.15 T 0.10 T 8 PL 0.10 M T W Y D 8 PL E L C4 8 PL C1 8 1 7 2 SIDE VIEW L1 F G 6 PL DETAIL Z 0.08 T 6 3 5 4 C3 P C2 MILLIMETERS MIN MAX 3.20 3.40 3.20 3.40 0.85 0.95 0.28 0.33 1.30 1.50 2.55 2.75 0.65 BSC 0.95 1.15 0.25 BSC 0.00 0.05 0.35 0.45 1.60 1.70 1.60 1.70 1.28 1.38 0.200 0.250 0.18 0.23 0.20 --- TERMINAL TIP S R U 4 PL NOTE 5 DIM A B C D E F G H J K L M N P R S U DETAIL Z H VIEW AA–AA EZFET is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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