NTF5P03T3 Preferred Device Power MOSFET 5.2 Amps, 30 Volts P–Channel SOT–223 Features • • • • • http://onsemi.com Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature SOT–223 Surface Mount Package Avalanche Energy Specified 5.2 AMPERES 30 VOLTS RDS(on) = 100 m P–Channel Applications • • • • • D DC–DC Converters Power Management Motor Controls Inductive Loads Replaces MMFT5P03HD G S MARKING DIAGRAM 4 1 2 SOT–223 CASE 318E STYLE 3 AWW 5P03 3 A WW 5P03 = Assembly Location = Work Week = Device Code PIN ASSIGNMENT 4 Drain 1 Gate 2 3 Drain Source ORDERING INFORMATION Semiconductor Components Industries, LLC, 2002 May, 2002 – Rev. 1 1 Device Package NTF5P03T3 SOT–223 Shipping 1000 Tape & Reel Publication Order Number: NTF5P03T3/D NTF5P03T3 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Negative sign for P–Channel devices omitted for clarity Rating Symbol Max Unit Drain–to–Source Voltage VDSS –30 V Drain–to–Gate Voltage (RGS = 1.0 M) VDGR –30 V VGS ± 20 V Thermal Resistance – Junction to Ambient Total Power Dissipation @ TA = 25°C Linear Derating Factor Drain Current – Continuous @ TA = 25°C Continuous @ TA = 70°C Pulsed Drain Current (Note 1) RTHJA PD 40 3.13 25 –5.2 –4.1 –26 °C/W Watts mW/°C A A A Thermal Resistance – Junction to Ambient Total Power Dissipation @ TA = 25°C Linear Derating Factor Drain Current – Continuous @ TA = 25°C Continuous @ TA = 70°C Pulsed Drain Current (Note 1) RTHJA PD IDM 80 1.56 12.5 –3.7 –2.9 –19 °C/W Watts mW/°C A A A TJ, Tstg – 55 to 150 °C Gate–to–Source Voltage – Continuous 1″ SQ. FR–4 or G–10 PCB 10 seconds Minimum FR–4 or G–10 PCB 10 seconds Operating and Storage Temperature Range Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C (VDD = –30 Vdc, VGS = –10 Vdc, Peak IL = –12 Apk, L = 3.5 mH, RG = 25 ) 1. Repetitive rating; pulse width limited by maximum junction temperature. http://onsemi.com 2 ID ID IDM ID ID EAS mJ 250 NTF5P03T3 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit –30 – – –28 – – – – – – –1.0 –25 – – ± 100 –1.0 – –1.75 3.5 –3.0 – – 76 107 100 150 gfs 2.0 3.9 – Mhos Ciss – 500 950 pF Coss – 153 440 Crss – 58 140 td(on) – 10 24 OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (Notes 2 and 4) (VGS = 0 Vdc, ID = –0.25 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = –24 Vdc, VGS = 0 Vdc) (VDS = –24 Vdc, VGS = 0 Vdc, TJ = 125°C) Gate–Body Leakage Current Vdc Adc IDSS (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS mV/°C nAdc ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (Cpk ≥ 2.0) (Notes 2 and 4) (VDS = VGS, ID = –0.25 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (Notes 2 and 4) (VGS = –10 Vdc, ID = –5.2 Adc) (VGS = –4.5 Vdc, ID = –2.6Adc) RDS(on) Forward Transconductance (Note 2) (VDS = –15 Vdc, ID = –2.0 Adc) Vdc mV/°C m DYNAMIC CHARACTERISTICS (VDS = –25 Vdc, VGS = 0 V, f=1 1.0 0 MH MHz)) Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3) (VDD = –15 Vdc, ID = –4.0 Adc, VGS = –10 10 Vdc, Vd RG = 6.0 ) (Note 2) Turn–On Delay Time Rise Time Turn–Off Delay Time Fall Time (VDD = –15 Vdc, ID = –2.0 Adc, VGS = –10 10 Vdc, Vd RG = 6.0 ) (Note 2) Turn–On Delay Time Rise Time Turn–Off Delay Time Fall Time Gate Charge (VDS = –24 Vdc, ID = –4.0 Adc, VGS = –10 10 Vdc) Vd ) (Note (N t 2) tr – 33 48 td(off) – 38 94 tf – 20 92 td(on) – 16 38 tr – 45 110 td(off) – 23 60 tf – 24 80 QT – 15 38 Q1 – 1.6 – Q2 – 3.5 – Q3 – 2.6 – – – –1.1 –0.89 –1.5 – ns ns nC SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage Reverse Recovery Time (IS = –4.0 Adc, VGS = 0 Vdc) (IS = –4.0 Adc, VGS = 0 Vdc, TJ = 125°C) (Note 2) VSD (IS = –4.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ A/s)) (Note (N t 2) trr – 34 – ta – 20 – tb – 14 – QRR – 0.036 – Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2.0%. 3. Switching characteristics are independent of operating junction temperatures. 4. Reflects typical values. Max limit Typ Cpk 3 SIGMA http://onsemi.com 3 Vdc ns C NTF5P03T3 TYPICAL ELECTRICAL CHARACTERISTICS 10 VGS = –4.3 V VGS = –4.5 V 4 VGS = –6.0 V VGS = –8.0 V VGS = –4.1 V 3 V = –10 V GS VGS = –3.9 V TJ = 25°C VGS = –3.7 V 2 VGS = –3.5 V VGS = –3.3 V 1 VGS = –3.1 V 0.3 0.9 0.6 1.2 VGS = –2.7 V 1.5 1.8 6 4 TJ = 25°C 2 TJ = 100°C TJ = –55°C 3.5 4.5 5 5.5 6 –VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics ID = –4.0 A TJ = 25°C 0.050 0.025 0 2 1 4 3 5 0.20 TJ = 25°C 0.15 VGS = –4.5 V 0.10 VGS = –10 V 0.05 0 0 2 1 3 4 5 7 6 –VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) –ID, DRAIN CURRENT (AMPS) Figure 3. On–Resistance versus Gate–to–Source Voltage Figure 4. On–Resistance versus Drain Current and Gate Voltage 1.6 8 100 VGS = 0 V ID = –2.0 A VGS = –10 V –IDSS, LEAKAGE (nA) 1.4 1.2 1 0.8 0.6 –50 4 –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 0.075 RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) 8 3 0.100 0 VDS ≥ –10 V 0 RDS(on), DRAIN–TO–SOURCE RESISTANCE () 0 0 RDS(on), DRAIN–TO–SOURCE RESISTANCE () –ID, DRAIN CURRENT (AMPS) –ID, DRAIN CURRENT (AMPS) 5 TJ = 125°C 10 TJ = 100°C 1 –25 0 25 50 75 100 125 150 0 10 15 20 25 –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C) Figure 6. Drain–to–Source Leakage Current versus Voltage Figure 5. On–Resistance Variation with Temperature http://onsemi.com 4 30 NTF5P03T3 TJ = 25°C Ciss 5000 C, CAPACITANCE (pF) VGS = 0 V VDS = 0 V 4000 Crss 3000 Ciss 2000 Coss 1000 Crss 0 10 –VGS 0 –VDS 10 20 30 12.5 7.5 15 –VGS 5.0 10 Q2 Q1 ID = –2 A TJ = 25°C 2.5 0 0 10 20 30 40 50 5 0 60 Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate–to–Source and Drain–to–Source Voltage versus Total Charge 3 –IS, SOURCE CURRENT (AMPS) td(off) t, TIME (ns) 20 GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) VDD = –15 V ID = –4.0 A VGS = –10 V tf 100 tr td(on) 1 10 RG, GATE RESISTANCE () 100 VGS = 0 V TJ = 25°C 2 1 0 0.5 100 VGS = 20 V SINGLE PULSE TC = 25°C 10 dc 1 10 ms 1 ms 0.1 0.01 0.1 100 s RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 s 10 100 0.6 0.7 0.8 0.9 –VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) 1.0 Figure 10. Diode Forward Voltage versus Current EAS, SINGLE PULSE DRAIN–TO–SOURCE AVALANCHE ENERGY (mJ) Figure 9. Resistive Switching Time Variation versus Gate Resistance –ID, DRAIN CURRENT (AMPS) QT 10 1000 10 25 –VDS –VDS, DRAIN–TO–SOURCE VOLTAGE (V) 6000 –VGS, GATE–TO–SOURCE VOLTAGE (V) TYPICAL ELECTRICAL CHARACTERISTICS 350 ID = –6 A 300 250 200 150 100 50 0 25 –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Mounted on 2”sq. FR4 board (1”sq. 2 oz. Cu 0.06” thick single sided) with on die operating, 10 s max. 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 5 NTF5P03T3 TYPICAL ELECTRICAL CHARACTERISTICS RTHJA(t), EFFECTIVE TRANSIENT THERMAL RESPONSE 1 D = 0.5 0.2 0.1 0.1 NORMALIZED TO RJA AT STEADY STATE (1″ PAD) 0.05 0.0175 CHIP JUNCTION 0.0154 F 0.02 0.01 0.0710 0.2706 0.5779 0.7086 0.0854 F 0.3074 F 1.7891 F 107.55 F AMBIENT SINGLE PULSE 0.01 1.0E-03 1.0E-02 1.0E-01 1.0E+00 t, TIME (s) 1.0E+01 1.0E+02 1.0E+03 Figure 13. FET Thermal Response INFORMATION FOR USING THE SOT–223 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.15 3.8 0.079 2.0 0.091 2.3 0.248 6.3 0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5 0.059 1.5 http://onsemi.com 6 inches mm NTF5P03T3 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177–189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 “RAMP” 200°C STEP 2 STEP 3 VENT HEATING “SOAK” ZONES 2 & 5 “RAMP” DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 “SOAK” 160°C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205° TO 219°C “SPIKE” PEAK AT 170°C SOLDER JOINT 150°C 150°C 100°C 140°C 100°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5°C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 14. Typical Solder Heating Profile http://onsemi.com 7 NTF5P03T3 PACKAGE DIMENSIONS SOT–223 (TO–261) CASE 318E–04 ISSUE K A F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 4 S B 1 2 3 D L G J C 0.08 (0003) M H K INCHES DIM MIN MAX A 0.249 0.263 B 0.130 0.145 C 0.060 0.068 D 0.024 0.035 F 0.115 0.126 G 0.087 0.094 H 0.0008 0.0040 J 0.009 0.014 K 0.060 0.078 L 0.033 0.041 M 0 10 S 0.264 0.287 STYLE 3: PIN 1. 2. 3. 4. MILLIMETERS MIN MAX 6.30 6.70 3.30 3.70 1.50 1.75 0.60 0.89 2.90 3.20 2.20 2.40 0.020 0.100 0.24 0.35 1.50 2.00 0.85 1.05 0 10 6.70 7.30 GATE DRAIN SOURCE DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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