MM54C373/MM74C373 TRI-STATEÉ Octal D-Type Latch MM54C374/MM74C374 TRI-STATE Octal D-Type Flip-Flop General Description The MM54C373/MM74C373, MM54C374/MM74C374 are integrated, complementary MOS (CMOS), 8-bit storage elements with TRI-STATE outputs. These outputs have been specially designed to drive high capacitive loads, such as one might find when driving a bus, and to have a fan out of 1 when driving standard TTL. When a high logic level is applied to the OUTPUT DISABLE input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM54C373/MM74C373 is an 8-bit latch. When LATCH ENABLE is high, the Q outputs will follow the D inputs. When LATCH ENABLE goes low, data at the D inputs, which meets the set-up and hold time requirements, will be retained at the outputs until LATCH ENABLE returns high again. The MM54C374/MM74C374 is an 8-bit, D-type, positiveedge triggered flip-flop. Data at the D inputs, meeting the set-up and hold time requirements, is transferred to the Q outputs on positive-going transitions of the CLOCK input. Both the MM54C373/MM74C373 and the MM54C374/ MM74C374 are being assembled in 20-pin dual-in-line packages with 0.300× pin centers. Features Y Y Y Y Y Y Y Y Y Wide supply voltage range High noise immunity Low power consumption TTL compatibility 3V to 15V 0.45 VCC (typ.) Fan out of 1 driving standard TTL Bus driving capability TRI-STATE outputs Eight storage elements in one package Single CLOCK/LATCH ENABLE and OUTPUT DISABLE control inputs 20-pin dual-in-line package with 0.300× centers takes half the board space of a 24-pin package Connection Diagrams MM54C374/MM74C374 Dual-In-Line Package MM54C373/MM74C373 Dual-In-Line Package TL/F/5906 – 1 TL/F/5906 – 2 Top View Top View Order Number MM54C373 or MM74C373 Order Number MM54C374 or MM74C374 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/5906 RRD-B30M105/Printed in U. S. A. MM54C373/MM74C373 TRI-STATE Octal D-Type Latch MM54C374/MM74C374 TRI-STATE Octal D-Type Flip-Flop March 1988 Absolute Maximum Ratings (Note 1) Power Dissipation Dual-In-Line Small Outline If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin Operating VCC Range b 0.3V to VCC a 0.3V Operating Temperature Range (TA) MM54C373 MM74C373 b 55§ C to a 125§ C b 40§ C to a 85§ C Storage Temperature Range (TS) b 65§ C to a 150§ C 700 mW 500 mW 3V to 15V 18V Absolute Maximum VCC Lead Temperature (TL) (Soldering, 10 seconds) 260§ C DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage VCC e 5V VCC e 10V VIN(0) Logical ‘‘0’’ Input Voltage VCC e 5V VCC e 10V VOUT(1) Logical ‘‘1’’ Output Voltage VCC e 5V, IO e b10 mA VCC e 10V, IO e b10 mA VOUT(0) Logical ‘‘0’’ Output Voltage VCC e 5V, IO e 10 mA VCC e 10V, IO e 10 mA IIN(1) Logical ‘‘1’’ Input Current VCC e 15V, VIN e 15V IIN(0) Logical ‘‘0’’ Input Current VCC e 15V, VIN e 0V b 1.0 b 0.005 IOZ TRI-STATE Leakage Current VCC e 15V, VO e 15V VCC e 15V, VO e 0V b 1.0 b 0.005 ICC Supply Current 3.5 8.0 V V 1.5 2.0 4.5 9.0 V V 0.5 1.0 0.005 0.005 VCC e 15V V V 0.05 1.0 V V mA mA 1.0 mA mA 300 mA CMOS/LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C 74C VCC e 4.5V VCC e 4.75V VIN(0) Logical ‘‘0’’ Input Voltage 54C 54C VCC e 4.5V VCC e 4.75V VOUT(1) Logical ‘‘1’’ Output Voltage 54C 74C VCC e 4.5V, IO e b360 mA VCC e 4.75V, IO e b360 mA VCC b 0.4 VCC b 0.4 V V 54C 74C VCC e 4.5V, IO e b1.6 mA VCC e 4.75V, IO e b1.6 mA 2.4 2.4 V V 54C 74C VCC e 4.5V, IO e 1.6 mA VCC e 4.75V, IO e 1.6 mA VOUT(0) Logical ‘‘0’’ Output Voltage VCC b 1.5 VCC b 1.5 V V 0.8 0.8 0.4 0.4 V V V V OUTPUT DRIVE (Short Circuit Current) ISOURCE Output Source Current VCC e 5V, VOUT e 0V TA e 25§ C (Note 4) b 12 b 24 mA ISOURCE Output Source Current VCC e 10V, VOUT e 0V TA e 25§ C (Note 4) b 24 b 48 mA ISINK Output Sink Current (N-Channel) VCC e 5V, VOUT e VCC TA e 25§ C (Note 4) 6 12 mA ISINK Output Sink Current (N-Channel) VCC e 10V, VOUT e VCC TA e 25§ C (Note 4) 24 48 mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. 2 AC Electrical Characteristics* MM54C373/MM74C373, TA e 25§ C, CL e 50 pF, tr e tf e 20 ns, unless otherwise noted Typ Max Units tpd0, tpd1 Symbol Propagation Delay, LATCH ENABLE to Output VCC VCC VCC VCC 5V, CL e 50 pF 10V, CL e 50 pF 5V, CL e 150 pF 10V, CL e 150 pF 165 70 195 85 330 140 390 170 ns ns ns ns tpd0, tpd1 Propagation Delay Data In to Output LATCH ENABLE e VCC VCC e 5V, CL e 50 pF VCC e 10V, CL e 50 pF VCC e 5V, CL e 150 pF VCC e 10V, CL e 150 pF 155 70 185 85 310 140 370 170 ns ns ns ns Minimum Set-Up Time Data In to CLOCK/LATCH ENABLE tHOLD e 0 ns VCC e 5V VCC e 10V 70 35 140 70 ns ns tSET-UP fMAX Parameter Maximum LATCH ENABLE Frequency Conditions e e e e VCC e 5V VCC e 10V Min 3.5 4.5 6.7 9.0 MHz MHz tPWH Minimum LATCH ENABLE Pulse Width VCC 5V VCC e 10V 75 55 tr, tf Maximum LATCH ENABLE Rise and Fall Time VCC e 5V VCC e 10V NA NA t1H, t0H Propagation Delay OUTPUT DISABLE to High Impedance State (from a Logic Level) RL e 10k, CL e 5 pF VCC e 5V VCC e 10V 105 60 210 120 ns ns Propagation Delay OUTPUT DISABLE to Logic Level (from High Impedance State) RL e 10k, CL e 50 pF VCC e 5V VCC e 10V 105 45 210 90 ns ns tTHL, tTLH Transition Time VCC VCC VCC VCC 65 35 110 70 130 70 220 140 ns ns ns ns CLE Input Capacitance LE Input (Note 2) 7.5 10 pF COD Input Capacitance OUTPUT DISABLE Input (Note 2) 7.5 10 pF CIN Input Capacitance Any Other Input (Note 2) 5 7.5 pF COUT Output Capacitance High Impedance State (Note 2) 10 15 pF CPD Power Dissipation Capacitance Per Package (Note 3) 200 tH1, tH0 e e e e 5V, CL e 50 pF 10V, CL e 50 pF 5V, CL e 150 pF 10V, CL e 150 pF *AC Parameters are guaranteed by DC correlated testing. 3 150 110 ns ns ms ms pF AC Electrical Characteristics* (Continued) MM54C374/MM74C374, TA e 25§ C, CL e 50 pF, tr e tf e 20 ns, unless otherwise noted Symbol Parameter Conditions Typ Max Units 150 65 180 80 300 130 360 160 ns ns ns ns tHOLD e 0 ns VCC e 5V VCC e 10V 70 35 140 70 ns ns Minimum CLOCK Pulse Width VCC e 5V VCC e 10V 70 50 140 100 ns ns fMAX Maximum CLOCK Frequency VCC e 5V VCC e 10V t1H, t0H Propagation Delay OUTPUT DISABLE to High Impedance State (from a Logic Level) RL e 10k, CL e 50 pF VCC e 5V VCC e 10V 105 60 210 120 ns ns Propagation Delay OUTPUT DISABLE to Logic Level (from High Impedance State) RL e 10k, CL e 50 pF VCC e 5V VCC e 10V 105 45 210 90 ns ns tTHL, tTLH Transition Time VCC VCC VCC VCC 65 35 110 70 130 70 220 140 ns ns ns ns tr, tf Maximum CLOCK Rise and Fall Time VCC e 5V VCC e 10V CCLK Input Capacitance CLOCK Input (Note 2) 7.5 10 pF COD Input Capacitance OUTPUT DISABLE Input (Note 2) 7.5 10 pF CIN Input Capacitance Any Other Input (Note 2) 5 7.5 pF COUT Output Capacitance High Impedance State (Note 2) 10 15 pF CPD Power Dissipation Capacitance Per Package (Note 3) 250 tpd0, tpd1 Propagation Delay, CLOCK to Output VCC VCC VCC VCC tSET-UP Minimum Set-Up Time Data In to CLOCK/LATCH ENABLE tPWH, tPWL tH1, tH0 e e e e e e e e Min 5V, CL e 50 pF 10V, CL e 50 pF 5V, CL e 150 pF 10V, CL e 150 pF 3.5 5 5V, CL e 50 pF 10V, CL e 50 pF 5V, CL e 150 pF 10V, CL e 150 pF 15 5 7.0 10 MHz MHz l 2000 ms ms l 2000 pF *AC Parameters are guaranteed by DC correlated testing. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application Note AN-90. Note 4: These are peak output current capabilities. Continuous output current is rated at 12 mA max. 4 Typical Performance Characteristics TA e 25§ C MM54C373/MM74C373 Propagation Delay, Data In to Output vs Load Capacitance MM54C373/MM74C373 Propagation Delay, LATCH ENABLE to Output vs Load Capacitance MM54C374/MM74C374 Propagation Delay, CLOCK to Output vs Load Capacitance TL/F/5906 – 3 MM54C373/MM74C373, MM54C374/MM74C374 Change in Propagation Delay per pF of Load Capacitance (DtPD/pF) vs Power Supply Voltage MM54C373/MM74C373, MM54C374/MM74C374 Output Sink Current vs VOUT MM54C373/MM74C373, MM54C374/MM74C374 Output Source Current vs VCC b VOUT TL/F/5906 – 4 Truth Table MM54C373/MM74C373 Output Disable LATCH ENABLE D L L L H H H L X H L X X MM54C374/MM74C374 Q H L Q Hi-Z Output Disable Clock L L L L H L L L H X D Q L e Low logic level H e High logic level 5 H L X X X H L Q Q Hi-Z X e Irrelevant L e Low to high logic level transition Q e Preexisting output level Hi-Z e High impedance output state Typical Applications Data Bus Interfacing Element Simple, Latching, Octal, LED Indicator Driver with Blanking for Use as Data Display, Bus Monitor, mP Front Panel Display, Etc. TL/F/5906–5 TL/F/5906 – 6 Logic Diagrams MM54C373/MM74C373 (1 of 8 Latches) TL/F/5906 – 7 MM54C374/MM74C374 (1 of 8 Flip-Flops) TL/F/5906 – 8 6 TRI-STATE Test Circuits and Switching Time Waveforms t1H, tH1 t1H, CL e 5 pF tH1, CL e 50 pF TL/F/5906 – 10 TL/F/5906–9 t0H, tH0 t0H, CL e 5 pF tH0, CL e 50 pF TL/F/5906 – 12 TL/F/5906–11 Switching Time Waveforms MM54C373/MM74C373 Output Disable e GND TL/F/5906 – 13 MM54C374/MM74C374 Output Disable e GND TL/F/5906 – 14 7 MM54C373/MM74C373 TRI-STATE Octal D-Type Latch MM54C374/MM74C374 TRI-STATE Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C373J, MM54C374J, MM74C373J or MM74C374J NS Package Number J20A Molded Dual-In-Line Package (N) Order Number MM54C373N, MM54C374N, MM74C373N or MM74C374N NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.