1W224B W224B 133-MHz Spread Spectrum FTG for Mobile Pentium III Platforms Features APIC, 48-MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter: ...................................................500 ps • Maximized EMI suppression using Cypress’s Spread Spectrum technology (–0.5% and –1.0%) • Single chip system FTG for Mobile Intel® Platforms • Three CPU outputs • Seven copies of PCI clock (one Free Running) • Seven SDRAM clock (one DCLK for Memory Hub) • Two copies of 48-MHz clock (non-spread spectrum) optimized for USB reference input and video DOT clock • Three 3V66 Hublink/AGP outputs • One VCH clock (48-MHz non-SSC or 66.67-MHz SSC) • Two APIC outputs • One buffered reference output • Supports frequencies up to 133 MHz • Supports 5% and 10% overclocking • SMBus interface for programming • Power management control inputs CPU Output Skew: ......................................................150 ps 3V66 Output Skew:......................................................175 ps APIC, SDRAM Output Skew:.......................................250 ps PCI Output Skew: ........................................................500 ps VDDQ3 (REF, PCI, 3V66, 48 MHz, SDRAM: ......... 3.3V ±5% VDDQ2 (CPU, APIC):............................................. 2.5V ±5% Table 1. Pin Selectable Functions TEST# FS1 FS0 CPU SDRAM 0 x 0 Three-state Three-state 0 x 1 Test Test 1 0 0 66 MHz 100 MHz 1 0 1 100 MHz 100 MHz Key Specifications 1 1 0 133 MHz 133 MHz CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps 1 1 1 133 MHz 100 MHz Block Diagram Pin Configuration VDD_REF XTAL OSC X1 X2 PLL 1 Divider Network REF PLL Ref Freq VDD_CPU CPU0 S top C lo ck C on trol FS0:1 CPU_F1:2 CPU_STP# VDD_SDRAM SDRAM0:5 VDD_APIC APIC0:1 PWR_DWN# VDD_PCI PCI_F S top C lo ck C on trol PCI1:6 PCI_STP# VDD_3V66 3V66_0:1 3V66_AGP VDD_48MHz PLL2 USB (48MHz) DOT (48MHz) SDATA SCLK SMBus Logic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 W 224B DCLK REF VDD_REF X1 X2 G ND_REF G ND_3V66 3V66_0 3V66_1 3V66_AG P VDD_3V66 P C I_ S T P # P C I_F P C I1 G N D _P C I P C I2 P C I3 V D D _P C I P C I4 P C I5 P C I6 G N D _P C I V D D _C O R E G N D _C O R E GND_48M Hz USB DOT VDD_48M Hz FS0 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 G N D _A P IC A P IC 0 A P IC 1 V D D _ A P IC CPU0 VDD_CPU CPU_F1 CPU_F2 G N D _C P U G N D _S D R A M SDRAM 0 SDRAM 1 VDD_SDRAM SDRAM 2 SDRAM 3 G N D _S D R A M SDRAM 4 SDRAM 5 DCLK VDD_SDRAM VCH_CLK VDD_VCH CPU_STP# TEST# PW R_DW N# SCLK S D ATA FS1 VCH_CLK Intel is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 June 12, 2001 W224B Pin Definitions Pin Type Pin Name Pin No. CPU0, CPU_F1:2 52, 50, 49 O CPU Clock Outputs: Frequency is set by the FS0:1 inputs or through serial input interface. The CPU0 output is gated by the CLK_STOP# input. 13, 15, 16, 18, 19, 20, 12 O 33MHz PCI Outputs: Except for the PCI_F output, these outputs are gated by the PCI_STOP# input. 55, 54 O APIC Output: 2.5V fixed 33.33-MHz clock. This output is synchronous to the CPU clock. SDRAM0:5, DCLK 46, 45, 43, 42, 40, 39, 38 O SDRAM Output Clocks: 3.3V outputs running at either 100 MHz or 133 MHz depending on the setting of FS0:1 inputs. DCLK is a free-running clock. 3V66_0:1, 3V66_AGP 7, 8, 9 O 66-MHz Clock Outputs: 3.3V fixed 66-MHz clock. USB 25 O USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock output. DOT 26 O Dot Clock Output: 3.3V fixed 48-MHz, non-spread spectrum signal. REF 1 O Reference Clock: 3.3V 14.318-MHz clock output. VCH_CLK 36 O Video Control Hub Clock Output: 3.3V selectable 48-MHz non-spread spectrum or 66.67-MHz spread spectrum clock output. PWR_DWN# 32 I Power Down Control: 3.3V LVTTL-compatible input that places the device in power-down mode when held LOW. CPU_STP# 34 I CPU Output Control: 3.3V LVTTL-compatible input that stops only the CPU0 clock. Output remains in the LOW state. PCI_STP# 11 I PCI Output Control: 3.3V LVTTL-compatible input that stops PCI1:6 clocks. Output remains in the LOW state. TEST# 33 I Test Mode Control: 3.3V LVTTL-compatible input to place the device into test mode. FS0:1 28, 29 I Frequency Selection Input: 3.3V LVTTL-compatible input used to select the CPU and SDRAM frequencies. See Frequency Table. SCLK 31 I SMBus Clock Input: Clock pin for SMBus circuitry. SDATA 30 I/O X1 3 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 4 O Crystal Connection: Connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. 2, 10, 17, 27, 35, 37, 44 P 3.3V Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. 51, 53 P 2.5V Power Connection: Power supply for APIC and CPU output buffers. Connect to 2.5V. 5, 6, 14, 21, 24, 41, 47, 48, 56 G Ground Connection: Connect all ground pins to the common system ground plane. PCI1:6, PCI_F APIC0:1 VDD_REF, VDD_3V66 VDD _PCI, VDD_48MHz, VDD_VCH, VDD_SDRAM, VDD_SDRAM VDD_APIC, VDD_CPU GND_REF, GND_3V66, GND_PCI, GND_PCI, GND_48MHz, GND_SDRAM. GND_SDRAM. GND_CPU, GND_APIC Pin Description SMBus Data Input: Data pin for SMBus circuitry. 2 W224B Pin Definitions Pin Name Pin No. Pin Type Pin Description VDD_CORE 22 P 3.3V Analog Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. GND_CORE 23 G Analog Ground Connection: Ground for core logic, PLL circuitry. Overview CPU/SDRAM Frequency Selection The W224 is a highly integrated frequency timing generator, supplying all the required clock sources for an Intel® architecture platform using graphics integrated core logic. CPU output frequency is selected through pins 28 and 29. For CPU/SDRAM frequency programming information, refer to Table 2 Alternatively, frequency selections are available through the serial data interface. . Table 2. Frequency Select Truth Table TEST# FS1 FS0 CPU SDRAM 3V66 PCI 48MHz 0 X 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 0 X 1 TCLK/2 TCLK/2 TCLK/3 TCLK/6 TCLK/2 TCLK TCLK/6 2, 3 1 0 0 66 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 33 MHz 4, 5, 6 1 0 1 100 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 33 MHz 4, 5, 6 1 1 0 133 MHz 133 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 33 MHz 4, 5, 6 1 1 1 133 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 33 MHz 4, 5, 6 Notes: 1. Provided for board-level “bed of nails” testing. 2. TCLK is a test clock overdriven on the XTAL_IN input during test mode. 3. Required for DC output impedance verification. 4. “Normal” mode of operation. 5. Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz. 6. Frequency accuracy of 48 MHz must be +167 PPM to match USB default. 3 REF APIC Notes W224B Offsets Among Clock Signal Groups spectively. It should be noted that when CPU clock is operating at 100 MHz, CPU clock output is 180 degrees out of phase with SDRAM clock outputs. Figure 1 and Figure 2 represent the phase relationship among the different groups of clock outputs from W224 when it is providing a 66-MHz CPU clock and a 100-MHz CPU clock, re0 ns 10 ns 20 ns 30 ns 40 ns Cycle Repeats C P U 66-M H z S D R AM 100-M H z 3V 66 66-M H z PC I 33-M H z AP IC 33-M H z R E F 14.318-M H z US B 48-M H z D O T 48-M H z Figure 1. Group Offset Waveforms (66 MHz CPU/100 MHz SDRAM Clock) Table 3. 66 MHz Group Timing Relationships and Tolerances CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI PCI to APIC USB & DOT Offset –2.5 ns 7.5 ns 0.0 ns 1.5–3.5 ns 0.0 ns Async Tolerance 500 ps 500 ps 500 ps 500 ps 1.0 ns N/A 0 ns 10 ns 20 ns 30 ns Cy cle Re peats CPU 100-MHz SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz APIC33-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz Figure 2. Group Offset Waveforms (100 MHz CPU/100 MHz SDRAM Clock) 4 40 ns W224B Table 4. 100 MHz Group Timing Relationships and Tolerances CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI PCI to APIC USB & DOT Offset 5.0 ns 5.0ns 0.0 ns 1.5–3.5 ns 0.0 ns Async Tolerance 500 ps 500 ps 500 ps 500 ps 1.0 ns N/A 0 ns 10 ns 20 ns 30 ns 40 ns C yc le Re pe ats CPU 133-MHz SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz APIC33-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz Figure 3. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM Clock) Table 5. 133 MHz/SDRAM 100 MHz Group Timing Relationships and Tolerances CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI PCI to APIC USB & DOT Offset 0.0 ns 0.0 ns 0.0 ns 1.5–3.5 ns 0.0 ns Async Tolerance 500 ps 500 ps 500 ps 500 ps 1.0 ns N/A Power-Down Control 0 ns 10 ns 20 ns 30 ns 40 ns C yc le Re pe ats CPU 133-MHz SDRAM 133-MHz 3V66 66-MHz PCI 33-MHz APIC33-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz Figure 4. Group Offset Waveforms (133-MHz CPU/133-MHz SDRAM Clock) 5 W224B Table 6. 133 MHz/SDRAM Test Mode Group Timing Relationships and Tolerance CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI PCI to APIC USB& DOT Offset 3.75 ns 0.0 ns 3.75 ns 1.5–3.5 ns 0.0 ns Async Tolerance 500 ps 500 ps 500 ps 500 ps 1.0 ns N/A W224 provides one PWR_DWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and all clock outputs are driven LOW. 0ns 25ns 50ns 75ns Center 1 2 VCO Internal CPU 100MHz 3V66 66MH z PCI 33MHz APIC 33MHz PwrDwn SDRAM 100MHz REF 14.318MHz USB 48MHz Figure 5. W224 PWR_DWN# Timing Diagram[7, 8, 9, 10] Table 7. W224 Maximum Allowed Current Max. 2.5V supply consumption Max. discrete cap loads, VDDQ2 = 2.625V All static inputs = VDDQ3 or VSS Max. 3.3V supply consumption Max. discrete cap loads VDDQ3 = 3.465V All static inputs = VDDQ3 or VSS Powerdown Mode (PWR_DWN# = 0) < 1 mA < 1 mA Full Active 66 MHz FS1:0 = 00 (PWR_DWN# =1) 60 mA 160 mA Full Active 100 MHz FS1:0 = 01 (PWR_DWN# =1) 75 mA 160 mA Full Active 133 MHz FS1:0 = 11 (PWR_DWN# =1) 90 mA 160 mA W224 Condition Notes: 7. Once the PWR_DWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition. 8. PWR_DWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W224. 9. The shaded sections on the SDRAM, REF, and USB clocks indicate “Don’t Care” states. 10. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz. 6 W224B Spread Spectrum Frequency Timing Generation Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 6. The output clock is modulated with a waveform depicted in Figure 7. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin, produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is –0.5% or –1.0% of the selected frequency. Figure 7 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. As shown in Figure 6, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: Spread Spectrum clocking is activated or deactivated by selecting the appropriate value for bit 3 in data byte 0 of the SMBus data stream. Refer to page 9 for more details. dB = 6.5 + 9*log10(P) + 9*log10(F) EMI Reduction Spread Spectrum Enabled NonSpread Spectrum Figure 6. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation M IN . Figure 7. Typical Modulation Profile 7 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY M AX. W224B 1 bit 7 bits 1 1 8 bits 1 Start bit Slave Address R/W Ack Command Code Ack Ack Data Byte 1 Ack Data Byte 2 Ack 1 bit 8 bits 1 8 bits 1 ... Byte Count = N Data Byte N Ack Stop 8 bits 1 1 Figure 8. An Example of a Block Write[11] Serial Data Interface the number 20 (14h), followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transfer a maximum of 32 data bytes. The slave receiver address for W224 is 11010010. Figure 8 shows an example of a block write. The W224 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The command code and the byte count bytes are required as the first two bytes of any transfer. W224 expects a command code of 0000 0000. The byte count byte is the number of additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. Table 8 shows an example of a possible byte count value. The clock driver serial protocol accepts only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. A block write begins with a slave address and a write condition. After the command code the core logic issues a byte count which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. Table 8. Example of Possible Byte Count Value Byte Count Byte Notes MSB LSB 0000 0000 Not allowed. Must have at least one byte. 0000 0001 Data for functional and frequency select register (currently byte 0 in spec) 0000 0010 Writes first two bytes of data (byte 0 then byte 1) 0000 0011 Writes first three bytes (byte 0, 1, 2 in order) 0000 0100 Writes first four bytes (byte 0, 1, 2, 3 in order) 0000 0101 Writes first five bytes (byte 0, 1, 2, 3, 4 in order) 0000 0110 Writes first six bytes (byte 0, 1, 2, 3, 4, 5 in order) 0000 0111 Writes first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order) 0010 0000 Max. byte count supported = 32 Note: 11. The acknowledgment bit is returned by the slave/receiver (W224). 8 W224B W224 Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: 2. All unused register bits (reserved and N/A) should be written to a “0” level. Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 3. All register bits labeled “Initialize to 0" must be written to zero during initialization. Failure to do so may result in higher than normal operating current. Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 0: Control Register (1 = Enable, 0 = Disable)[12] Bit Pin# Name Pin Description Bit 7 36 VCH (Disabled/Enabled) Bit 6 49 CPU_F2 (Disabled/Enabled) Bit 5 50 CPU_F1 (Disabled/Enabled) Bit 4 52 CPU0 (Disabled/Enabled) Bit 3 - Spread Spectrum (1 = On/0 = Off) (Active/Inactive) Bit 2 26 DOT (Disabled/Enabled) Bit 1 25 USB (Disabled/Enabled) Bit 0 -- Reserved Drive to ‘0’ (Active/Inactive) Byte 1: Control Register (1 = Enable, 0 = Disable)[12] Bit Pin# Name Pin Description Bit 7 -- Reserved Drive to ‘0’ (Active/Inactive) Bit 6 -- Reserved Drive to ‘0’ (Active/Inactive) Bit 5 39 SDRAM5 (Disabled/Enabled) Bit 4 40 SDRAM4 (Disabled/Enabled) Bit 3 42 SDRAM3 (Disabled/Enabled) Bit 2 43 SDRAM2 (Disabled/Enabled) Bit 1 45 SDRAM1 (Disabled/Enabled) Bit 0 46 SDRAM0 (Disabled/Enabled) Byte 2: Control Register (1 = Enable, 0 = Disable)[12] Bit Pin# Name Pin Description Bit 7 9 3V66_AGP (Disabled/Enabled) Bit 6 8 3V66_1 (Disabled/Enabled) Bit 5 7 3V66_0 (Disabled/Enabled) Bit 4 -- Reserved Drive to ‘0’ (Active/Inactive) Bit 3 -- Reserved Drive to ‘0’ (Active/Inactive) Bit 2 -- Reserved Drive to ‘0’ (Active/Inactive) Bit 1 -- Reserved Drive to ‘0’ (Active/Inactive) Bit 0 -- Reserved Drive to ‘0’ ((Active/Inactive) Note: 12. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 9 W224B Byte 3: Control Register (1 = Enable, 0 = Disable) Bit Pin# Bit 7 - Bit 6 Name Pin Description Reserved Drive to ’0’ (Active/Inactive) 20 PCI6 (Disabled/Enabled) Bit 5 19 PCI5 (Disabled/Enabled) Bit 4 18 PCI4 (Disabled/Enabled) Bit 3 16 PCI3 (Disabled/Enabled) Bit 2 15 PCI2 (Disabled/Enabled) Bit 1 13 PCI1 (Disabled/Enabled) Bit 0 -- SDRAM 133 MHz Mode Enable Default is Disabled = ‘0’, Enabled = ‘1’ (Active/Inactive) Byte 4: Control Register (1 = Enable, 0 = Disable) Bit Pin# Bit 7 36 Bit 6 Bit 5 Name Pin Description VCH_CLK SSC Mode Enable Default is Disabled = ‘0’ (Disabled/Enabled) - Reserved Drive to ’0’ (Active/Inactive) - Reserved Drive to ’0’ (Active/Inactive) Bit 4 - Reserved Drive to ’0’ (Active/Inactive) Bit 3 - Reserved Drive to ’0’ (Active/Inactive) Bit 2 - Reserved Drive to ’0’ (Active/Inactive) Reserved Drive to ’0’ (Active/Inactive) Reserved Drive to ’0’ (Active/Inactive) Bit 1 Bit 0 - Byte 5: Control Register (1 = Enable, 0 = Disable) Bit Pin# Name Pin Description Bit 7 - Reserved Drive to’0’ (Active/Inactive) Bit 6 - (Active/Inactive) Bit 5 - Spread Spectrum and Overclocking Mode Select. See Table 9 Bit 4 - Reserved Drive to ’0’ (Active/Inactive) Bit 3 - Reserved Drive to ’0’ (Active/Inactive) Bit 2 - Reserved Drive to ’0’ (Active/Inactive) Reserved Drive to’0’ (Active/Inactive) Reserved Drive to’0’ (Active/Inactive) Bit 1 Bit 0 - Byte 5 has been provided as an optional register to enable a greater degree of spread spectrum and overclocking performance for all PLL1 outputs. (CPU, SDRAM, DCLK, APIC, PCI, 3V66 and VCH_CLK) (Active/Inactive) programming both bits 5 and 6 to ‘1.’ The part will enter this mode irrespective of pin 33, TEST#. It is not necessary to access Byte 5 if these additional features are not implemented. All outputs will default to 0% overclocking upon power up, with either 0% or –0.5% spread spectrum. (Spread spectrum ON/OFF remains under Byte 0, bit 3 control). Note that 10% overclocking can only be enabled with Spread Spectrum turned OFF. By enabling Byte 5, (bits 5 and 6) spread spectrum can be increased to –1.0% and /or overclocking of either 5% or 10% can be enabled. Although the default values are ‘0’ for all bits, the part can be placed into either Three-State or Test Mode by 10 W224B Table 9. Spread Spectrum and Overclocking Mode Select[13] Byte 0 Bit 3 Spread Spectrum ON Spread Spectrum OFF Byte 5 SS% Overclock% Description and Comments Bit 5 Bit 6 0 0 –0.5% 0% No overclocking 0 1 –1.0% 0% No overclocking 1 0 –0.5% 5%[13] 1 1 –1.0% 5%[13] 0 0 - 0% 0 1 - 10%[13] 1 0 - 5%[13] 1 1 Three-state or Test Mode Mode determined by FS0 (see Table 1) Note: 13. Overclocking not tested; characterized at room temperature only. Base Frequency determined through hardware select pins, FS0 & FS1. 11 W224B DC Electrical Characteristics Absolute Maximum DC Power Supply Parameter Description Min. Max. Unit VDD3 3.3V Core Supply Voltage –0.5 4.6 V VDDQ2 2.5V I/O Supply Voltage –0.5 3.6 V VDDQ3 3.3V Supply Voltage –0.5 4.6 V TS Storage Temperature –65 150 °C Absolute Maximum DC I/O Min. Max. Unit Vih3 Parameter 3.3V Input High Voltage Description –0.5 4.6 V Vil3 3.3V Input Low Voltage –0.5 V ESD prot. Input ESD Protection 2000 V DC Operating Requirements Parameter Description Condition Min. Max. Unit VDD3 3.3V Core Supply Voltage 3.3V ±5% 3.135 3.465 V VDDQ3 3.3V I/O Supply Voltage 3.3V ±5% 3.135 3.465 V VDDQ2 2.5V I/O Supply Voltage 2.5V ±5% 2.375 2.625 V Vih3 3.3V Input High Voltage VDD3 2.0 VDD + 0.3 V Vil3 3.3V Input Low Voltage VSS – 0.3 0.8 V Iil Input Leakage Current[14] 0<Vin<VDD3 –5 +5 µA Voh2 2.5V Output High Voltage Ioh = (–1 mA) 2.0 Vol2 2.5V Output Low Voltage Iol = (1 mA) Voh3 3.3V Output High Voltage Ioh = (–1 mA) Vol3 3.3V Output Low Voltage Iol = (1 mA) VDD3 = 3.3V±5% VDDQ2 = 2.5V±5% V 0.4 V VDDQ3 = 3.3V±5% 2.4 V 0.4 V VDDQ3 = 3.3V±5% Vpoh3 PCI Bus Output High Voltage Ioh = (–1 mA) Vpol3 PCI Bus Output Low Voltage Iol = (1 mA) Cin Input Pin Capacitance Cxtal Xtal Pin Capacitance Cout Output Pin Capacitance Lpin Pin Inductance 2.4 0.55 12 V 5 pF 22.5 pF 6 pF 0 7 nH 0 70 °C 13.5 Ambient Temperature No Airflow Ta Note: 14. Input Leakage Current does not include inputs with pull-up or pull-down resistors. V W224B AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V ±5%, VDDQ2= 2.5V ±5% fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[15] AC Electrical Characteristics 66.6-MHz Host Parameter Description 100-MHz Host 133-MHz Host Min. Max. Min. Max. Min. Max. Unit 15.0 15.5 10.0 10.5 7.5 8.0 ns Notes TPeriod Host/CPUCLK Period THIGH Host/CPUCLK High Time 5.2 N/A 3.0 N/A 1.87 N/A ns 16 TLOW Host/CPUCLK Low Time 5.0 N/A 2.8 N/A 1.67 N/A ns 17 TRISE Host/CPUCLK Rise Time 0.4 1.6 0.4 1.6 0.4 1.6 ns 18 TFALL Host/CPUCLK Fall Time 0.4 1.6 0.4 1.6 0.4 1.6 ns 18 TPeriod SDRAM CLK Period (100-MHz) 10.0 10.5 10.0 10.5 10.0 10.5 ns 15 THIGH SDRAM CLK High Time (100-MHz) 3.0 N/A 3.0 N/A 3.0 N/A ns 16 TLOW SDRAM CLK Low Time (100-MHz) 2.8 N/A 2.8 N/A 2.8 N/A ns 17 TRISE SDRAM CLK Rise Time (100-MHz) 0.4 1.6 0.4 1.6 0.4 1.6 ns 18 TFALL SDRAM CLK Fall Time (100-MHz) 0.4 1.6 0.4 1.6 0.4 1.6 ns 18 TPeriod APIC 33-MHz CLK Period 30.0 N/A 30.0 N/A 30.0 N/A ns 15 THIGH APIC 33-MHz CLK High Time 12.0 N/A 12.0 N/A 12.0 N/A ns 16 TLOW APIC 33-MHz CLK Low Time 12.0 N/A 12.0 N/A 12.0 N/A ns 17 TRISE APIC CLK Rise Time 0.4 1.6 0.4 1.6 0.4 1.6 ns 18 TFALL APIC CLK Fall Time 0.4 1.6 0.4 1.6 0.4 1.6 ns 18 TPeriod 3V66 CLK Period 15.0 16.0 15.0 16.0 15.0 16.0 ns 15 THIGH 3V66 CLK High Time 5.25 N/A 5.25 N/A 5.25 N/A ns 16 TLOW 3V66 CLK Low Time 5.05 N/A 5.05 N/A 5.05 N/A ns 17 TRISE 3V66 CLK Rise Time 0.5 2.0 0.5 2.0 0.5 2.0 ns 18 TFALL 3V66 CLK Fall Time 0.5 2.0 0.5 2.0 0.5 2.0 ns 18 TPeriod PCI CLK Period 30.0 N/A 30.0 N/A 30.0 N/A 15 THIGH PCI CLK High Time 12.0 N/A 12.0 N/A 12.0 N/A 16 TLOW PCI CLK Low Time 12.0 N/A 12.0 N/A 12.0 N/A 17 TRISE PCI CLK Rise Time 0.5 2.0 0.5 2.0 0.5 2.0 18 TFALL PCI CLK Fall Time 0.5 2.0 0.5 2.0 0.5 2.0 18 tpZL, tpZH Output Enable Delay (All outputs) 1.0 10.0 1.0 10.0 1.0 10.0 ns tpLZ, tpZH Output Disable Delay (All outputs) 1.0 10.0 1.0 10.0 1.0 10.0 ns tstable All Clock Stabilization from Power-Up 3 ms 3 3 15 19 Notes: 15. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks. 16. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs. 17. TLOW is measured at 0.4V for all outputs. 18. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification for 2.5V outputs and VOL = 0.4V and VOH = 2.4V for 3.3V outputs. 19. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and operating within specification. 13 W224B Group Skew and Jitter Limits Output Group Pin-Pin Skew Max. Cycle-Cycle Jitter Duty Cycle Nom Vdd Skew, Jitter Measure Point CPU 150 ps 250 ps 45/55 2.5V 1.25V SDRAM 250 ps 250 ps 45/55 3.3V 1.5V APIC 250 ps 500 ps 45/55 2.5V 1.25V 48MHz N/A 500 ps 45/55 3.3V 1.5V 3V66 175 ps 500 ps 45/55 3.3V 1.5V PCI 500 ps 500 ps 45/55 3.3V 1.5V REF N/A 1000 ps 45/55 3.3V 1.5V VCH_CLK N/A 250 ps 45/55 3.3V 1.5V Output Buffer Test Point Test Load Clock Output Wave TPERIOD Duty Cycle THIGH 2.0 2.5V Clocking Interface 1.25 0.4 TLOW TRISE TFALL TPERIOD Duty Cycle THIGH 2.4 3.3V Clocking Interface 1.5 0.4 TLOW TRISE TFALL Figure 9. Output Buffer Ordering Information Ordering Code W224B Package Name H X Package Type 56-pin SSOP (7.5 mm) 56-pin TSSOP (6.1 mm) Document #: 38-00926-** 14 W224B Layout Example +2.5V Supply +3.3V Supply FB FB VD D Q 2 VD D Q 3 C4 G G G VD D Q3 10Ω C5 G G C6 10 µF G G C1 C3 1 2 3 4 5 6 7 8 9 G G V G G V G V G G G 10 V 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 G G V W 224B G 0.005 µF G V G G G G V G G V Core V G PLL2 G G 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 10 µF 0.005 µF G G C2 G G G G G FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) Ceramic Caps: C1, C3 & C5 = 10–22 µF G = VIA to GND plane layer C2 & C4 = 0.005 µF C6 = 0.1 µF V =VIA to respective supply plane layer Note: E ach sup ply pla ne or strip shou ld have a ferrite bead and capacitors 15 W224B Package Diagram 56-Pin Thin Shrink Small Outline Package (TSSOP, 6.1 mm) 4 1.00 B 0.00 DEEP 0.05 1.00 DIA. 3 2 C 1 1 2 3 H/2 E/2 1.00 E 0.20 H A-B D 0.20 C A-B D N N A C L H 8 7 D 4 SEE DETAIL "A" e/2 X 4 X END VIEW TOP VIEW b bbb M C A-B D BOTTOM VIEW 0.05 b C b1 A H C aaa 3 e A1 D ODD LEAD SIDES TOPVIEW 9 SEE DETAIL 'B' A2 X = A AND B X = A AND B EVEN LEAD SIDES TOPVIEW WITH PLATING C 8 SEATING PLANE c1 c 5 SIDE VIEW BASE METAL SECTION "C-C" SCALE: 120/1 (SEE NOTE 10) 0.25 PARTING LINE H C L SEATING PLANE 6 C (O )C DETAIL "B" PACKAGE OUTLINE, (SCALE: 30/1) DAMBAR PROTRUSION DETAIL 'A' 6.10mm BODY, TSSOP (SCALE: 30/1) THIS TABLE FOR 0.50mm PITCH S Y M B O L A A1 A2 aaa b b1 bbb c c1 D E e H L N C OC COMMON DIMENSIONS MIN. NOM. MAX. 0.05 0.80 1.00 0.10 0.17 0.20 0.17 0.08 0.09 0.09 0.127 SEE VARIATIONS 6.10 6.00 0.50 BSC 8.10 BSC 0.60 0.50 SEE VARIATIONS 0 N O T E 1.10 0.15 1.05 0.27 0.23 9 NOTE VARIATIONS ED EE EF* MIN. 5 D NOM. MAX. 12.40 13.90 16.90 12.50 14.00 17.00 12.60 14.10 17.10 *DESIGNED BUT NOT TOOLED 0.20 0.16 6.20 0.75 5 5 6 7 8 ALL DIMENSIONS IN MILLIMETERS NOTES: 7 N 48 56 64 1. DIE THICKNESS ALLOWABLE IS 0.2790.0127 (.0110DIE THICKNESS ALLOWABLE IS 0.279.0005 INCH 2. DIMENSIONING & TOLERANCES PER ASME. Y14.5M-1994. 3. DATUM PLANE H LOCATED AT MOLD PARTING LINE AND CONCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE. 4. DATUMS A-B AND D TO BE DETERMINED WHERE CENTERLINE BETWEEN LEADS EXITS PLASTIC BODY AT DATUM PLANE H. 5. "D" & "E" ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, AND ARE MEASURED AT THE BOTTOM PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15mm ON D AND 0.25mm ON E PER SIDE. 6. DIMENSION IS THE LENGTH OF TERMINAL FOR SOLDERING TO A SUBSTRATE. 7. TERMINAL POSITIONS ARE SHOWN FOR REFERENCE ONLY. 8. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.076mm AT SEATING PLANE. 9. THE LEAD WIDTH DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND AN ADJACENT LEAD TO BE 0.10MM FOR 0.65MM PITCH, 0.08MM FOR 0.50MM PITCH AND 0.07MM FOR 0.40MM PITCH PACKAGES. SEE DETAIL 'B' AND SECTION "C-C". 10. SECTION "C-C" TO BE DETERMINED AT 0.10 TO 0.25 MM FROM THE LEAD TIP. 11. CONTROLLING DIMENSION: MILLIMETERS. 12. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153, VARIATIONS DB, DC, DE, ED, EE, AND FE. 16 W224B Package Diagram 56-Pin Shrink Small Outline Package (SSOP, 7.5 mm) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.725 Body Height: 0.102 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.