HD151TS174 Mother Board Clock Generator for ALI M1651 Chip set with DDR SDRAM Clock ADE-205-568B (Z) Rev.2 Sep. 2002 Description The HD151TS174 is a high-performance, low-skew, low-jitter, PC mother board clock generator. It is specifically designed for ALI M1651 PII/PIII chip set use with DDR (Double Data Rate) synchronous DRAMs. Features • 7 differential pairs of memory clock for DDR SDRAM @2.5 V, up to 146.66 MHz • 2 copies of CPU clock @2.5 V, up to 146.66 MHz • 6 copies of PCI clock @3.3 V, 33.33 MHz • 2 copies of AGP clock @3.3 V, 66.66 MHz • 1 copy of 48 MHz @3.3 V • 1 copy of IOAPIC clock @2.5 V, 14.318 MHz • 1 copy of 14.318 MHz reference clock @3.3 V • IC 2 TM serial port programming • Spread spectrum modulation (–0.5%, ±0.25%) • 48pin SSOP (300 mils) • Can support with DDR clock buffer HD74CDCV857 2 Note: I C is a trademark of Philips Corporation. HD151TS174 Key Specifications • Supply voltages : VDD = 3.3 V±0.3 V, VDDL = 2.5 V±0.2 V • CPU & SDRAM clock cycle to cycle jitter = |250 ps| • CPU to CPU clock skew = 250 ps max • Mem to Mem clock skew = 250 ps max • AGP to AGP clock skew = 250 ps max • PCI to PCI clock skew = 500 ps max • CPU to Mem clock skew = 350 ps max • PCI to AGP clock skew = 350 ps max • Clock output duty cycle = 50±3% (CPU, Mem) • CPU (leads) to PCI offset = 1.0 ns Min, 2.0 ns Typ, 3.0 ns Max Rev.2, Sep. 2002, page 2 of 21 HD151TS174 Pin Arrangement 48 VDDL VDDL 1 IOAPIC 2 47 CPUCLK0 GND 3 46 CPUCLK1 X1 4 45 GND X2 5 44 SDRAMT0 VDD 6 43 SDRAMC0 *FS0/REF0 7 42 GND VDD 8 41 VDDL *FS1/AGP0 9 40 SDRAMT1 AGP1 10 39 SDRAMC1 GND 11 38 SDRAMT2 *FS2/PCICLK_F 12 37 SDRAMC2 PCICLK0 13 36 VDDL PCICLK1 14 35 GND PCICLK2 15 34 SDRAMT3 GND 16 33 SDRAMC3 VDD 17 32 SDRAMT4 *Mode/PCICLK3 18 31 SDRAMC4 30 GND PD#/PCICLK4 19 29 VDDL VDD 20 *FS3/48MHz 21 28 SDRAMT5 GND 22 27 SDRAMC5 SDATA 23 26 SDRAMT6 SCLK 24 25 SDRAMC6 (Top view) * Latch input / multi function pin. Rev.2, Sep. 2002, page 3 of 21 HD151TS174 Pin Descriptions Pin name No. GND 3, 11, 16, 22, Ground 30, 35, 42, 45 GND pins VDD 6, 8, 17, 20 Power Power supplies pins. Nominal 3.3 V. VDDL 1, 29, 36, 41, Power 48 Power supplies pins. Nominal 2.5 V. CPUCLK [1:0] 47, 46 Output CPU clock outputs. These pins are associated with 2.5 V VDDL. SDRAMT [0:6] 44, 40, 38, 34, Output 32, 28, 26 “True” clocks of differential pair SDRAM outputs. These pins are associated with 2.5 V VDDL. SDRAMC [0:6] 43, 39, 37, 33, Output 31, 27, 25 “Complementary” clocks of differential pair SDRAM outputs. These pins are associated with 2.5 V VDDL. IOAPIC 2 Output 2.5 V output. This IOAPIC out runs 14.318 MHz. PCICLK_F 12 Output Free running 3.3 V output. 2× strength output. Input Latch input multi function pin for frequency select. This pin is internal pull–up to VDD. Output 3.3 V PCI clock outputs. (*FS2) PCICLK [0:2] 13, 14, 15 PCICLK3 (*MODE) 18 PCICLK4/ PD# 19 REF0 (*FS0) 7 AGP0 (*FS1) 9 AGP1 10 48 MHz (*FS3) 21 X1 Type Description Output 3.3 V PCI clock outputs. Input Latch input multi function pin for PD# pin function. When MODE = 1, pin 19 will be PCICLK4 output. When MODE = 0, pin 19 will be PD# input pin. This pin is internal pull–up to VDD. Output/ Input 3.3 V PCI clock output or power down control input pin. The pin mode is determined by MODE setting pin 18. Output 14.318 MHz reference clock. Input Latch input multi function pin for frequency select. This pin is internal pull–up to VDD. Output AGP clock output. 2× PCI clock frequency. AGP0 may not be stopped. Input Latch input multi function pin for frequency select. This pin is internal pull–up to VDD. Output AGP clock output. 2× PCI clock frequency. AGP1 may not be stopped. Output 3.3 V 48 MHz output. Input Latch input multi function pin for frequency select. This pin is internal pull–up to VDD. 4 Input XTAL input. X2 5 Output XTAL output. SDATA 23 Input Data input for I2C logic. This pin is internal pull–up to VDD by 120 kΩ resistor. SCLK 24 Input Clock input for I2C logic. This pin is internal pull–up to VDD by 120 kΩ resistor. Note: 1. *FS[0:3] & MODE input logic levels are latched an internal power-on reset. Use 10 kΩ resistor to program logic high to VDD or GND for logic low. Rev.2, Sep. 2002, page 4 of 21 HD151TS174 Block Diagram 4× 3.3 V VDD 4× 2.5 V VDDL 8× GND 1× REF 3.3(14.318 MHz) 1× IOAPIC 2.5(14.318 MHz) XTAL 14.318 MHz XTAL OSC 7× Diff. SDRAMCLK 2.5 1/m1 Synthesizer 1/2 (CPU PLL) 2× CPUCLK 2.5 1/3, 1/4 1/n1 SSC Modulator PD# 1/3, 1/4 5× PCICLK 3.3 (33 MHz) *FS0, 1, 2, 3 SCLK *MODE 2× AGP 3.3 (66 MHz fixed) Mode Control Logic 1/m2 Synthesizer (48 MHz PLL) 1× PCICLK_F 3.3 (33 MHz) 1× 48 MHz 3.3 1/n2 Note: Latched input / Multi function pin. Rev.2, Sep. 2002, page 5 of 21 HD151TS174 Clock Frequency Function Table & I2C Byte0 (bit2, 4, 5, 6 &7) Bit2 Bit7 Bit6 Bit5 Bit4 FS3 FS2 FS1 FS0 CPU SDRAM PCICLK AGP Spread% 0 0 0 0 0 66.66 66.66 33.33 66.66 ±0.25% 0 0 0 0 1 66.66 100 33.33 66.66 ±0.25% 0 0 0 1 0 100 66.66 33.33 66.66 ±0.25% 0 0 0 1 1 100 100 33.33 66.66 ±0.25% 0 0 1 0 0 100 133.33 33.33 66.66 ±0.25% 0 0 1 0 1 133.33 66.66 33.33 66.66 ±0.25% 0 0 1 1 0 133.33 100 33.33 66.66 ±0.25% 0 0 1 1 1 133.33 133.33 33.33 66.66 ±0.25% 0 1 0 0 0 66.66 66.66 33.33 66.66 –0.50% 0 1 0 0 1 66.66 100 33.33 66.66 –0.50% 0 1 0 1 0 100 66.66 33.33 66.66 –0.50% 0 1 0 1 1 100 100 33.33 66.66 –0.50% 0 1 1 0 0 100 133.33 33.33 66.66 –0.50% 0 1 1 0 1 133.33 66.66 33.33 66.66 –0.50% 0 1 1 1 0 133.33 100 33.33 66.66 –0.50% 0 1 1 1 1 133.33 133.33 33.33 66.66 –0.50% 1 0 0 0 0 69.99 69.99 35 69.99 ±0.25% 1 0 0 0 1 69.99 105 35 69.99 ±0.25% 1 0 0 1 0 105 69.99 35 69.99 ±0.25% 1 0 0 1 1 105 105 35 69.99 ±0.25% 1 0 1 0 0 105 140 35 69.99 ±0.25% 1 0 1 0 1 140 69.99 35 69.99 ±0.25% 1 0 1 1 0 140 105 35 69.99 ±0.25% 1 0 1 1 1 140 140 35 69.99 ±0.25% 1 1 0 0 0 73.33 73.33 36.66 73.33 ±0.25% 1 1 0 0 1 73.33 110 36.66 73.33 ±0.25% 1 1 0 1 0 110 73.33 36.66 73.33 ±0.25% 1 1 0 1 1 110 110 36.66 73.33 ±0.25% 1 1 1 0 0 110 146.66 36.66 73.33 ±0.25% 1 1 1 0 1 146.66 73.33 36.66 73.33 ±0.25% 1 1 1 1 0 146.66 110 36.66 73.33 ±0.25% 1 1 1 1 1 146.66 146.66 36.66 73.33 ±0.25% Hardware latch inputs (FS0:3) can only access these frequency. Rev.2, Sep. 2002, page 6 of 21 HD151TS174 I2C Controlled Register Bit Map Byte0 CLK Frequency & SSC Control Register Bit Description Contents Default 7 CLK Freq. Control Bit (See Table 1) 1 6 CLK Freq. Control Bit (See Table 1) 1 5 CLK Freq. Control Bit (See Table 1) 1 4 CLK Freq. Control Bit (See Table 1) 1 3 SSC Enable Bit “0” = SSC OFF, “1” = SSC ON 0 2 CLK Freq. Control Bit (See Table 1) 0 1 SSC Modulation Rate Control Bit “0” = 33 kHz, “1” = 50 kHz 0 0 Freq. Select Mode Bit 0 = Freq. is selected by latched input FS0:3 2 1 = Freq. is selected by I C byte0 bit 2, 4–7 0 Contents Default Byte1 CPU Clock Outputs Control Register Bit Description 7 (Reserved Bit) 0 6 (Reserved Bit) 0 5 CPUCLK1 Enable / Disable 4 CPUCLK0 Enable / Disable 0 = Enable, 1 = Disable (DC low fixed) 0 3 REF0 Strength Control Bit “0” = X1, “1” = X2 0 2 (Reserved Bit) 0 1 (Reserved Bit) 0 0 (Reserved Bit) 0 0 = Enable, 1 = Disable (DC low fixed) 0 Byte2 PCI Clock Outputs Control Register Bit Description Contents Default 7 (Reserved Bit) 0 6 (Reserved Bit) 0 5 PCICLK_F Enable / Disable 0 = Enable, 1 = Disable (DC low fixed) 0 4 PCICLK4 Enable / Disable 0 = Enable, 1 = Disable (DC low fixed) 0 3 PCICLK3 Enable / Disable 0 = Enable, 1 = Disable (DC low fixed) 0 2 PCICLK2 Enable / Disable 0 = Enable, 1 = Disable (DC low fixed) 0 1 PCICLK1 Enable / Disable 0 = Enable, 1 = Disable (DC low fixed) 0 0 PCICLK0 Enable / Disable 0 = Enable, 1 = Disable (DC low fixed) 0 Rev.2, Sep. 2002, page 7 of 21 HD151TS174 I2C Controlled Register Bit Map (cont.) Byte3 SDRAM Clock Outputs Control Register Bit Description Contents Default 7 (Reserved Bit) 6 SDRAMT / C6 Enable / Disable 0 = Enable, 1 = Disable (Hi–Z) 0 0 5 SDRAMT / C5 Enable / Disable 0 = Enable, 1 = Disable (Hi–Z) 0 4 SDRAMT / C4 Enable / Disable 0 = Enable, 1 = Disable (Hi–Z) 0 3 SDRAMT / C3 Enable / Disable 0 = Enable, 1 = Disable (Hi–Z) 0 2 SDRAMT / C2 Enable / Disable 0 = Enable, 1 = Disable (Hi–Z) 0 1 SDRAMT / C1 Enable / Disable 0 = Enable, 1 = Disable (Hi–Z) 0 0 SDRAMT / C0 Enable / Disable 0 = Enable, 1 = Disable (Hi–Z) 0 Contents Default Byte4 Clock Outputs Control Register Bit Description 7 (Reserved Bit) 0 6 (Reserved Bit) 0 5 (Reserved Bit) 0 4 (Reserved Bit) 0 3 (Reserved Bit) 0 2 (Reserved Bit) 0 1 (Reserved Bit) 0 0 (Reserved Bit) 0 Byte5 Reserved Register Bit Description 7 (Reserved Bit) 0 6 (Reserved Bit) 0 5 (Reserved Bit) 0 4 (Reserved Bit) 0 3 (Reserved Bit) 0 2 (Reserved Bit) 0 1 (Reserved Bit) 0 0 (Reserved Bit) 0 Rev.2, Sep. 2002, page 8 of 21 Contents Default HD151TS174 I2C Controlled Register Bit Map (cont.) Byte6 Reserved Register Bit Description Contents Default 7 (Reserved Bit) 0 6 (Reserved Bit) 0 5 (Reserved Bit) 0 4 (Reserved Bit) 0 3 (Reserved Bit) 0 2 (Reserved Bit) 0 1 (Reserved Bit) 0 0 (Reserved Bit) 0 Rev.2, Sep. 2002, page 9 of 21 HD151TS174 I2C Serial Interface Operation 1. Write mode 1.1 Controller (host) sends a start bit. 1.2 Controller (host) sends the write address D2(h). 1.3 TS174 clock will acknowledge (TS174 sends “L”). 1.4 Controller (host) sends a dummy command code. 1.5 TS174 clock will acknowledge (TS174 sends “L”). 1.6 Controller (host) sends a dummy byte count. 1.7 TS174 clock will acknowledge (TS174 sends “L”). 1.8 Controller (host) starts sending first byte (Byte 0) through byte 6. 1.9 TS174 clock will acknowledge each byte one at a time. 1.10 Controller (host) sends a stop bit. 1 bit 7 bits Start bit 1 bit 1 bit 8 bits 1 bit Slave Dummy R/W Ack Ack address D2(h) command code 8 bits 1 bit 8 bits Dummy byte count Ack Byte 0 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits Ack Byte 1 Ack Byte 5 Ack Byte 6 Rev.2, Sep. 2002, page 10 of 21 1 bit 1 bit Ack Stop bit HD151TS174 I2C Serial Interface Operation (cont.) 2. Read mode 2.1 Controller (host) sends a start bit. 2.2 Controller (host) sends the read address D3 (h). 2.3 TS174 clock will acknowledge (TS174 sends “L”). 2.4 TS174 clock will send the byte count. (TS174 send “06(h)”). 2.5 Controller (host) acknowledges. 2.6 TS174 clock sends first byte (Byte 0) through byte 6. 2.7 Controller (host) will need to acknowledge each byte. 2.8 Controller (host) sends a stop bit. 1 bit 7 bits Start bit Slave R/W Ack address D3(h) 8 bits 1 bit 8 bits 1 bit 8 bits Byte count Ack Byte 0 Ack Byte 1 8 bits 1 bit 8 bits 1 bit Ack Byte 2 Ack Byte 6 Ack Stop bit 1 bit Notes: 1 bit 1 bit 1. 2. 3. 4. 5. 6. 1 bit 2 The TS174 clock generator is a slave / receiver, I C component. It can read back the data stored in the latches for the verification. The data transfer rate supported by this clock generator is 100 k bits / sec or less (standard mode). The input is operating at 3.3 V logic levels. The data byte format is 8 bit bytes. 2 To simplify the clock generator I C interface, the protocol is set to use only block–write from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The command code and byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a stop sequence is issued. At power–on, all registers are set to a default condition, as shown. Rev.2, Sep. 2002, page 11 of 21 HD151TS174 Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VDD –0.5 to 4.6 V VI –0.5 to 4.6 V VO –0.5 to VDD+0.5 V Input clamp current IIK –50 mA VI < 0 Output clamp current IOK –50 mA VO < 0 Continuous output current IO ±50 mA VO = 0 to VDD 0.7 W –65 to +150 °C Input voltage Output voltage *1 Maximum power dissipation at Ta = 55°C (in still air) Storage temperature Notes: Tstg Conditions Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Recommended Operating Conditions Item Symbol Min Typ Max Unit Conditions Supply voltage VDD 3.0 3.3 3.6 V VDDL 2.3 2.5 2.7 V –0.3 — VDD+0.3 V DC input signal voltage High level input voltage VIH 2.0 — VDD+0.3 V Low level input voltage VIL –0.3 — 0.8 V Operating temperature Ta 0 — 70 °C Rev.2, Sep. 2002, page 12 of 21 HD151TS174 DC Electrical Characteristics / Serial Input Port Ta = 0 to 70°C, VDD = 3.3 ± 0.3 V, VDDL = 2.5 ± 0.2 V Item Symbol Min Typ *1 Max Unit Test Conditions Input low voltage VIL — — 0.8 V Input high voltage VIH 2.0 — — V II –50 — +10 µA VI = 0 V or 3.6 V, VDD = 3.6 V CI — — 10 pF SDATA & SCLK Input current 1 Input capacitance * Notes: 1.Target of design, not 100% tested in production. AC Electrical Characteristics / Serial Input Port Item Symbol Min Typ Max Unit Test Conditions SCLK frequency FSCLK — — 100 kHz Start hold time tSTHD 4.0 — — µs SCLK low time tLOW 4.7 — — µs SCLK high time tHIGH 4.0 — — µs Data setup time tDSU 250 — — ns Data hold time tDHD 0 — — ns Rise time tr — — 1000 ns SDATA & SCLK, 0.8 V to 2.0 V Fall time tf — — 300 ns SDATA & SCLK, 2.0 V to 0.8 V Stop setup time tSTSU 4.0 — — µs BUS free time between stop & start condition tSPF 4.7 — — µs Note: Normal mode Target of design, not 100% tested in production. Rev.2, Sep. 2002, page 13 of 21 HD151TS174 DC Electrical Characteristics / SDRAM Clock Ta = 0 to 70°C, VDD = 3.3 V, VDDL = 2.3 V, CL = 21 pF Item Symbol Min Output voltage VOH VOL Differential cross point 1, 2 voltage * VOX Typ Max Unit V Test Conditions IOH = –100 µA, VDDL = 2.3 V VDD–0.2 — — 1.7 — — IOH = –12 mA, VDDL = 2.3 V — — 0.2 IOL = 100 µA, VDDL = 2.3 V — — 0.6 IOL = 12 mA, VDDL = 2.3 V 0.5×VDDL –0.2 — 0.5×VDDL V +0.2 Notes: 1. Differential cross point voltage is expected to track variation of VDDL and is the voltage at which the differential signals must be crossing. Vox is specified at SDRAM clock input. 2. Target of design, not 100% tested in production. AC Electrical Characteristics / SDRAM Clock Ta = 25°C, VDD = 3.3 V, VDDL = 2.5 V, CL = 21 pF Item Symbol Min Typ Max Unit Test Conditions Cycle to cycle jitter * tCCS –250 — 250 ps 133 MHz, Figure 1, 2 Output clock skew (SDRAM clock out to SDRAM clock out) tskD — — 250 ps Figure 1, 3 Slew rate tSL 1 1.0 — — V/ns 20% – 80%, Figure 1 Clock duty cycle 47 50 53 % Figure 1 CPU to SDRAM clock skew — — 350 ps Figure 1 Notes: Target of design, not 100% tested in production. 1. Difference of cycle time between two adjoining cycles. Rev.2, Sep. 2002, page 14 of 21 HD151TS174 DC Electrical Characteristics / CPU Clock Ta = 0 to 70°C, VDD = 3.3 V, VDDL = 2.5 V, CL = 20 pF Item Symbol Min Output voltage VOH 2.2 VOL — IOH IOL Output current Typ Max Unit Test Conditions — — V IOH = –1 mA, VDDL = 2.5 V — 50 mV IOL = 1 mA, VDDL = 2.5 V — — –19 mA VOH = 1.7 V, VDDL = 2.5 V 19 — — VOL = 0.70 V, VDDL = 2.5 V AC Electrical Characteristics / CPU Clock Ta = 25°C, VDD = 3.3 V, VDDL = 2.5 V, CL = 20 pF Item Symbol Min Typ Max Unit Test Conditions Cycle to cycle jitter * tCCS –250 — 250 ps 133 MHz, Figure 4 Output clock skew (CPU clock out to CPU clock out) tskS — — 250 ps Rising edge@ 1.25 V to 1.25 V, Figure 6 Slew rate tSL 1.0 — — V/ns 0.4 V to 2.0 V 1 Clock duty cycle 47 50 53 % CPU to SDRAM clock skew — — 350 ps CPU to AGP skew 1.0 2.0 3.0 ns CPU to PCI skew 1.0 2.0 3.0 ns Output impedance — 30 — Ω Notes: Target of design, not 100% tested in production. 1. Difference of cycle time between two adjoining cycles. Rev.2, Sep. 2002, page 15 of 21 HD151TS174 DC Electrical Characteristics / PCI Clock Ta = 0 to 70°C, VDD = 3.3 V, VDDL = 2.5 V, CL = 30 pF Item Symbol Min Output voltage VOH 3.1 VOL — IOH IOL Output current Typ Max Unit Test Conditions — — V IOH = –1 mA, VDD = 3.3 V — 50 mV IOL = 1 mA, VDD = 3.3 V — — –22 mA VOH = 2.0 V 25 — — VOL = 0.8 V AC Electrical Characteristics / PCI Clock Ta = 25°C, VDD = 3.3 V, VDDL = 2.5 V, CL = 30 pF Item Symbol Min Typ Max Unit Test Conditions Cycle to cycle jitter * tCCS –250 — 250 ps 33.3 MHz, Figure 4 Output clock skew (PCI clock out to PCI clock out) tskS — — 500 ps Rising edge @1. 5 V to 1.5 V, Figure 6 Slew rate tSL 1.0 — — V/ns 0.4 V to 2.4 V 1 Clock duty cycle 45 50 55 % PCI to AGP clock skew — — 350 ps Output impedance — 30 — Ω Notes: Target of design, not 100% tested in production. 1. Difference of cycle time between two adjoining cycles. Rev.2, Sep. 2002, page 16 of 21 HD151TS174 DC Electrical Characteristics / AGP Clock Ta = 0 to 70°C, VDD = 3.3 V, VDDL = 2.5 V, CL = 20 pF Item Symbol Min Output voltage VOH 3.1 VOL — IOH IOL Output current Typ Max Unit Test Conditions — — V IOH = –1 mA, VDD = 3.3 V — 50 mV IOL = 1 mA, VDD = 3.3 V — — –22 mA VOH = 2.0 V 25 — — VOL = 0.8 V AC Electrical Characteristics / AGP Clock Ta = 25°C, VDD = 3.3 V, VDDL = 2.5 V, CL = 20 pF Item Symbol Min Typ Max Unit Test Conditions Period jitter * tpre –500 — 500 ps 66.6 MHz, Figure 5 Output clock skew (AGP clock out to AGP clock out) tskS — — 250 ps Rising edge @1. 5 V to 1.5 V, Figure 6 Slew rate tSL 1.0 — — V/ns 0.4 V to 2.4 V 1 Clock duty cycle 45 50 55 % PCI to AGP clock skew — — 350 ps Output impedance — 30 — Ω Notes: Target of design, not 100% tested in production. 1. Difference of cycle time between two adjoining cycles. Rev.2, Sep. 2002, page 17 of 21 HD151TS174 DC Electrical Characteristics / 48 MHz & REF Clock Ta = 0 to 70°C, VDD = 3.3 V, VDDL = 2.5 V, CL = 20 pF Item Symbol Min Typ Output voltage VOH 3.1 VOL — IOH IOL Output current Max Unit Test Conditions — — V IOH = –1 mA, VDD = 3.3 V — 50 mV IOL = 1 mA, VDD = 3.3 V — — –22 mA VOH = 2.0 V 16 — — VOL = 0.8 V AC Electrical Characteristics / 48 MHz & REF Clock Ta = 25°C, VDD = 3.3 V, VDDL = 2.5 V, CL = 20 pF Item Symbol Min Typ Max Unit Test Conditions Period jitter * tpre –1.00 — 1.00 ns Slew rate tSL 0.5 — — V/ns 0.4 V to 2.4 V Clock duty cycle 45 50 55 % Output impedance — 40 — Ω 1 48 MHz, Figure 5 Notes: Target of design, not 100% tested in production. 1. Difference of cycle time between two adjoining cycles. Zo = 60 Ω SDRAMT *1 RT = 120 Ω C = 21 pF Zo = 60 Ω SDRAMC *1 C = 21 pF Note: 1. SDRAM Cin 3.5 pF ×6 Figure 1 SDRAM clock outputs test circuit SDRAMT SDRAMC tcycle n tcycle n+1 t CCD = (tcycle n) - (tcycle n+1) Figure 2 Cycle to cycle jitter (Differential memory clock) Rev.2, Sep. 2002, page 18 of 21 HD151TS174 SDRAMTx SDRAMCx SDRAMTy SDRAMCy tskD Figure 3 Output clock skew (Differential memory clock) Clock Out tcycle n tcycle n+1 t CCS = (tcycle n) - (tcycle n+1) Figure 4 Cycle to cycle jitter (Single ended clock output) Clock Out tperiod n tperiod n+1 tper = (period maximum deviation) - (mean clock period) Figure 5 Period jitter (Single ended clock output) Clock Outx Clock Outy 1.5 V 1.5 V tskS Figure 6 Output clock skew (Single ended clock output) Rev.2, Sep. 2002, page 19 of 21 HD151TS174 Package Dimensions Unit: mm 15.85 ± 0.3 25 1 24 0.635 0.25 ± 0.1 Rev.2, Sep. 2002, page 20 of 21 0.15 0.13 M 0.10 Min 0.78 Max 0.15 ± 0.05 2.65 Max 7.50 ± 0.3 48 10.40 ± 0.4 1.45 0˚ - 10˚ 0.60 ± 0.2 HD151TS174 Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Sales Offices Hitachi, Ltd. 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(Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan. Colophon 6.0 Rev.2, Sep. 2002, page 21 of 21