ETC WF128K32

WF128K32-XXX5
128KX 32 5V FL ASH MODULE, SMD 5962-94716
FEATURES
n Access Times of 50*, 60, 70, 90, 120, 150ns
n 5 Volt Programming. 5V ± 10% Supply
n
Packaging:
n Low Power CMOS, 1mA Standby Typical
•66 pin, PGA Type, 1.075 inch square, Hermetic
Ceramic HIP (Package 400)
n Embedded Erase and Program Algorithms
•68 lead, Hermetic CQFP (G2U)1, 22.4mm (0.880 inch)
square, 3.56mm (0.140 inch) high (Package 510)
n Built-in Decoupling Caps and Multiple Ground Pins for
•68 lead, Hermetic CQFP (G1U), 23.9mm (0.940 inch)
square, 3.56mm (0.140 inch) high (Package 519)
n
Page Program Operation and Internal Program Control
Time
•68 lead, Hermetic CQFP (G1T), 23.9mm (0.940 inch)
square, 4.06mm (0.160 inch) high (Package 524)
n
Weight
n TTL Compatible Inputs and CMOS Outputs
Low Noise Operation
WF128K32-XG1UX5 - 5 grams typical
n Sector Architecture
WF128K32-XG1TX5 - 5 grams typical
•8 equal size sectors of 16KBytes each
WF128K32-XG2UX51 - 8 grams typical
•Any combination of sectors can be concurrently
erased.
Also supports full chip erase
WF128K32-XH1X5 - 13 grams typical
Note 1: Package Not Recommended For New Design
Note: For programming information refer to Flash Programming 1M5
Application Note.
* The access time of 50ns is available in Industrial and Commercial temperature
ranges only.
n 100,000 Erase/Program Cycles Typical, 0°C to +70°C
n Organized as 128Kx32
n Commercial, Industrial and Military Temperature Ranges
FIG. 1
PIN CONFIGURATION FOR WF128K32N-XH1X5
TOP VIEW
PIN DESCRIPTION
I/O 0-31
Data Inputs/Outputs
A 0-16
Address Inputs
WE 1-4
Write Enables
CS1-4
Chip Selects
OE
Output Enable
VCC
Power Supply
GND
Ground
NC
Not Connected
BLOCK DIAGRAM
December 2001 Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
PIN CONFIGURATION FOR WF128K32-XG1UX5, WF128K32-XG1TX5 AND
WF128K32-XG2UX51
FIG. 3
PIN DESCRIPTION
NC
A0
A1
A2
A3
A4
A5
CS3
GND
CS4
WE1
A6
A7
A8
A9
A10
VCC
TOP VIEW
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O 0-31
Data Inputs/Outputs
A 0-16
Address Inputs
WE 1-4
Write Enables
CS1-4
Chip Selects
OE
Output Enable
VCC
Power Supply
GND
Ground
NC
Not Connected
BLOCK DIAGRAM
E4
NC
NC
NC
E3
A16
CS1
OE
CS2
NC
E2
A15
A14
A13
A12
A11
VCC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Note 1: Package Not Recommended For New Design
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2
WF128K32-XXX5
ABSOLUTE MAXIMUM RATINGS (1)
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Max
Unit
Operating Temperature
-55 to +125
°C
Supply Voltage
V CC
4.5
5.5
V
Supply Voltage Range (VCC)
-2.0 to +7.0
V
Input High Voltage
VIH
2.0
V CC + 0.3
V
Signal voltage range (any pin except A9) (2)
-2.0 to +7.0
V
Input Low Voltage
VIL
-0.5
+0.8
V
Storage Temperature Range
-65 to +150
°C
Operating Temp. (Mil.)
TA
-55
+125
°C
+300
°C
A9 Voltage for Sector Protect
VID
11.5
12.5
V
Parameter
Parameter
Unit
Lead Temperature (soldering, 10 seconds)
Data Retention Mil Temp
10 years
Endurance (write/erase cycles) Mil Temp
CAPACITANCE
10,000 cycles min.
A9 Voltage for sector protect (VID) (3)
-2.0 to +14.0
(TA = +25ºC)
V
NOTES:
Parameter
1. Stresses above the absolute maximum rating may cause permanent damage to
the device. Extended operation at the maximum levels may degrade
performance and affect reliability.
2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions,
inputs may overshoot Vss to -2.0 V for periods of up to 20ns. Maximum DC
voltage on output and I/O pins is Vcc + 0.5V. During voltage transitions, outputs
may overshoot to Vcc + 2.0 V for periods of up to 20ns.
3. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9
may overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage
on A9 is +13.5V which may overshoot to 14.0 V for periods up to 20ns.
Symbol
Conditions
OE capacitance
COE
VIN = 0 V, f = 1.0 MHz
WE1-4 capacitance
HIP (PGA)
CQFP G2U/G1U/G1T
CWE
VIN = 0 V, f = 1.0 MHz
Max
50
Unit
pF
pF
20
15
CS1-4 capacitance
CCS
VIN = 0 V, f = 1.0 MHz
20
pF
Data I/O capacitance
CI/O
VI/O = 0 V, f = 1.0 MHz
20
pF
Address input capacitance
CAD
VIN = 0 V, f = 1.0 MHz
50
pF
This parameter is guaranteed by design but not tested.
DC CHAR ACTERISTICS - CMOS COMPATIBLE
(V CC = 5.0V, VSS = 0V, T A = -55°C TO +125°C)
Parameter
Symbol
Conditions
Unit
Min
Input Leakage Current
Output Leakage Current
Max
I LI
VCC = 5.5, VIN = GND to VCC
10
I LOx32
VCC = 5.5, VIN = GND to VCC
10
µA
µA
VCC Active Current for Read (1)
I CC1
CS = VIL, OE = VIH
140
mA
VCC Active Current for Program
or Erase (2)
I CC2
CS = VIL, OE = VIH
200
mA
VCC Standby Current
I CC3
VCC = 5.5, CS = VIH, f = 5MHz
6.5
mA
VCC Static Current
I CC4
VCC = 5.5, CS = VIH
0.6
mA
Output Low Voltage
VOL
IOL = 8.0 mA, VCC = 4.5
0.45
V
Output High Voltage
VOH1
IOH = -2.5 mA, VCC = 4.5
0.85 x
VCC
V
Output High Voltage
VOH2
IOH = -100 µA, VCC = 4.5
VCC
-0.4
V
Low VCC Lock Out Voltage
VLKO
3.2
V
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
3
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WF128K32-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED
(VCC = 5.0V, VSS = 0V, TA = -55°C TO+125°C)
Parameter
Symbol
-50
Min
-60
Max
Min
-70
Max
Min
-90
Max
Min
-120
Max
Min
-150
Max
Min
Unit
Max
Write Cycle Time
t AVAV
t WC
50
60
70
90
120
150
ns
WE Setup Time
tWLEL
tWS
0
0
0
0
0
0
ns
CS Pulse Width
t ELEH
t CP
25
30
35
45
50
50
ns
Address Setup Time
t AVEL
t AS
0
0
0
0
0
0
ns
Data Setup Time
t DVEH
tDS
25
30
30
45
50
50
ns
Data Hold Time
t EHDX
tDH
0
0
0
0
0
0
ns
Address Hold Time
tELAX
t AH
40
45
45
45
50
50
ns
WE Hold from WE High
t EHWH
t WH
0
0
0
0
0
0
ns
CS Pulse Width High
tEHEL
tCPH
20
20
20
20
20
20
ns
Duration of Programming Operation
t WHWH1
14
Duration of Erase Operation
t WHWH2
2.2
t GHEL
0
Read Recovery before Write
Chip Programming Time
14
60
2.2
14
60
0
12.5
14
2.2
60
0
12.5
2.2
14
60
0
12.5
FIG. 4 AC T EST C IRCUIT
2.2
14
60
0
12.5
2.2
µs
60
sec
0
12.5
ns
12.5
sec
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 ý.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
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4
WF128K32-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED
(V CC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
Parameter
Symbol
-50
Min
-60
Max
Min
-70
Max
Min
-90
Max
Min
-120
Max
Min
-150
Max
Min
Unit
Max
Write Cycle Time
t AVAV
t WC
50
60
70
90
120
150
ns
Chip Select Setup Time
tELWL
tCS
0
0
0
0
0
0
ns
Write Enable Pulse Width
t WLWH
t WP
25
30
35
45
50
50
ns
Address Setup Time
tAVWL
t AS
0
0
0
0
0
0
ns
Data Setup Time
t DVWH
tDS
25
30
30
45
50
50
ns
Data Hold Time
t WHDX
tDH
0
0
0
0
0
0
ns
Address Hold Time
tWLAX
t AH
40
45
45
45
50
50
ns
Chip Select Hold Time
t WHEH
tCH
0
0
0
0
0
0
ns
Write Enable Pulse Width High
t WHWL
t WPH
20
20
20
20
20
20
ns
Duration of Byte Programming Operation (min)
t WHWH1
14
14
14
14
14
14
µs
Sector Erase Time
t WHWH2
2.2
t GHWL
0
Read Recovery Time Before Write
VCC Setup Time
tVCS
60
2.2
60
0
50
60
0
50
Chip Programming Time
2.2
60
0
50
12.5
2.2
12.5
2.2
60
0
50
60
0
50
12.5
2.2
ns
50
12.5
sec
µs
12.5
12.5
sec
Output Enable Setup Time
tOES
0
0
0
0
0
0
ns
Output Enable Hold Time (1)
1. For Toggle and Data Polling.
tOEH
10
10
10
10
10
10
ns
AC CHARACTERISTICS – READ ONLY OPERATIONS
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
Parameter
Symbol
-50
Min
-60
Max
Min
Read Cycle Time
t AVAV
t RC
Address Access Time
t AVQV
t ACC
50
Chip Select Access Time
t ELQV
t CE
50
60
OE to Output Valid
t GLQV
tOE
25
30
Chip Select to Output High Z (1)
t EHQZ
t DF
20
20
OE High to Output High Z (1)
t GHQZ
t DF
20
20
t AXQX
tOH
Output Hold from Address, CS or OE Change,
whichever is first
1. Guaranteed by design, not tested.
50
-70
Max
60
Min
70
60
0
0
5
-90
Max
Min
90
70
0
-120
Max
Min
-150
Max
120
Min
Unit
Max
150
ns
90
120
150
ns
70
90
120
150
ns
35
40
50
55
ns
20
25
30
35
ns
20
25
30
35
ns
0
0
0
ns
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WF128K32-XXX5
FIG. 5 AC WAVEFORMS FOR READ OPERATIONS
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6
WF128K32-XXX5
FIG. 6 WRITE/ERASE/PROGRAM OPERATION, WE CONTROLLED
:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to the device (for each chip).
4. DOUT is the output of the data written to the device.
5.Figure indicates last two bus cycles of four bus cycle sequence.
NOTES
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
FIG. 7 AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
Notes:
1. SA is the sector address for Sector Erase.
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8
WF128K32-XXX5
FIG. 8
AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS
9
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WF128K32-XXX5
FIG. 9 WRITE/ERASE/PROGRAM OPERATION, CS CONTROLLED
NOTES:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to the device (for each chip).
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
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WF128K32-XXX5
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
27.3 (1.075) ± 0.25 (0.010) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
4.34 (0.171)
MAX
3.81 (0.150)
± 0.13 (0.005)
1.42 (0.056) ± 0.13 (0.005)
0.76 (0.030) ± 0.13 (0.005)
2.54 (0.100)
TYP
15.24 (0.600) TYP
1.27 (0.050) TYP DIA
0.46 (0.018) ± 0.05 (0.002) DIA
25.4 (1.0) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
PACKAGE 510:
68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)1
The White 68 lead G2U CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2U has the
TCE and lead inspection
advantage of the CQFP form.
0.940"
TYP
Note 1: Package Not Recommended For New Design
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
12
WF128K32-XXX5
PACKAGE 519:
68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G1U)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
13
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
PACKAGE 524:
68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G1T)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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14
WF128K32-XXX5
ORDERING INFORMATION
W F 128K32 X - XXX X X 5 X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
VPP PROGRAMMING VOLTAGE
5 = 5V
DEVICE GRADE:
Q = MIL - STD 833 Compliant
M = Military Screened -55°C to +125°C
I = Industrial
-40°C to +85°C
C = Commercial
0°C to + 70°C
PACKAGE TYPE:
H1 = 1.075" sq. Ceramic Hex In-line Package, HIP (Package 400)
G2U1 = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 510)
G1U = 23.9mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 519)
G1T = 23.9mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 524)
ACCESS TIME (ns)
IMPROVEMENT MARK
N = No Connect at pin 8, 21, 28 and 39 in HIP for Upgrade
ORGANIZATION, 128K x 32
User configurable as 256K x 16 or 512K x 8
Flash
WHITE ELECTRONIC DESIGNS CORP.
Note 1: Package Not Recommended For New Design
15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
DEVICE TYPE
SPEED
PACKAGE
SMD NO.
128K x 32 Flash
150ns
66 pin HIP (H1)
5962-94716 01H8X
128K x 32 Flash
120ns
66 pin HIP (H1)
5962-94716 02H8X
128K x 32 Flash
90ns
66 pin HIP (H1)
5962-94716 03H8X
128K x 32 Flash
70ns
66 pin HIP (H1)
5962-94716 04H8X
128K x 32 Flash
60ns
66 pin HIP (H1)
5962-94716 05H8X
128K x 32 Flash
150ns
68 lead CQFP (G1U)
5962-94716 01H9X
128K x 32 Flash
120ns
68 lead CQFP (G1U)
5962-94716 02H9X
128K x 32 Flash
90ns
68 lead CQFP (G1U)
5962-94716 03H9X
128K x 32 Flash
70ns
68 lead CQFP (G1U)
5962-94716 04H9X
128K x 32 Flash
60ns
68 lead CQFP (G1U)
5962-94716 05H9X
128K x 32 Flash
150ns
68 lead CQFP (G2U)1
5962-94716 01HNX 1
128K x 32 Flash
120ns
68 lead CQFP (G2U)
1
5962-94716 02HNX 1
128K x 32 Flash
90ns
68 lead CQFP (G2U)
1
5962-94716 03HNX 1
128K x 32 Flash
70ns
68 lead CQFP (G2U)1
5962-94716 04HNX 1
128K x 32 Flash
60ns
68 lead CQFP (G2U)1
5962-94716 05HNX 1
Note 1: Package Not Recommended For New Design
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16