WSF2816-39XX 128KX16 SRAM/512KX16 FLASH MODULE FEATURES ■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation ■ Access Times of 35ns (SRAM) and 90ns (FLASH) ■ Weight: WSF2816-39G2UX - 8 grams typical WSF2816-39H1X - 13 grams typical ■ Packaging • 66 pin, PGA Type, 1.075" square HIP, Hermetic Ceramic HIP (Package 400) FLASH MEMORY FEATURES • 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880") square (Package 510) 3.56mm (0.140") height. Designed to fit JEDEC 68 lead 0.990” CQFJ footprint (Fig. 2) ■ 100,000 Erase/Program Cycles ■ Sector Architecture ■ 128Kx16 SRAM • 8 equal size sectors of 64K bytes each ■ 512Kx16 5V FLASH • Any combination of sectors can be concurrently erased. Also supports full chip erase ■ Organized as 128Kx16 of SRAM and 512Kx16 of Flash Memory with separate Data Buses ■ 5 Volt Programming; 5V ± 10% Supply ■ Both blocks of memory are User Configurable as 256Kx8 ■ Embedded Erase and Program Algorithms ■ Low Power CMOS ■ Hardware Write Protection ■ Commercial, Industrial and Military Temperature Ranges Note: For programming information refer to Flash Programming 4M5 Application Note. ■ TTL Compatible Inputs and Outputs FIG. 1 PIN CONFIGURATION FOR WSF2816-39H1X PIN DESCRIPTION TOP VIEW 1 12 23 34 45 FD0-15 Flash Data Inputs/Outputs 56 SD8 SWE2 SD15 FD8 VCC FD15 SD9 SCS2 SD14 FD9 FCS2 FD14 SD0-15 SRAM Data Inputs/Outputs A0-18 Address Inputs SWE1-2 SRAM Write Enable SD10 GND SD13 FD10 FWE2 FD13 SCS1-2 SRAM Chip Selects A13 SD11 SD12 A6 FD11 FD12 OE Output Enable A14 A10 OE A7 A3 A0 VCC Power Supply GND Ground NC A4 A1 SWE1 A8 A5 A2 VCC SD7 A9 FWE1 FD7 SD0 SCS1 SD6 FD0 FCS1 FD6 SD1 NC SD5 FD1 GND FD5 SD2 SD3 SD4 FD2 FD3 FD4 A15 A11 A17 A16 A12 A18 NC Not Connected FWE1-2 Flash Write Enable FCS1-2 Flash Chip Select BLOCK DIAGRAM 11 22 November 2003 Rev. 5 33 44 55 66 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WSF2816-39XX FIG. 2 PIN CONFIGURATION FOR WSF2816-39G2UX PIN DESCRIPTION TOP VIEW FD0-15 Flash Data Inputs/Outputs SD0-15 SRAM Data Inputs/Outputs A0-18 The White 68 lead G2U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form. Address Inputs SWE1-2 SRAM Write Enable SCS1-2 SRAM Chip Selects OE Output Enable VCC Power Supply GND Ground NC Not Connected FWE1-2 Flash Write Enable FCS1-2 Flash Chip Select BLOCK DIAGRAM White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 2 WSF2816-39XX ABSOLUTE MAXIMUM RATINGS Parameter SRAM TRUTH TABLE Symbol Min Max Unit TA -55 +125 °C °C Operating Temperature Storage Temperature TSTG -65 +150 Signal Voltage Relative to GND VG -0.5 7.0 V Junction Temperature TJ 150 °C 7.0 V Supply Voltage VCC -0.5 SCS H L L L OE X L H X SWE X H H L 20 years Flash Endurance (write/erase cycles) 100,000 Test NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. RECOMMENDED OPERATING CONDITIONS Parameter Data I/O High Z Data Out High Z Data In Power Standby Active Active Active CAPACITANCE (TA = +25°C) Parameter Flash Data Retention Mode Standby Read Read Write Symbol Min Max Unit Supply Voltage V CC 4.5 5.5 V Input High Voltage V IH 2.2 V CC + 0.3 V Input Low Voltage V IL -0.5 +0.8 V Symbol Condition Max Unit OE Capacitance C OE V IN = 0V, f = 1.0MHz 50 pF WE Capacitance C WE V IN = 0V, f = 1.0MHz 20 pF CS Capacitance C CS V IN = 0V, f = 1.0MHz 20 pF Data I/O Capacitance CI/ O V IN = 0V, f = 1.0MHz 20 pF Address Line Capacitance C AD V IN = 0V, f = 1.0MHz 50 pF This parameter is guaranteed by design but not tested. DC CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Max Unit Input Leakage Current I LI V CC = 5.5, V IN = GND to V CC 10 µA Output Leakage Current I LO SCS = VIH, OE = VIH, VOUT = GND to V CC 10 µA ICCx16 SCS = VIL, OE = FCS = VIH, f = 5MHz, V CC = 5.5 325 mA Standby Current I SB FCS = SCS = VIH, OE = VIH, f = 5MHz, V CC = 5.5 20 mA SRAM Output Low Voltage V OL I OL = 8.0mA, V CC = 4.5 0.4 V SRAM Output High Voltage V OH I OH = -4.0mA, V CC = 4.5 Flash V CC Active Current for Read (1) I CC1 FCS = VIL, OE = SCS = V IH 120 mA Flash V CC Active Current for Program or Erase (2) I CC2 FCS = VIL, OE = SCS = V IH 140 mA Flash Output Low Voltage V OL I OL = 8.0mA, V CC = 4.5 Flash Output High Voltage V OH1 I OH = -2.5 mA, V CC = 4.5 0.85 x V CC V Flash Output High Voltage V OH2 I OH = -100 µA, V CC = 4.5 V CC -0.4 V Flash Low V CC Lock Out Voltage V LKO 3.2 V SRAM Operating Supply Current x 16 Mode Symbol Conditions Min 2.4 V 0.45 V NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH . 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = V CC - 0.3V 3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WSF2816-39XX SRAM AC CHARACTERISTICS (VCC = 5.0V, TA = -55°C to +125°C) Parameter Read Cycle Symbol -35 Min Read Cycle Time t RC Address Access Time tAA Output Hold from Address Change t OH Chip Select Access Time t ACS Output Enable to Output Valid t OE Chip Select to Output in Low Z t CLZ 1 Output Enable to Output in Low Z t OLZ 1 Chip Disable to Output in High Z t CHZ 1 Output Disable to Output in High Z t OHZ 1 SRAM AC CHARACTERISTICS (VCC = 5.0V, TA = -55°C to +125°C) Parameter Write Cycle Unit Max Symbol -35 Min Unit Max ns Write Cycle Time t WC 35 ns ns Chip Select to End of Write tCW 25 ns ns Address Valid to End of Write t AW 25 ns 35 ns Data Valid to End of Write t DW 20 ns 20 ns Write Pulse Width t WP 25 ns 3 ns Address Setup Time t AS 0 ns 0 ns Address Hold Time t AH 0 ns 20 ns Output Active from End of Write t OW 1 4 20 ns Write Enable to Output in High Z t WHZ 1 35 35 0 Data Hold from Write Time 1. This parameter is guaranteed by design but not tested. ns 20 ns 0 t DH ns 1. This parameter is guaranteed by design but not tested. FIG. 3 AC TEST CONDITIONS AC TEST CIRCUIT PARAMETER ˜ TYP UNIT Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 4 WSF2816-39XX FIG. 4 SRAM tRC TIMING WAVEFORM - READ CYCLE ADDRESS tAA SCS tRC tCHZ tACS ADDRESS tCLZ tAA SOE tOE tOLZ tOH DATA I/O DATA I/O DATA VALID PREVIOUS DATA VALID tOHZ DATA VALID HIGH IMPEDANCE READ CYCLE 2, (SWE = VIH) READ CYCLE 1, (SCS = OE = VIL, SWE = VIH) FIG. 5 SRAM WRITE CYCLE - SWE CONTROLLED tWC ADDRESS tAW tAH tCW SCS tAS tWP SWE tOW tWHZ tDW DATA I/O tDH DATA VALID WRITE CYCLE 1, SWE CONTROLLED FIG. 6 SRAM WRITE CYCLE - SCS CONTROLLED tCW WS32K32-XHX ADDRESS tAS tWA tAH tCW SCS tWP SWE tDW DATA I/O tDH DATA VALID WRITE CYCLE 2, SCS CONTROLLED 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WSF2816-39XX FLASH AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, FWE CONTROLLED (VCC = 5.0V, TA = -55°C to +125°C) Parameter Symbol -90 Unit Min Max Write Cycle Time t AVAV t WC 90 ns Chip Select Setup Time t ELWL t CS 0 ns Write Enable Pulse Width t WLWH t WP 45 ns Address Setup Time t AVWL t AS 0 ns Data Setup Time t DVWH t DS 45 ns Data Hold Time t WHDX t DH 0 ns Address Hold Time t WLAX t AH 45 ns Chip Select Hold Time t WHEH t CH 0 ns Write Enable Pulse Width High t WHWL t WPH 20 Duration of Byte Programming Operation (1) t WHWH1 Sector Erase Time (2) t WHWH2 Read Recovery Time Before Write t GHWL ns 300 µs 15 sec 0 µs t VCS 50 µs Output Enable Setup Time tOES 0 Output Enable Hold Time (4) tOEH 10 VCC Set-up Time Chip Programming Time 11 sec ns ns Chip Erase Time 64 sec NOTES: 1. Typical value for tWHWH1 is 7µs. 2. Typical value for tWHWH1 is 1sec. 3. Typical value for Chip Erase Time is 8sec. 4. For Toggle and Data Polling. FLASH AC CHARACTERISTICS – READ ONLY OPERATIONS (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Symbol -90 Min Unit Max Read Cycle Time t AVAV t RC Address Access Time t AVQV t ACC 90 ns Chip Select Access Time t ELQV t CE 90 ns OE to Output Valid t GLQV t OE 35 ns Chip Select to Output High Z (1) t EHQZ t DF 20 ns OE High to Output High Z (1) t GHQZ t DF 20 ns Output Hold from Address, CS or OE Change, whichever is first t AXQX t OH 1. Guaranteed by design, not tested. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 6 90 0 ns ns WSF2816-39XX FLASH AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, FCS CONTROLLED (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Symbol -90 Min Unit Max Write Cycle Time t AVAV t WC 90 FWE Setup Time t WLEL t WS 0 ns ns FCS Pulse Width t ELEH t CP 45 ns Address Setup Time t AVEL t AS 0 ns Data Setup Time t DVEH t DS 45 ns Data Hold Time t EHDX t DH 0 ns Address Hold Time t ELAX t AH 45 ns FWE Hold from FWE High t EHWH t WH 0 ns FCS Pulse Width High tEHEL tCPH 20 ns Duration of Byte Programming Operation (1) t WHWH1 300 ms Duration of Erase Operation (2) t WHWH2 15 sec Chip Programming Time 11 sec Chip Erase Time (3) 64 sec Read Recovery before Write t GHEL 0 ns NOTES: 1. Typical value for tWHWH1 is 7µs. 2. Typical value for tWHWH1 is 1sec. 3. Typical value for Chip Erase Time is 8sec. 7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WSF2816-39XX FIG. 7 AC WAVEFORMS FOR FLASH MEMORY READ OPERATIONS White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 8 WSF2816-39XX FIG. 8 A0H 5.0 V Data tDS tCS FWE OE 9 tDH tWPH tWP tGHWL tWC FCS NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Addresses 5555H tAS PA PD tAH tWHWH1 Data Polling D7 PA DOUT tOE tCE tRC tDF tOH WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE CONTROLLED White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WSF2816-39XX FIG. 9 AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FLASH MEMORY NOTES: 1. SA is the sector address for Sector Erase. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 10 WSF2816-39XX FIG. 10 AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS FOR FLASH MEMORY 11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WSF2816-39XX FIG. 11 A0H tDH tCPH NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 12 5.0 V tDS Data FCS OE tWS tWC FWE Addresses 5555H tGHEL tCP tAS PA PD tAH tWHWH1 Data Polling D7 PA DOUT WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS CONTROLLED WSF2816-39XX PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1) ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 13 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WSF2816-39XX PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U) The White 68 lead G2U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form. 0.940" TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 14 WSF2816-39XX ORDERING INFORMATION W S F 2816 - 39 X X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: M = Military Screened I = Industrial C = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C PACKAGE TYPE: H1= 1.075" sq. Ceramic Hex In-line Package, HIP (Package 400) G2U = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 510) ACCESS TIME (ns) 39 = 35ns SRAM and 90ns FLASH 2Mbit of SRAM and 8Mbit of Flash ORGANIZATION: 128K x 16 SRAM and 512K x 16 Flash Flash SRAM WHITE ELECTRONIC DESIGNS CORP. 15 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com