ETC HMS81032ET

HYNIX SEMICONDUCTOR
8-BIT SINGLE-CHIP MICROCONTROLLERS
HMS81020ET
HMS81032ET
User’s Manual (Ver. 1.00)
Version 1.00
Published by
MCU Application Team
2002 Hynix Semiconductor, Inc. All right reserved.
Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors
and Representatives listed at address directory.
Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no
way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
HMS81032ET
OVERVIEW ...............................................1
Description ..............................................................1
Features ..................................................................1
Development Tools .................................................2
BLOCK DIAGRAM ...................................... 3
PIN ASSIGNMENT (Top View) ...............4
PACKAGE DIMENSION ...........................5
PIN FUNCTION .........................................8
Standard mode pin function ..................................9
PORT STRUCTURES .............................10
ELECTRICAL CHARACTERISTICS .......12
Absolute Maximum Ratings ..................................12
Recommended Operating Conditions ...................12
DC Electrical Characteristics .................................12
REMOUT Port Ioh Characteristics Graph .............14
REMOUT Port Iol Characteristics Graph ..............14
AC Characteristics ................................................15
MEMORY ORGANIZATION ....................16
Registers ...............................................................16
Program Memory ..................................................19
Data Memory .........................................................22
List for Control Registers .............................................. 23
Addressing Mode ..................................................25
I/O PORTS ..............................................29
R0 Ports ................................................................29
R1 Ports ................................................................29
R2 Port ..................................................................31
CLOCK GENERATOR ............................32
Oscillation Circuit ..................................................33
BASIC INTERVAL TIMER .......................34
WATCH DOG TIMER .............................36
Timer0, Timer1, Timer2 ..........................37
INTERRUPTS .........................................45
Interrupt priority and sources ............................... 46
Interrupt control register ....................................... 46
Interrupt accept mode .......................................... 47
Interrupt Sequence ............................................... 48
BRK Interrupt ....................................................... 50
Multi Interrupt ....................................................... 50
External Interrupt .................................................. 50
Key Scan Input Processing .................................. 51
STANDBY FUNCTION ...........................53
Sleep Mode .......................................................... 53
Stop Mode ............................................................ 53
Standby mode release ......................................... 54
Operation of standby mode release ..................... 56
RESET FUNCTION ................................59
External RESET ................................................... 59
Power on RESET ................................................. 59
Low voltage detection mode ................................ 61
EPROM MODE .......................................64
PIN ASSIGNMENT (Top View) .......................... 64
EPROM mode pin function .................................. 65
EPROM Mode setting .......................................... 66
General view of EPROM operation ...................... 67
EPROM write & verify ....................................... 68
EPROM verify ..................................................... 69
LOCK bit write ..................................................... 70
LOCK bit read ..................................................... 71
Considerations on programming .......................... 72
Programming flow chart ...................................... 73
Recommended circuit diagram of
HMS81032ET ........................................74
Sep. 2002 Ver 1.00
HMS81032ET
HMS81020ET/HMS81032ET
CMOS SINGLE- CHIP 8-BIT MICROCONTROLLER
FOR UNIVERSAL REMOTE CONTROLLER
1. OVERVIEW
1.1 Description
The HMS81020ET/HMS81032ET is an advanced CMOS 8-bit microcontroller with 20K/32K bytes of EPROM. The device
is one of GMS800 family. The HYNIX HMS81020ET/HMS81032ET is a powerful microcontroller which provides a highly
flexible and cost effective solution to many UR applications.The HMS81020ET/HMS81032ET provides the following standard features: 20K/32K bytes of EPROM, 448 bytes of RAM, 8-bit timer/counter, on-chip oscillator and clock circuitry. In
addition, the HMS81020ET/HMS81032ET supports power saving modes to reduce power consumption, low voltage indication circuit(LVIR) to display the consumption of batteries and low voltage detection control register(LVDC) to disable or
enable LVD function during transmission.
Device Name
EPROM Size
RAM Size
Package
HMS81020ET
20K Bytes
HMS81032ET
32K Bytes
448 Bytes (included
256 bytes
stack memory)
20 SOP/PDIP
24 SOP/Skinny DIP
28 SOP/Skinny DIP
1.2 Features
• Minimum instruction execution time: 1uS at
4MHz (2 cycle NOP Instruction)
• Programmable I/O pins
20 PIN
24 PIN
28 PIN
INPUT
3
3
3
OUTPUT
2
2
2
I/O
13
17
21
• Operating voltage
- 2.0 ~ 4.0 V @ 1~4MHz
• One 16-bit Timer/Counter
• Two 8-bit Timer/Counter
• One 8-bit Basic interval timer
- Timer : 3
• Power on reset
• Power saving operation modes
- STOP operation
- SLEEP operation
• Low voltage detection(LVD) circuit to get into
back-up mode
• Watchdog timer auto start (during 1second
after power on reset)
• Low voltage indication circuit(LVIR) to display
the consumption of batteries
- LVIR0: 2.2V(Typ.) - 300mV ~ +200mV
- LVIR1: 2.0V(Typ.) - 300mV ~ +200mV
• Low voltage detection control register(LVDC)
• One 6-bit Watch dog timer
• 8 Interrupt sources
- Nested interrupt control is available.
- External input: 2
- Keyscan input: 1
- Basic interval timer: 1
- Watchdog timer: 1
Sep. 2002 Ver 1.00
1
HMS81032ET
1.3 Development Tools
The HMS81020ET/HMS81032ET are supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr.TM
and OTP programmers. Macro assembler operates under the
MS-Windows 95/98TM /NT4/2000/XP.The OTP programmer
can be supplied two types of programmer such as universal single programmer (CHOICE-SIGMATM ) and stand alone gran4
programmer.
Software
- MS- Window base assembler
- Linker / Editor / Debugger
Hardware
(Emulator)
- CHOICE-Dr. (ICE main body)
- EVA 81C50 (Evaluation board)
OTP programmer
- Universal single programmer
- stand alone gang4 programmer
CHPOD810D-28SK
EVA81C50 B/D
1.4 Ordering Information
Device name
Package
ROM Size (bytes)
RAM size
HMS81020ET 20
HMS81020ET 20D
HMS81020ET 24SK
HMS81020ET 24D
HMS81020ET 28SK
HMS81020ET 28D
20DIP
20SOP
24Skinny DIP
24SOP
28Skinny DIP
28SOP
20K bytes OTP
448 bytes
HMS81032ET 20
HMS81032ET 20D
HMS81032ET 24SK
HMS81032ET 24D
HMS81032ET 28SK
HMS81032ET 28D
20DIP
20SOP
24Skinny DIP
24SOP
28Skinny DIP
28SOP
32K bytes OTP
448 bytes
2
Sep. 2002 Ver 1.00
HMS81032ET
2. BLOCK DIAGRAM
VDD
G8MC
Core
Watchdog
Timer
R0
PORT
R00~R07
R1
PORT
R10~R17
R2
PORT
R20~R24
RAM
REMOUT
R17/T0
R16/T1
R15/T2
R14/EC
R12/INT2
R11/INT1
R00~R07
R10~R17
TEST
RESET
XIN
XOUT
(448byte)
Timer
EPROM
Interrupt
(32kbyte)
Key Scan
INT.
Generation
Block
Clock Gen.
&
System
Control
Prescaler
&
BIT
VSS
Sep. 2002 Ver 1.00
3
HMS81032ET
3. PIN ASSIGNMENT (Top View)
R13
R12
R11
R10
VDD
XOUT
XIN
R00
R01
R02
R03
R20
R21
R22
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28PIN
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R14
R15
R16
R17
REMOUT
RESET
TEST
R07
R06
R05
R04
VSS
R24
R23
R13
R12
R11
R10
VDD
XOUT
XIN
R00
R01
R02
R03
R20
1
2
3
4
5
6
7
8
9
10
11
12
24PIN
24
23
22
21
20
19
18
17
16
15
14
13
R14
R15
R16
R17
REMOUT
RESET
TEST
R07
R06
R05
R04
VSS
R11
R10
VDD
XOUT
XIN
R00
R01
R02
R03
R20
1
2
3
4
5
6
7
8
9
10
20PIN
20
19
18
17
16
15
14
13
12
11
R16
R17
REMOUT
RESET
TEST
R07
R06
R05
R04
VSS
Sep. 2002 Ver 1.00
HMS81032ET
4. PACKAGE DIMENSION
20 SOP
0.5118
0.4961
0.020
0.013
0.050 PITCH
0.419
0.398
0.0125
0.0091
0.0118
0.004
0.104
0.093
0.299
0.291
UNIT: INCH
MAX
MIN
0 ~ 8°
0.042
0.016
20 PDIP
0.300 BSC
1.043
1.010
0.270
0.245
MAX 0.180
0.140
0.120
MIN 0.015
0.021
0.015
Sep. 2002 Ver 1.00
0.065
0.050
0.100 PITCH
0.014
0.008
0 ~ 15°
5
HMS81032ET
24 SOP
0.419
0.398
0.0118
0.004
0.614
0.593
0.019
0.0138
0.050 PITCH
0.0125
0.009
0.104
0.093
0.299
0.292
UNIT: INCH
MAX
MIN
0 ~ 8°
0.042
0.016
24 SKDIP
0.300 BSC
1.265
1.160
0.300
0.250
MAX 0.180
0.140
0.120
MIN 0.015
0.021
0.015
6
0.065
0.045
0.100 PITCH
0 .0 1 4
0.008
0 ~ 15°
Sep. 2002 Ver 1.00
HMS81032ET
28 SOP
0.020
0.0138
0.419
0.398
0.0118
0.004
0.713
0.697
0.050 PITCH
0 ~ 8°
0.0125
0.009
0.104
0.093
0.299
0.292
UNIT: INCH
MAX
MIN
0.042
0.016
28 SKDIP
0.300 BSC
1.375
1.355
0.300
0.275
MAX 0.180
0.140
0.120
MIN 0.020
0.021
0.015
Sep. 2002 Ver 1.00
0.055
0.045
0.100 PITCH
0 .0 1 4
0.008
0 ~ 15°
7
HMS81032ET
5. PIN FUNCTION
VDD: Supply voltage.
used as outputs or inputs.
VSS: Circuit ground.
In addition, R1 serves the functions of the various following special features.
TEST: Used for shipping inspection of the IC. For normal
operation, it should be connected to VDD.
RESET: Reset the MCU.
XIN: Input to the inverting oscillator amplifier and input to
the internal main clock operating circuit.
XOUT: Output from the inverting oscillator amplifier.
R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1
pins 1 or 0 written to the Port Direction Register can be
8
Port pin
R11
R12
R14
R15
R16
R17
Alternate function
INT1 (External Interrupt input 1)
INT2 (External Interrupt input 2)
EC (Event Counter input)
T2 (Timer / Counter output 2)
T1 (Timer / Counter output 1)
T0 (Timer / Counter output 0)
R20~R24: R2 is an 8-bit CMOS bidirectional I/O port. R2
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
Sep. 2002 Ver 1.00
HMS81032ET
5.1 Standard mode pin function
PIN NAME
INPUT/
OUTPUT
Function
@RESET
@STOP
R00
I/O
R01
I/O
R02
I/O
R03
I/O
R04
I/O
R05
I/O
R06
I/O
R07
I/O
R10
I/O
R11/INT1
I/O
R12/INT2
I/O
R13
I/O
R14/EC
I/O
R15/T2
I/O
R16/T1
I/O
R17/T0
I/O
R20
I/O
R21
I/O
R22
I/O
R23
I/O
R24
I/O
XIN
I
Oscillator input
Low
XOUT
O
Oscillator output
Low
REMOUT
O
High current output
‘L’ output
‘L’ output
RESET
I
Low active, includes pull-up resistor
‘L’ level
TEST
I
Low active, includes pull-up resistor
state of
before stop
VDD
P
Positive power supply
VSS
P
Ground
Sep. 2002 Ver 1.00
- Each bit of the port can be individually configured
as an input or an output by user software
- 8bit Push-pull output
- 8bit CMOS input with pull-up resister (can be
selectable by user software)
- Can be programmable as key scan input or open
drain output
- Pull-up resisters are automatically disabled at output
mode
INPUT
State of
before
Stop
- Each bit of the port can be individually configured
as an input or an output by user software
- 8bit Push-pull output
- 8bit CMOS input with pull-up resister (can be
selectable by user software)
- Can be programmable as key scan input or open
drain output
- Pull-up resisters are automatically disabled at output
mode
- Direct driving of LED(N-Tr.)
INPUT
State of
before
Stop
- Each bit of the port can be individually configured
as an input or an output by user software
- 5bit Push-pull output
- 5bit CMOS input with pull-up resister (can be
selectable by user software)
- Pull-up resisters are automatically disabled at output
mode
- Direct driving of LED(N-Tr.)
INPUT
State of
before
Stop
9
HMS81032ET
6. PORT STRUCTURES
R0[0:7]/KS[0:7]
R10/KS10,R11/KS11/INT1, R12/KS12/INT2, R13/
KS13,R14/KS14/EC
LVD
Signal
VDD
Pull up
Reg.
Pull-up Tr.
VDD
Pull up
Reg.
Pull-up Tr.
Open Drain
Reg.
Open Drain
Reg.
VDD
Data Bus
Data Bus
LVD
Signal
Data Reg.
Data Reg.
Pin
Function Selection Reg.
Pin
Dir. Reg.
VDD
VSS
Dir R eg.
VSS
MUX
Rd
Key Scan
Input
Noise
Filter
MUX
MUX
KS_EN
Standby Release Level Control Register
Rd
Tr.: Transistor
Reg.: Register
INT1 at R11
INT2 at R12
EC at R14
Key Scan
Input
Noise
Filter
Noise
Filter
MUX
KS_EN
Standby Release Level Control Register
10
Tr.: Transistor
Reg.: Register
Sep. 2002 Ver 1.00
HMS81032ET
R15/KS15/T2, R16/KS16/T1, R17/KS17/T0
TEST
VDD
LVD
Signal
VDD
Internal TEST
Pull up
Reg.
Pull-up Tr.
Noise
Filter
Pin
Open Drain
Reg.
Data Bus
VSS
VDD
REMOUT
Data Reg.
VDD
Pin
Function Selection Reg.
VSS
Internal Signal
Dir R eg.
Pin
VSS
MUX
Rd
T2 at R15
T1 at R16
T0 at R17
Key Scan
Input
XIN, XOUT
MUX
VDD
Noise
Filter
MUX
KS_EN
Tr.: Transistor
Reg.: Register
Standby Release Level Control Register
XIN
XOUT
VSS
R2[0:4]
STOP
LVD
Circuit
VDD
Pull up
Reg.
Pull-up Tr.
MAIN
CLOCK
RESET
VDD
Open Drain
Reg.
Data Bus
Amp
VDD
VSS
Internal Reset
Data Reg.
Noise
Filter
Pin
Pin
Dir. Reg.
From Power On Reset
VSS
MUX
Rd
Sep. 2002 Ver 1.00
Tr.: Transistor
Reg.: Register
11
HMS81032ET
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage ........................................... -0.3 to +6.0 V
Input Voltage .....................................-0.3 to VDD+0.3 V
Output Voltage ...................................-0.3 to VDD+0.3 V
Operating Temperature........................................ 0~70°C
Storage Temperature ...................................... -65~150°C
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Power Dissipation...............................................700 mW
7.2 Recommended Operating Conditions
Specifications
Parameter
Symbol
Unit
Min.
Max.
Supply Voltage
VDD
2.0
4.0
V
Operating Frequency
fXIN
1.0
4.0
MHz
TOPR
0
+70
°C
Operating Temperature
7.3 DC Electrical Characteristics
(TA=-0~70°C, VDD=2.0~4.0V, GND=0V)
Specifications
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
High level
input Voltage
VIH1
R11,R12,R14(using the EXT. interrupt
input),RESET
0.8 VDD
-
VDD
V
VIH2
R0,R1,R2
0.7 VDD
-
VDD
V
Low level
input Voltage
VIL1
R11,R12,R14(using the EXT. interrupt
input),RESET
0
-
0.2 VDD
V
VIL2
R0,R1,R2
0
-
0.3 VDD
V
High level input
Leakage Current
IIH
R0,R1,R2,RESET (without pull-up),VIH=
VDD
-
-
1
µA
Low level input
Leakage Current
IIL
R0,R1,R2,RESET (without pull-up),VIL= 0
-
-
-1
µA
High level
output Voltage
Low level
output Voltage
High level output
Leakage Current
12
VOH1
R0, IOH=-0.5mA
VDD-0.4
-
-
V
VOH2
R1, R2, IOH=-1.0mA
VDD-0.4
-
-
V
VOH3
XOUT,IOH=-50µA
VDD-0.9
-
-
V
VOL1
R0, IOL=1mA
-
-
0.4
V
VOL2
R1, R2, IOL=5mA
-
-
0.8
V
VOL3
XOUT,IOL=50µA
-
-
0.8
V
IOHL
R0,R1,R2, VOH=VDD
-
-
1
µA
Sep. 2002 Ver 1.00
HMS81032ET
Specifications
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
-
-
-1
µA
Low level output
Leakage Current
IOLL
R0,R1,R2, VOL= 0
High Level
output current
IOH
REMOUT, VOH =2V
-24
-12
-5
mA
Low Level
output current
IOL
REMOUT, VOL =1V
0.3
-
3
mA
R0,R1,R2, RESET, TEST,VDD=3V
15
30
60
µA
0.1
0.4
1.0
ΜΩ
Input pull-up current
Ip
Feedback resistance
RFD
XIN, VDD =3V
IDD1
Operating current, fxin=4Mhz, VDD=4.0V
-
4
10
mA
IDD2
Operating current, fxin=4Mhz, VDD=2.0V
-
2.4
6
mA
ISLP1
Sleep mode current, fxin=4Mhz,
VDD=4.0V
-
2
3
mA
ISLP2
Sleep mode current, fxin=4Mhz,
VDD=2.0V
-
1
2
mA
ISTP1
Stop mode current, Oscillator Stop
VDD=4.0V
-
3
10
µA
ISTP2
Stop mode current, Oscillator Stop
VDD=2.0V
-
2
8
µA
Power Supply Current
RAM retention
supply voltage
VRET
-
0.7
-
-
V
Low voltage detection
voltage
LVD
To get into back-up mode, Ta=25°C
1.55
1.70
1.85
V
Sep. 2002 Ver 1.00
13
HMS81032ET
7.4 REMOUT Port Ioh Characteristics Graph
(TA= 25°C)
.
IOH(mA)
0
VDD=2V
-5
VDD=3V
-10
-15
VDD=4V
-20
-25
-30
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VOH (V)
Figure 7-1 IOH vs VOH
7.5 REMOUT Port Iol Characteristics Graph
(TA= 25°C)
.
IOL(mA)
6
VDD=4V
5
4
VDD=3V
3
2
VDD=2V
1
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VOL (V)
Figure 7-2 IOL vs VOL
14
Sep. 2002 Ver 1.00
HMS81032ET
7.6 AC Characteristics
(TA=0~+70°°C, VDD=2.0~4.0V, VSS=0V)
Specifications
Parameter
Symbol
Pins
Unit
Min.
Typ.
Max.
250
500
1000
ns
500
1000
2000
ns
XIN
External clock input cycle time
tCP
System clock cycle time
tSYS
External clock pulse width High
tCPH
XIN
40
-
-
ns
External clock pulse width Low
tCPL
XIN
40
-
-
ns
External clock rising time
tRCP
XIN
-
-
40
ns
External clock falling time
tFCP
XIN
-
-
40
nS
Interrupt pulse width High
tIH
INT1, INT2
2
-
-
tSYS
Interrupt pulse width Low
tIL
INT1, INT2
2
-
-
tSYS
RESET Input pulse width low
tRSTL
RESET
8
-
-
tSYS
Event counter input pulse width high
tECH
EC
2
-
-
tSYS
Event counter input pulse width low
tECL
EC
2
-
-
tSYS
Event counter input pulse rising time
tREC
EC
-
-
40
ns
Event counter input pulse falling time
tFEC
EC
-
-
40
ns
tCPH
tCP
tCPL
VDD-0.5V
XIN
0.5V
tRCP
tFCP
tIH
INT1
INT2
tIL
0.8VDD
0.2VDD
tRSTL
RESET
0.2VDD
tECH
tECL
0.8VDD
EC
0.2VDD
tREC
tFEC
Figure 7-3 Timing Diagram
Sep. 2002 Ver 1.00
15
HMS81032ET
8. MEMORY ORGANIZATION
The HMS81020ET/HMS81032ET has separate address
spaces for Program memory and Data Memory. Program
memory can only be read, not written to. It can be up to
32K bytes of Program memory. Data memory can be read
and written to up to 448 bytes including the stack area.
8.1 Registers
This device has six registers that are the Program Counter
(PC), an Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.
A
ACCUMULATOR
the register contents are added to the specified address,
which becomes the actual address. These modes are extremely effective for referencing subroutine tables and
memory tables. The index registers also have increment,
decrement, comparison and data transfer functions, and
they can be used as simple accumulators.
X
X REGISTER
• X Register
Y
Y REGISTER
In the case of division instruction, execute as register.
STACK POINTER
• Y Register
SP
PCH
PCL
PROGRAM COUNTER
PSW
PROGRAM STATUS
WORD
Figure 8-1 Configuration of Registers
Accumulator:
The Accumulator is the 8-bit general purpose register, used
for data operation such as transfer, temporary saving, and
conditional judgement, etc. The Accumulator can be used
as a 16-bit register with Y Register as shown below.
In the case of multiplication instruction, execute as a multiplier register. After multiplication operation, the lower 8bit of the result enters. (Y*A => YA). In the case of division instruction, execute as the lower 8-bit of dividend. After division operation, quotient enters.
Y
Y
A
A
Two 8-bit Registers can be used as a "YA" 16-bit Register
Figure 8-2 Configuration of YA 16-bit Register
X, Y Registers:
In the case of 16-bit operation instruction, execute as the
upper 8-bit of YA. (16-bit accumulator). In the case of
multiplication instruction, execute as a multiplicand register. After multiplication operation, the upper 8-bit of the
result enters. In the case of division instruction, execute as
the upper 8-bit of dividend. After division operation, remains enters. Y register can be used as loop counter of conditional branch command. (e.g.DBNE Y, rel)
Stack Pointer:
The Stack Pointer is an 8-bit register used for occurrence
interrupts, calling out subroutines and PUSH, POP, RETI,
RET instruction. Stack Pointer identifies the location in the
stack to be accessed (save or restore).
Generally, SP is automatically updated when a subroutine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost. The SP is post-decremented when a subroutine call or a push instruction is executed, or when an interrupt is accepted. The SP is pre-incremented when a return
or a pop instruction is executed.
The stack can be located at any position within 100H to
1FFH of the internal data memory. The SP is not initialized
by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH" is
used.
In the addressing mode which uses these index registers,
16
Sep. 2002 Ver 1.00
HMS81032ET
Caution:
Stack Address (100H ~ 1FFH)
15
8
7
The Stack Pointer must be initialized by software because its value is undefined after RESET.
0
01H
SP
Example: To initialize the SP
LDX
TXSP
Hardware fixed
At execution of
a CALL/TCALL/PCALL
At acceptance
of interrupt
01FC
01FC
01FD
01FD
01FE
PCL
01FF
PCH
Push
down
At execution
of RET instruction
PSW
01FE
PCL
01FF
PCH
Push
down
#0FFH
; SP ← FFH
At execution
of RETI instruction
01FC
01FC
01FD
01FD
PSW
01FE
PCL
01FE
PCL
01FF
PCH
01FF
PCH
Pop
up
SP before
execution
01FF
01FF
01FD
01FC
SP after
execution
01FD
01FC
01FF
01FF
At execution
of PUSH instruction
PUSH A (X,Y,PSW)
At execution
of POP instruction
POP A (X,Y,PSW)
01FC
01FC
01FD
01FD
01FE
01FF
Pop
up
0100H
Stack
depth
01FE
A
Push
down
01FF
A
SP before
execution
01FF
01FE
SP after
execution
01FE
01FF
Pop
up
01FFH
Figure 8-3 Stack Operation
Program Counter:
The Program Counter is a 16-bit wide which consists of
two 8-bit registers, PCH and PCL. This counter indicates
the address of the next instruction to be executed. In reset
state, the program counter has reset routine address
(PCH:0FFH, PCL:0FEH).
Program Status Word:
reflect the current state of the CPU. The PSW is described
in Figure 8-4. It contains the Negative flag, the Overflow
flag, the Break flag the Half Carry (for BCD operation),
the Interrupt enable flag, the Zero flag, and the Carry flag.
[Carry flag C]
This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.
The Program Status Word (PSW) contains several bits that
Sep. 2002 Ver 1.00
17
HMS81032ET
[Zero flag Z]
This flag is set when the result of an arithmetic operation
or data transfer is "0" and is cleared by any other result.
MSB
PSW
N
LSB
V
G
B
H
I
Z
C
RESET VALUE: 00H
CARRY FLAG RECEIVES
CARRY OUT
NEGATIVE FLAG
OVERFLOW FLAG
ZERO FLAG
SELECT DIRECT PAGE
when g=1, page is addressed by RPR
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
BRK FLAG
Figure 8-4 PSW (Program Status Word) Register
[Interrupt disable flag I]
This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
[Half carry flag H]
After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).
[Break flag B]
This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector address.
the direct addressing mode, addressing area is from zero
page 00H to 0FFH when this flag is "0". If it is set to "1",
addressing area is 1 Page. It is set by SETG instruction and
cleared by CLRG.
[Overflow flag V]
This flag is set to "1" when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80H). The CLRV instruction
clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
[Direct page flag G]
This flag assigns RAM page for direct addressing mode. In
18
Sep. 2002 Ver 1.00
HMS81032ET
8.2 Program Memory
A 16-bit program counter is capable of addressing up to
64K bytes, but this device has 20K/32K bytes program
memory space only physically implemented. Accessing a
location above FFFFH will cause a wrap-around to 0000H.
Example: Usage of TCALL
Figure 8-5, shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFEH and FFFFH as shown in Figure 8-6.
;
;TABLE CALL ROUTINE
;
FUNC_A: LDA
LRG0
RET
;
FUNC_B: LDA
LRG1
2
RET
;
;TABLE CALL ADD. AREA
;
ORG
0FFC0H
DW
FUNC_A
DW
FUNC_B
As shown in Figure 8-5, each area is assigned a fixed location in Program Memory. Program Memory area contains
the user program.
8000H
LDA
#5
TCALL 0FH
:
:
;1BYTE INSTR UCTIO N
;INSTEAD OF 2 BYTES
;NOR M AL C ALL
1
;TCALL ADDRESS AREA
FFC0H
FFE0H
FFFFH
PCALL
AREA
HMS81032ET 32KROM
FF00H
HMS81020ET 20KROM
B000H
The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte
interval: 0FFF8H and 0FFF9H for External Interrupt 1,
0FFFAH and 0FFFBH for External Interrupt 0, etc.
Any area from 0FF00H to 0FFFFH, if it is not going to be
used, its service location is available as general purpose
Program Memory.
TCALL
AREA
Address
INTERRUPT
VECTOR AREA
0FFDEH
Vector Area Memory
S/W Interrupt Vector Area
E0
-
E2
-
E4
-
E6
Basic Interval Timer Interrupt Vector Area
Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called,
it is more useful to save program byte length.
E8
Watch Dog Timer Interrupt Vector Area
EA
-
F0
Timer1 Interrupt Vector Area
Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0H for TCALL15, 0FFC2H for
TCALL14, etc., as shown in Figure 8-7.
F2
Timer0 Interrupt Vector Area
Figure 8-5 Program Memory Map
EC
-
EE
Timer2 Interrupt Vector Area
F4
-
F6
External Interrupt 2 Vector Area
F8
External Interrupt 1 Vector Area
FA
FC
Key Scan Interrupt Vector Area
-
FE
RESET Vector Area
NOTE:
"-" means reserved area.
Figure 8-6 Interrupt Vector Area
Sep. 2002 Ver 1.00
19
HMS81032ET
Address
Address
Program Memory
0FFC0H
C1
TCALL 15
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
PCALL Area Memory
0FF00H
PCALL Area
(192 Bytes)
0FFBFH
TCALL 14
TCALL 13
TCALL 12
TCALL 11
TCALL 10
TCALL 9
TCALL 8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
TCALL 7
TCALL 6
TCALL 5
TCALL 4
TCALL 3
TCALL 2
TCALL 1
TCALL 0 / BRK *
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
Figure 8-7 PCALL and TCALL Memory Area
PCALL→
→ rel
TCALL→
→n
4F35
4A
PCALL 35H
TCALL 4
4A
4F
35
~
~
~
~
~
~
0D125H
~
~
NEXT
0FF00H
0FF35H
0FFFFH
01001010
➊
PC: 11111111 11010110
FH FH
DH 6H
➌
NEXT
0FF00H
0FFD6H
25
0FFD7H
D1
Reverse
➋
0FFFFH
20
Sep. 2002 Ver 1.00
HMS81032ET
Example: The usage software example of Vector address and the initialize part.
ORG
0FFE0H
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
NOT_USED
NOT_USED
NOT_USED
BIT_INT
WDT_INT
NOT_USED
NOT_USED
TMR2_INT
TMR1_INT
TMR0_INT
NOT_USED
INT2
INT1
KEY_INT
NOT_USED
RESET
ORG
08000H
; BIT
; Watch Dog Timer
;
;
;
;
;
;
;
;
;
Timer-2
Timer-1
Timer-0
Int.2
Int.1
Key Scan
Reset
;HMS81032E Program start address
;********************************************
;
MAIN
PROGRAM
*
;********************************************
;
RESET:
NOP
CLRG
DI
;Disable All Interrupts
LDX
#0
RAM_CLR: LDA
#0
;RAM Clear(!0000H->!00BFH)
STA
{X}+
CMPX
#0C0H
BNE
RAM_CLR
;
LDX
TXSP
#0FFH
;Stack Pointer Initialize
LDM
LDM
LDM
LDM
:
:
LDM
:
:
R0, #0
R0DD,#1000_0010B
P0PC,#1000_0010B
PMR1,#0000_0010B
;Normal Port 0
;Normal Port Direction
;Pull Up Selection Set
;R1 port / int
CKCTLR,#0011_1101B
;WDT ON, 16mS Time delay after stop mode release
Sep. 2002 Ver 1.00
21
HMS81032ET
8.3 Data Memory
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into 3 groups, a user RAM,
control registers, Stack.
0000H
Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
More detailed informations of each register are explained
in each peripheral section.
RAM
(192 Bytes)
PAGE0
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction.
00BFH
00C0H
00FFH
CONTROL
REGISTERS
Example; To write at CKCTLR
0100H
LDM
RAM (STACK)
(256 Bytes)
PAGE1
01FFH
Figure 8-8 Data Memory Map
User Memory
The HMS81020ET/HMS81032ET has 448 × 8 bits for the
user memory (RAM).
Control Registers
The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0H to 0FFH.
22
CLCTLR,#09H ;Divide ratio ÷16
Stack Area
The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.
When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the program counter and flags.
The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save. Refer to Figure 8-3 on page 17.
Sep. 2002 Ver 1.00
HMS81032ET
8.4 List for Control Registers
Address
Function Register
Symbol
Read
Write
RESET Value
00C0h
PORT R0 DATA REG.
R0
R/W
undefined
00C1h
PORT R0 DATA DIRECTION REG.
R0DD
W
00000000b
00C2h
PORT R1 DATA REG.
R1
R/W
undefined
00C3h
PORT R1 DATA DIRECTION REG.
R1DD
W
00000000b
00C4h
PORT R2 DATA REG.
R2
R/W
undefined
00C5h
PORT R2 DATA DIRECTION REG.
R2DD
W
- - -00000b
00C6h
Reserved
00C7h
CLOCK CONTROL REG.
CKCTLR
W
- -110111b
BASIC INTERVAL REG.
BITR
R
undefined
00C8h
WATCH DOG TIMER REG.
WDTR
W
-0001111b
00C9h
PORT R1 MODE REG.
PMR1
W
00000000b
00CAh
INT. MODE REG.
IMOD
R/W
- -000000b
00CBh
EXT. INT. EDGE SELECTION
IEDS
W
- -0000- -b
00CCh
INT. ENABLE REG. LOW
IENL
R/W
-00- - - - -b
00CDh
INT. REQUEST FLAG REG. LOW
IRQL
R/W
-00- - - - -b
00CEh
INT. ENABLE REG. HIGH
IENH
R/W
000-000-b
00CFh
INT. REQUEST FLAG REG. HIGH
IRQH
R/W
000-000-b
00D0h
TIMER0 (16bit) MODE REG.
TM0
R/W
00000000b
00D1h
TIMER1 (8bit) MODE REG.
TM1
R/W
00000000b
00D2h
TIMER2 (8bit) MODE REG.
TM2
R/W
00000000b
00D3h
TIMER0 HIGH-MSB DATA REG.
T0HMD
W
undefined
00D4h
TIMER0 HIGH-LSB DATA REG.
T0HLD
W
undefined
TIMER0 LOW-MSB DATA REG.
T0LMD
W
undefined
TIMER0 HIGH-MSB COUNT REG.
T0HMC
R
undefined
TIMER0 LOW-LSB DATA REG.
T0LLD
W
undefined
TIMER0 LOW-LSB COUNT REG.
T0LLC
R
undefined
TIMER1 HIGH DATA REG.
T1HD
W
undefined
TIMER1 LOW DATA REG.
T1LD
W
undefined
R
undefined
W
undefined
R
undefined
TM01
R/W
00000000b
00D5h
00D6h
00D7h
00D8h
00D9h
TIMER1 LOW COUNT REG.
TIMER2 DATA REG.
T2DR
TIMER2 COUNT REG.
00DAh
TIMER0 / TIMER1 MODE REG.
00DBh
Reserved
00DCh
STANDBY MODE RELEASE REG0
SMPR0
W
00000000b
00DDh
STANDBY MODE RELEASE REG0
SMPR1
W
00000000b
00DEh
PORT R1 OPEN DRAIN ASSIGN REG.
R1ODC
W
00000000b
Sep. 2002 Ver 1.00
23
HMS81032ET
00DFh
PORT R2 OPEN DRAIN ASSIGN REG.
R2ODC
W
- - -00000b
00E0h
Reserved
00E1h
Reserved
00E2h
Reserved
00E3h
Reserved
00E4h
PORT R0 OPEN DRAIN ASSIGN REG.
R0ODC
W
00000000b
00E5h
Reserved
00E6h
Reserved
00E7h
Reserved
00E8h
Reserved
00E9h
Reserved
00EAh
Reserved
00EBh
Reserved
00ECh
Reserved
00EDh
Reserved
00EEh
Reserved
00EFh
LOW VOLTAGE INDICATION REG.
LVIR
R
- - - - - -00b
00F0h
SLEEP MODE REG.
SLPM
W
- - - - - - -0b
00F1h
LVD CONTROL REG.
LVDC
W
- - - - 0- - -b
00F2h
Reserved
00F3h
Reserved
00F4h
Reserved
00F5h
Reserved
00F6h
STANDBY RELEASE LEVEL CONT. REG. 0
SRLC0
W
00000000b
00F7h
STANDBY RELEASE LEVEL CONT. REG. 1
SRLC1
W
00000000b
00F8h
PORT R0 PULL-UP REG. CONT. REG.
R0PC
W
00000000b
00F9h
PORT R1 PULL-UP REG. CONT. REG.
R1PC
W
00000000b
00FAh
PORT R2 PULL-UP REG. CONT. REG.
R2PC
W
- - - 00000b
00FBh
Reserved
00FCh
Reserved
00FDh
Reserved
00FEh
Reserved
00FFh
Reserved
W
R/W
Registers are controlled by byte manipulation instruction such as LDM etc., do not use bit manipulation
instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,
content of other seven bits are may varied to unwanted value.
Registers are controlled by both bit and byte manipulation instruction.
- : this bit location is reserved.
LVIR,LVDC are newly added in HMS81032ET, but not supported in MASK and EVA version
24
Sep. 2002 Ver 1.00
HMS81032ET
8.5 Addressing Mode
The HMS81020ET/HMS81032ET uses six addressing
modes;
(3) Direct Page Addressing → dp
• Register addressing
Example;
• Immediate addressing
C535
In this mode, a address is specified within direct page.
LDA
;A ←RAM[35H]
35H
• Direct page addressing
• Absolute addressing
0035H
data
➋
• Indexed addressing
~
~
• Register-indirect addressing
(1) Register Addressing
~
~
0F550H
C5
0F551H
35
➊
data → A
Register addressing accesses the A, X, Y, C and PSW.
(2) Immediate Addressing → #imm
In this mode, second byte (operand) is accessed as a data
immediately.
Absolute addressing sets corresponding memory data to
Data, i.e. second byte(Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.
Example:
0435
ADC
(4) Absolute Addressing → !abs
#35H
MEMORY
04
A+35H+C → A
35
ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY
Example;
0735F0
E45535
LDM
ADC
35H,#55H
data
0F035H
~
~
➊
0F100H
data ← 55H
data
0035H
;A ←ROM[0F035H]
!0F035H
~
~
~
~
0F100H
➋
~
~
➊
A+data+C → A
07
0F101H
35
0F102H
F0
address: 0F035
➋
E4
0F101H
55
0F102H
35
Sep. 2002 Ver 1.00
25
HMS81032ET
The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR
Example; Addressing accesses the address 0135H.
983500
INC
;A ←RAM[035H]
!0035H
X indexed direct page, auto increment→
→ {X}+
In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.
LDA, STA
Example; X=35H
DB
data
0035H
~
~
LDA
{X}+
➌
~
~
➋
data+1 → data
0F100H
98
➊
0F101H
35
address: 0035
0F102H
00
35H
➋
data
~
~
~
~
data → A
➊
36H → X
DB
(5) Indexed Addressing
X indexed direct page (no offset) → {X}
In this mode, a address is specified by the X register.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Example; X=15H
D4
LDA
{X}
;ACC←RAM[X].
X indexed direct page (8 bit offset) → dp+X
This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page.
ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR
Example; X=015H
15H
~
~
0F550H
C645
data
~
~
D4
LDA
45H+X
➋
data → A
➊
5AH
data
➌
~
~
26
➋
~
~
0F550H
C6
0F551H
45
data → A
➊
45H+15H=5AH
Sep. 2002 Ver 1.00
HMS81032ET
Y indexed direct page (8 bit offset) → dp+Y
3F35
JMP
[35H]
This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in
Direct page.
This is same with above (2). Use Y register instead of X.
35H
0A
36H
F3
Y indexed absolute →!abs+Y
~
~
Sets the value of 16-bit absolute address plus Y-register
data as Memory. This addressing mode can specify memory in whole area.
Example; Y=55H
D500FA
LDA
~
~
D5
00
0F102H
FA
~
~
~
~
➊
3F
35
!0FA00H+Y
0F100H
➋ jump to address 0F30AH
NEXT
0FA00H
0F101H
0FA55H
0F30AH
~
~
➊
0FA00H+55H=0FA55H
~
~
➋
data
➌
data → A
X indexed indirect → [dp+X]
Processes memory data as Data, assigned by 16-bit pair
memory which is determined by pair data
[dp+X+1][dp+X] Operand plusX-register data in Direct
page.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; X=10H
1625
ADC
[25H+X]
(6) Indirect Addressing
Direct page indirect → [dp]
Assigns data address to use for accomplishing command
which sets memory data(or pair memory) by Operand.
Also index can be used with Index register X,Y.
JMP, CALL
35H
05
36H
F4
0F405H
~
~ ➋
~
~
0F405H
~
~
Example;
0FA00H
~
~
16
25
Sep. 2002 Ver 1.00
➊ 25 + X(10) = 35H
data
➌ A + data + C → A
27
HMS81032ET
Y indexed indirect → [dp]+Y
Absolute indirect → [!abs]
Processes memory data as Data, assigned by the data
[dp+1][dp] of 16-bit pair memory paired by Operand in Direct pageplus Y-register data.
The program jumps to address specified by 16-bit absolute
address.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; Y=10H
1725
ADC
JMP
Example;
1F25F0
JMP
[!0F025H]
[25H]+Y
PROGRAM MEMORY
25H
05
0F025H
25
26H
F7
0F026H
F8
~
~
0F715H
~
~
0FA00H
~
~
➊
0F825H
~
~
0FA00H
17
➌ A + data + C → A
➋
jump to
address 0F80AH
NEXT
~
~
~
~
25
28
0F705H + Y(10) = 0F715H
➊
data
~
~
➋
~
~
1F
25
F0
Sep. 2002 Ver 1.00
HMS81032ET
9. I/O PORTS
The HMS81020ET/HMS81032ET has 21 I/O ports which
are PORT0(8 I/O), PORT1 (8 I/O), PORT2 (5 I/O). Pullup resistor of each port can be selectable by program. Each
port contains data direction register which controls I/O and
data register which stores port data.
(1) R0 I/O Data Direction Register (R0DD)
R0 I/O Data Direction Register (R0DD) is an 8-bit register,
and can assign input state or output state to each bit. If
R0DD is “1”, port R0 is in the output state, and if “0”, it is
in the input state. R0DD is write-only register. Since
R0DD is initialized as “00h” in reset state, the whole port
R0 becomes input state.
9.1 R0 Ports
R0 is an 8-bit CMOS bidirectional I/O port (address
0C0H). Each I/O pin can independently used as an input or
an output through the R0DD register (address 0C1H).
R0 has internal pull-ups that is independently connected or
disconnected by R0PC. The control registers for R0 are
shown below.
(2) R0 Data Register (R0)
R0 data register (R0) is an 8-bit register to store data of port
R0. When set as the output state by R0DD, and data is written in R0, data is output into R0 pin. When set as the input
state, input state of pin is read. The initial value of R0 is unknown in reset state.
(3) R0 Open drain Assign Register (R0ODC)
R0 Data Register (R/W)
R0
ADDRESS: 0C0H
RESET VALUE: Undefined
R07 R06 R05 R04 R03 R02 R01 R00
R0 Direction Register (W)
ADDRESS: 0C1H
RESET VALUE: 00H
R0DD
(4) R0 Pull-up Control Register (R0PC)
Port Direction
0: Input
1: Output
R0 Pull-up Control Register (W)
R0 Open Drain Assign Register (R0ODC) is an 8-bit register, and can assign R0 port as open drain output port each
bit, if corresponding port is selected as output. If R0ODC
is selected as “1”, port R0 is open drain output, and if selected as, “0” it is push-pull output. R0ODC is write-only
register and initialized as “00h” in reset state.
ADDRESS:0F8H
RESET VALUE: 00H
R0PC
Pull-up select
1: Without pull-up
0: With pull-up
R0 Open drain Assign Register (W) ADDRESS:0E4H
RESET VALUE: 00H
R0ODC
Open drain select
0: Push-pull
1: Open drain
R0 Pull-up Control Register (R0PC) is an 8-bit register and
can control pull-up on or off each bit, if corresponding port
is selected as input. If R0PC is selected as “1”, pull-up is
disabled and if selected as “0”, it is enabled. R0PC is writeonly register and initialized as “00h” in reset state. The
pull-up is automatically disabled, if corresponding port is
selected as output.
9.2 R1 Ports
R1 is an 8-bit CMOS bidirectional I/O port (address
0C2H). Each I/O pin can independently used as an input or
an output through the R1DD register (address 0C3H).
R1 has internal pull-ups that is independently connected or
disconnected by register R1PC. The control registers for
R1 are shown at next page.
Sep. 2002 Ver 1.00
29
HMS81032ET
R1 Data Register (R/W)
R1
ADDRESS: 0C2H
RESET VALUE: Undefined
R17 R16 R15 R14 R13 R12 R11 R10
R1 Direction Register (W)
ADDRESS: 0C3H
RESET VALUE: 00H
R1DD
Port Direction
0: Input
1: Output
R1 Pull-up Control Register (W)
ADDRESS: 0F9H
RESET VALUE: 00H
R1PC
Pull-up select
1: Without pull-up
0: With pull-up
R1 Open drain Assign Register (W) ADDRESS: 0DEH
RESET VALUE: 00H
ter, and can assign R1 port as open drain output port each
bit, if corresponding port is selected as output. If R1ODC
is selected as “1”, port R1 is open drain output, and if selected as “0”, it is push-pull output. R1ODC is write-only
register and initialized as “00h” in reset state.
(4) R1 Port Mode Register (PMR1)
R1 Port Mode Register (PMR1) is an 8-bit register, and can
assign the selection mode for each bit. When set as “0”,
corresponding bit of PMR1 acts as port R1 selection mode,
and when set as “1”, it becomes function selection mode.
PMR1 is write-only register and initialized as “00h” in reset state. Therefore, becomes Port selection mode. Port R1
can be I/O port by manipulating each R1DD bit, if corresponding PMR1 bit is selected as “0”.
Bit Name
PMR1
Selection
Mode
Remarks
0
R17 (I/O)
-
1
T0 (O)
Timer0
0
R16 (I/O)
-
1
T1 (O)
Timer1
0
R15 (I/O)
-
1
T2 (O)
Timer2
0
R14 (I/O)
-
1
EC (I)
Timer0 Event
0
R12 (I/O)
1
INT2 (I)
0
R11 (I/O)
1
INT1 (I)
P1ODC
Open drain select
0: Push-pull
1: Open drain
R1 Port Mode Register (W)
ADDRESS: 0C9H
RESET VALUE: 00H
PMR1
T0S
T1S
T2S
Mode select
0: Port R1 selection
1: Function selection
ECS
INT2S
Timer0 Input Capture
(1) R1 I/O Data Direction Register (R1DD)
R1 I/O Data Direction Register (R1DD) is an 8-bit register,
and can assign input state or output state to each bit. If
R1DD is “1”, port R1 is in the output state, and if “0”, it is
in the input state. R1DD is write-only register. Since
R1DD is initialized as “00h” in reset state, the whole port
R1 becomes input state.
(2) R1 Data Register (R1)
R1 data register (R1) is an 8-bit register to store data of
port R1. When set as the output state by R1DD, and data
is written in R1, data is output into R1 pin. When set as
the input state, input state of pin is read. The initial value
of R1 is unknown in reset state.
INT1S
Table 9-1 Selection mode of PMR1
(5) R1 Pull-up Control Register (R1PC)
R1 Pull-up Control Register (R1PC) is an 8-bit register and
can control pull-up on or off each bit, if corresponding port
is selected as input. If R1PC is selected as “1”, pull-up is
disabled and if selected as “0”, it is enabled. R1PC is writeonly register and initialized as “00h” in reset state. The
pull-up is automatically disabled, if corresponding port is
selected as output.
(3) R1 Open drain Assign Register (R1ODC)
R1 Open Drain Assign Register (R1ODC) is an 8bit regis-
30
Sep. 2002 Ver 1.00
HMS81032ET
9.3 R2 Port
R2 is an 5-bit CMOS bidirectional I/O port (address
0C4H). Each I/O pin can independently used as an input or
an output through the R2DD register (address 0C5H).
R2 has internal pull-ups that is independently connected or
disconnected by R2PC (address 0FAH). The control registers for R2 are shown as below.
ADDRESS: 0C4H
RESET VALUE: Undefined
R2 Data Register (R/W)
R2
-
-
-
R24 R23 R22 R21 R20
R2 Direction Register (W)
ADDRESS: 0C5H
RESET VALUE: 00H
R2DD
Port Direction
0: Input
1: Output
R2 Pull-up Control Register (W)
ADDRESS:0FAH
RESET VALUE: 00H
(1) R2 I/O Data Direction Register (R2DD)
R2 I/O Data Direction Register (R2DD) is an 8-bit register,
and can assign input state or output state to each bit. If
R2DD is “1”, port R2 is in the output state, and if “0”, it is
in the input state. R2DD is write-only register. Since
R2DD is initialized as “00h” in reset state, the whole port
R2 becomes input state.
(2) R2 Data Register (R2)
R2 data register (R2) is an 8-bit register to store data of port
R2. When set as the output state by R2DD, and data is written in R2, data is outputted into R2 pin. When set as the input state, input state of pin is read. The initial value of R2
is unknown in reset state.
(3) R2 Open drain Assign Register (R2ODC)
R2 Open Drain Assign Register (R2ODC) is an 8bit register, and can assign R2 port as open drain output port each
bit, if corresponding port is selected as output. If R2ODC
is selected as “1”, port R2 is open drain output, and if selected as “0”, it is push-pull output. R2ODC is write-only
register and initialized as “00h” in reset state.
R2PC
Pull-up select
1: Without pull-up
0: With pull-up
R2 Open drain Assign Register (W) ADDRESS:0DFH
RESET VALUE: 00H
R2ODC
Open drain select
0: Push-pull
1: Open drain
Sep. 2002 Ver 1.00
(4) R2 Pull-up Control Register (R2PC)
R2 Pull-up Control Register (R2PC) is an 8-bit register and
can control pull-up on or off each bit, if corresponding port
is selected as input. If R2PC is selected as “1”, pull-up ia
disabled and if selected as ”0”, it is enabled. R2PC is writeonly register and initialized as “00h” in reset state. The
pull-up is automatically disabled, if corresponding port is
selected as output.
31
HMS81032ET
10. CLOCK GENERATOR
state.
The Clock generating circuit consists of Clock Pulse Generator (C.P.G), Prescaler, Basic Interval Timer (BIT) and
Watch Dog Timer. The clock applied to the Xin pin divided by two is used as the internal system clock.
ADDRESS: 0C7H
INITIAL VALUE: --110111b
Clock Control Register (W)
CKCTLR
7
6
5
4
3
2
1
0
Prescaler consist of 12-bit binary counter. The clock supplied from oscillation circuit is input to prescaler(fXIN)
The divided output from each bit of prescaler is provided
to peripheral hardware
ENPCK
0: Stopped
1: Provided
Clock to peripheral hardware can be stopped by bit4 (ENPCK) of CKCTLR Register. ENPCK is set to “1” in reset
OSC
CIRCUIT
fXIN
Internal system clock (CPU clock)
CLOCK PULSE
GENERATOR
PRESCALER
PS0
÷1
PS1
÷2
PS2
÷4
PS3
÷8
PS4
÷16
PS5
÷32
PS6
÷64
PS7
÷128
PS8
÷256
PS9
PS10
PS11 PS12
÷512 ÷1024 ÷2048 ÷4096
Peripheral clock
fXIN=4MHz
Frequency (Hz)
period (S)
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
4M
2M
1M
500K
250K
125K
62.5K
31.25K
15.63K
250n
500n
1u
2u
4u
8u
16u
32u
64u
PS9
PS10
7.183K 3.906K
128u
256u
PS11
PS12
1.953K 0.976K
512u
1024u
Figure 10-1 Block diagram of Clock Generator
32
Sep. 2002 Ver 1.00
HMS81032ET
10.1 Oscillation Circuit
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Figure 10-2 shows
circuit diagrams using a crystal (or ceramic) oscillator. As
shown in the diagram, oscillation circuits can be constructed by connecting a oscillator between Xout and Xin. Clock
from oscillation circuit makes CPU clock via clock pulse
generator, and then enters prescaler to make peripheral
hardware clock. Alternately, the oscillator may be driven
from an external source as Figure 10-3 . In the STOP
mode, oscillation stop, Xout state goes to “Low”, Xin state
goes to “LOW”, and built-in feed back resistor is disabled.
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and
ceramic resonator have their own characteristics, the user
should consult the crystal manufacturer for appropriate
values of external components. In addition, see Figure 104 for the layout of the crystal.
Note: Minimize the wiring length. Do not allow the wiring to
intersect with other signal conductors. Do not allow the wiring to come near changing high current. Set the potential of
the grounding position of the oscillator capacitor to that of
VSS. Do not ground it to any ground pattern where high current is present. Do not fetch signals from the oscillator.
Xout
Cout
Cin
Xin
Vss
XOUT
Figure 10-2 External Crystal(Ceramic) oscillator circuit
CKB
External
Clock
Source
XIN
Xout
CK
Xin
Figure 10-4 Recommend Layout of Oscillator PCB
circuit
Vss
Figure 10-3 External clock input circuit
Frequency
Resonator Maker
Part Name
Load Capacitor
Operating Voltage(V)
CQ
ZTA2.00M
Cin=Cout=33pF
2.0~4.0
MURATA
CSTCC2M00G56-R0
Cin=Cout=open
2.0~4.0
MURATA
CSTCC2.00MG0H6
Cin=Cout=open
2.0~4.0
CQ
ZTA4.00M
Cin=Cout=33pF
2.0~4.0
MURATA
CSTS0400MG03
Cin=Cout=open
2.0~4.0
MURATA
CSTLS4M00G53-B0
Cin=Cout=open
2.0~4.0
MURATA
CSTCR4M00G53-R0
Cin=Cout=open
2.0~4.0
TDK
FCR4.0MC5
Cin=Cout=open
2.0~4.0
2.00MHz
4.00MHz
Table 10-1 recommendation resonator
Sep. 2002 Ver 1.00
33
HMS81032ET
11. BASIC INTERVAL TIMER
The Basic Interval Timer is controlled by the clock control
register (CKCTLR) shown in Figure 11-2. If bit3(BTCL)
of CKCTLR is set to “1”, BIT is cleared, and then, after
one machine cycle, BTCL becomes “0”, and BIT starts
counting. BTCL is set to ``0`` in reset state.
The HMS81020ET/HMS81032ET has one 8-bit Basic Interval Timer that is free-run and can not stop. Block diagram is shown in Figure 11-1.
The Basic Interval Timer generates the time base for
Standby release time, watchdog timer counting, and etc. It
also provides a Basic interval timer interrupt (IFBIT). As
the count overflow from FFH to 00H, this overflow causes
the interrupt to be generated.
The input clock of BIT can be selected from the prescaler
within a range of 2us to 256us by clock input selection bits
(BTS2~BTS0). (at fXIN = 4MHz). In reset state, or power
on reset, BTS2=“1”, BTS1= “1”, BTS0= “1” to secure the
longest oscillation stabilization time. BIT can generate the
wide range of basic interval time interrupt request (IFBIT)
by selecting prescaler output.
-8bit binary up-counter
-Use the bit output of prescaler as input to secure the oscillation stabilization time after power-on
-Secures the oscillation stabilization time in standby mode
(stop mode) release
By reading of the Basic Interval Timer Register (BITR),
we can read counter value of BIT Because BIT can be
cleared or read, the spending time up to maximum 65.5ms
can be available. BIT is read-only register. If BIT register
is written, then CKCTLR register with same address is
written.
-Contents of BIT can be read
-Provides the clock for watch dog timer
÷8
÷16
Prescaler
÷32
÷64
÷128
MUX
source
clock
Basic Interval Timer
overflow
8-bit up-counter
IFBIT
Basic Interval Timer Interrupt
÷256
÷512
÷1024
To Watchdog timer (WDTR)
clear
Select Input clock 3
BTS[2:0]
[0C7H]
CKCTLR
BTCL
BITR
Read
clock control register
Internal bus line
Figure 11-1 Block diagram of Basic Interval Timer
34
Sep. 2002 Ver 1.00
HMS81032ET
7
-
CKCTLR
6
-
W
5
W
4
W
W
W
W
3
2
1
0
WDTON ENPCKBTCL
BTCL BTS2 BTS1 BTS0
ADDRESS: 0C7H
INITAIL VALUE: --110111B
Basic Interval Timer source clock select
000: fXIN ÷ 8
001: fXIN ÷ 16
010: fXIN ÷ 32
011: fXIN ÷ 64
100: fXIN ÷ 128
101: fXIN ÷ 256
110: fXIN ÷ 512
111: fXIN ÷ 1024
Caution:
Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.
Clear bit
0: Normal operation, free-run
1: Clear 8-bit counter (BITR) to “0” and count up again.
This bit becomes to “0” automatically after one machine cycle.
Peripheral clock
0:stopped
1:provided
Watch Dog Timer function control
0:6bit timer
1:Watch Dog Timer
R
7
R
6
R
5
R
4
BITR
R
3
BTCL
R
2
R
1
R
0
ADDRESS: 0C7H
INITIAL VALUE: Undefined
8-BIT FREE-RUN BINARY COUNTER
Figure 11-2 CKCTLR AND BITR
BTS[2:0]
000
001
010
011
100
101
110
111
CPU Source clock
÷8
÷16
÷32
÷64
÷128
÷256
÷512
÷1024
BIT Input [email protected](us)
2
4
8
16
32
64
128
256
Standby release time(ms)
0.512
1.024
2.048
4.096
8.192
16.384
32.768
65.536
Table 11-1 Standby release time according to BTS
Sep. 2002 Ver 1.00
35
HMS81032ET
12. WATCH DOG TIMER
As IFBIT (Basic Interval Timer Interrupt Request) is used
for input clock of WDT, Input clock cycle is possible from
512 us to 65,536 us by BTS. (at fXIN = 4MHz)
Watch Dog Timer (WDT) consists of 6-bit binary counter,
6-bit comparator, and Watch Dog Timer Register
(WDTR).Watch Dog Timer can be used 6-bit general Timer or specific Watch dog timer by setting bit5 (WDTON)
of Clock Control Register (CKCTLR).By assigning
bit6(WDTCL) of WDTR, 6-bit counter can be cleared.
*At Hardware reset time, WDT starts automatically.
Therefore the user must select the CKCTLR and WDTR
before WDT overflow.
WDT Interrupt (IFWDT) interval is determined by the interrupt IFBIT interval of Basic Interval Timer and the value of WDT Register.
-Reset WDTR value = 0Fh=15
-Interval of WDT = 65,536 × 15 = 983,040 us
-Interval of IFWDT = (IFBIT interval) × (WDTR value)
7
WDTR
-
(about 1second)
W
W
W
W
W
W
W
6
5
4
3
2
1
0
WDTCL WDTR5 WDTR4 WDTR3
BTCL WDTR2 WDTR1 WDTR0
ADDRESS: 0C8H
INITIAL VALUE: -0001111b
Watch Dog Timer Operation
0:Free-run
1:Automatically cleared, after one machine cycle
WDTON
IFBIT
WDT (6-bit)
To Reset circuit
IFWDT
Comparator
Clear 6
WDTCL
WDT
INTERRUPT
WDTR (6-bit)
[0C8H]
Figure 12-1 Block diagram of Watch Dog Timer
36
Sep. 2002 Ver 1.00
HMS81032ET
13. Timer0, Timer1, Timer2
(1) Timer Operation Mode
Timer consists of 16bit binary counter Timer0 (T0), 8bit
binary Timer1 (T1), Timer2 (T2), Timer Data Register,
Timer Mode Register (TM01, TM0, TM1, TM2) and control circuit. Timer Data Register Consists of Timer0 HighMSB Data Register (T0HMD), Timer0 High-LSB Data
Register (T0HLD), Timer0 Low-MSB Data Register
(T0LMD), Timer0 Low-LSB Data Register (T0LLD),
Timer1 High Data Register (T1HD), Timer1 Low Data
Timer0
- 16-bit Interval Timer
- 16-bit Event Counter
- 16-bit Input Capture
- 16-bit rectangular-wave output
Timer1
- 8-bit Interval Timer
- 8-bit rectangular-wave output
Timer2
- 8-bit Interval Timer
- 8-bit rectangular-wave output
- Modulo-N Mode
Register (T1LD), Timer2 Data Register (T2DR). Any of
the PS0 ~ PS5, PS11 and external event input EC can be
selected as clock source for T0. Any of the PS0 ~ PS3, PS7
~ PS10 can be selected as clock T1. Any of the PS5 ~ PS12
can be selected as clock source for T2.
* Relevant Port Mode Register (PMR1: 00C9h) value
should be assigned for event counter.
- Single/Modulo-N Mode
- Timer Output Initial Value Setting
- Timer0~Timer1 combination Logic Output
- One Interrupt Generating Every 2nd
Counter Overflow
Table 13-1 Timer Operation
16bit Timer 0 (fXIN=4MHz)
Resolution
MAX. Count
8bit Timer 1 (fXIN=4MHz)
Resolution
MAX. Count
8bit Timer 2 (fXIN=4MHz)
Resolution
MAX. Count
PS0 (0.25us)
16,384us
PS0 (0.25us)
64us
PS5 (8us)
2,048us
PS1 (0.5us)
32,768us
PS1 (0.5us)
128us
PS6 (16us)
4,096us
PS2 (1us)
65,536us
PS2 (1us)
256us
PS7 (32us)
8,192us
PS3 (2us)
131,072us
PS3 (2us)
512us
PS8 (64us)
16,384us
PS4 (4us)
262,144us
PS7 (32us)
8,192us
PS9 (128us)
32,768us
PS5 (8us)
524,288us
PS8 (64us)
16,384us
PS10 (256us)
65,536us
PS11 (512us)
33,554,432us
PS9 (128us)
32,768us
PS11 (512us)
131,072us
PS10 (256us)
65,536us
PS12 (1024us)
262,144us
EC
-
Table 13-2 Function of Timer & Counter
Sep. 2002 Ver 1.00
37
HMS81032ET
T0HMD T0HLD
T0LMD
T0LLD
T1HD
T1LD
T2DR
from
EC/R14
Timer0 (16bit)
Timer2(8bit)
Timer1(8bit)
TM01
7
0
TO U TS TO UTB
Edge
Selection
Polarity
Selection
-
T0INLIT T1INIT TO UT1 TO UT0
T0O UTP BTC
Tout
Logic
from
INT2/R12
(Capture Signal)
T0OUT
(R17)
Timer 01 mode register
TM01
R/W
7
R/W
6
TO UTS TO UTB
TOUT
(REMOUT)
5
-
R/W
4
R/W
3
T2OUT
(R15)
T1OUT
(R16)
R/W
2
R/W
1
R/W
0
T0INIT T1INIT TO UT1 TO UT0
T0OUTP BTCL
ADDRESS: 0DAH
INITIAL VALUE: 00H
REMOUT Port Output Selection
(TOUT Logic or TOUTB)
0: Bit(TOUTB) Output Through REMOUT
1: TOUT Logic Output Through REMOUT
TOUT LOGIC
00: AND of T0 OUTPUT and T1 OUTPUT
01: NAND of T0 OUTPUT and T1 OUTPUT
10: OR of T0 OUTPUT and T1 OUTPUT
11: NOR of T0 OUTPUT and T1 OUTPUT
REMOUT Port Bit Control
0: REMOUT Output Low
1: REMOUT Output High
Timer1 output initial value
0: Timer1 output low
1: Timer1 output high
T0OUT Polarity Selection
0: T0OUT Polarity Equal to TOUT Logic input signal
1: T0OUT Polarity Reverse to TOUT Logic input signal
Timer0 output initial value
0: Timer0 output low
1: Timer0 output high
Figure 13-1 Block Diagram of Timer/Counter
38
Sep. 2002 Ver 1.00
HMS81032ET
IEDS[5:4]
01
10
INT2/R12 PIN
IFINT2
INT2
INTERRUPT
11
MSB
16 BITS
T0HC
LSB
T0LC
[0D5H][0D6H]
capture
T0ST
CAP0
T0IFS
T 0 S L [2 :0 ]
E d g e D e te cto r
EC PIN
delay
P rescaler
P S 11
PS5
PS4
PS3
PS2
PS1
PS0
1
0
111
CAP0
clear
110
101
clear
Interrupt
GEN.
IFT0
OUTPUT
GEN.
T0OUT
T0 COUNTER (16-bit)
100
011
010
001
000
Comparator
MUX(16-bit)
1
MUX
0
T0MOD T0CN
T0INIT (refer to figure 13-1)
T0HMD
T0HLD
T0LMD
Timer 0 mode register
R/W
7
R/W
6
R/W
5
TM0
C AP0
T0ST
T0CN T0M O D T0IFS
BTC L T0SL2
R/W
4
R/W
3
T0LLD
[0D5H][0D6H]
[0D3H][0D4H]
R/W
2
R/W
1
R/W
0
T0SL1 T0SL0
ADDRESS: 0D0H
INITIAL VALUE: 00H
Timer0 input clock select (fXIN=4MHz)
000: PS0 250ns
001: PS1 500ns
010: PS2 1us
011: PS3 2us
100: PS4 4us
101: PS5 8us
110: PS11 512us
111: EC
Timer0 Interrupt select
0: Timer/Counter
1: Input capture (PS1:not supporting
input capture)
Timer0 Start/Stop control
0: Timer0 Stop
1: Tiemr0 Start after clear
Timer0 Counter Continuation/Pause Control
0: Count Pause
1: Count Continuation
Timer0 Interrupt select
0: Interrupt Every Count Overflow
1: Interrupt Every 2nd Count Overflow
Timer0 Single/Modulo-N select
0: Modulo-N
1: Single Mode
Figure 13-2 Block Diagram of Timer0
Sep. 2002 Ver 1.00
39
HMS81032ET
T1ST
T1IFS
T1 COUNT REG.
T 1S L [2 :0 ]
P rescaler
PS10
PS9
PS8
PS7
PS3
PS2
PS1
PS0
[0D8H]
1 11
1 10
1 01
clear
IFT1
OUTPUT
GEN.
T1OUT
T1 COUNTER (8-bit)
1 00
0 11
0 10
0 01
0 00
Comparator
1
MUX
MUX(8-bit) 0
T1MOD T1CN
T1INIT (refer to figure 13-1)
T1HD(8-bit)
[0D7H]
Timer 1 mode register
TM1
Interrupt
GEN.
R/W
7
R/W
6
R/W
5
T1LD(8-bit)
[0D8H]
R/W
4
3
R/W
2
T1CN T1M O D T1IFS BTCL
T1SL2
T1S T
R/W
1
R/W
0
T1S L1 T1SL0
ADDRESS: 0D1H
INITIAL VALUE: 00H
Timer1 Counter Continuation/Pause Control
0: Count Pause
1: Count Continuation
Timer1 input clock select (fXIN=4MHz)
000: PS0 250ns
001: PS1 500ns
010: PS2 1us
011: PS3 2us
100: PS7 32us
101: PS8 64us
110: PS9 128us
111: PS10 256us
Timer1 Single/Modulo-N select
0: Modulo-N
1: Single Mode
Timer1 Interrupt select
0: Interrupt Every Count Overflow
1: Interrupt Every 2nd Count Overflow
Timer1 Start/Stop control
0: Timer1 Stop
1: Tiemr1 Start after clear
Figure 13-3 Block Diagram of Timer1
40
Sep. 2002 Ver 1.00
HMS81032ET
T2ST
T2 COUNT REG.
T 2S L [2 :0 ]
P rescaler
PS12
PS11
PS10
PS9
PS8
PS7
PS6
PS5
[0D9H]
1 11
1 10
1 01
clear
Interrupt
GEN.
IFT2
OUTPUT
GEN.
T2OUT
T2 COUNTER (8-bit)
1 00
0 11
0 10
0 01
0 00
Comparator
T2DR
MUX
[0D9H]
T2CN
Timer 2 mode register
TM2
7
6
5
R/W
4
R/W
3
R/W
2
-
-
-
T2ST BTC
T2CN
L T2SL2
R/W
1
R/W
0
T2S L1 T2SL0
Timer2 Start/Stop control
0: Timer2 Stop
1: Tiemr2 Start after clear
Timer2 Counter Continuation/Pause Control
0: Count Pause
1: Count Continuation
ADDRESS: 0D2H
INITIAL VALUE: 00H
Timer2 input clock select (fXIN=4MHz)
000: PS5 8us
001: PS6 16us
010: PS7 32us
011: PS8 64us
100: PS9 128us
101: PS10 256us
110: PS11 512us
111: PS12 1,024us
Figure 13-4 Block Diagram of Timer2
Sep. 2002 Ver 1.00
41
HMS81032ET
2) Timer0, Timer1
TIMER0 and TIMER1 have an up-counter. When value of
the up-counter reaches the content of Timer Data Register
T0 Data
Register
Value
(TDR), the up-counter is cleared to “00h”, and interrupt
(IFT0, IFT1) is occurred at the next clock.
MATCH
(TDR = T0)
n
n
n-1
up
6
5
5
4
4
3
3
2
2
1
0
~~
6
T0 Value
~~
~~
up
-
-c
o
co
un
un
t
t
n-1
1
0
0
TIME
Interrupt period
Timer 0 (IFT0)
Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 13-5 Operation of Timer0
For Timer0, the internal clock (PS) and the external clock
(EC) can be selected as counter clock. But Timer1 and
Timer2 use only internal clock. As internal clock is chosen,
Timer0 can be used as internal-timer which period is determined by Timer Data Register (TDR). Chosen as external
clock, Timer0 executes as event-counter. The counter execution of Timer0 and Timer1 is controlled by T0CN,
T0ST, CAP0, T1CN, T1ST, of Timer Mode Register TM0
and TM1. T0CN, T1CN are used to stop and start Timer0
and Timer1 without clearing the counter. T0ST, T1ST is
42
used to clear the counter. For clearing and starting the
counter, T0ST or T1ST should be temporarily set to “0”
and then set to “1”. T0CN, T1CN, T0ST and T1ST should
be set “1”, when Timer counting-up. Controlling of CAP0
enables Timer0 as input capture. By programming of
CAP0 to “1”, the period of signal from INT2 can be measured and then, event counter value for INT2 can be read.
During counting-up, value of counter can be read. Timer
execution is stopped by the reset signal (RESET=”L”)
Sep. 2002 Ver 1.00
HMS81032ET
TDR
disable
~~
clear & start
enable
up
-c
ou
n
t
stop
~~
TIME
Timer 0 (IFT0)
Interrupt
Occur interrupt
Occur interrupt
T0ST
Start & Stop
T0ST = 1
T0ST = 0
T0CN
Control count
T0CN = 1
T0CN = 0
Figure 13-6 Start/Stop Operation of Timer0
T2
T3
T1
T0
INT2
Figure 13-7 Input capture operation of Timer0
Sep. 2002 Ver 1.00
43
HMS81032ET
3) Single/Modulo-N Mode
Timer0 (Timer1) can select initial output level of Timer
Output port by T0INIT, T1INIT of TM01. If initial level is
“L”, Low-Data Register value of Timer Data Register is
transferred to comparator and T0OUT (T1OUT) is to be
“Low”. If initial level is “High”, High -Data Register is
transferred and to be “High”. Single Mode can be set by
Mode Select bit (T0MOD, T1MOD) of Timer Mode Register (TM0, TM1) to “1”. When used as Single Mode, Timer counts up and compares with value of Data Register. If
the result is same, Time Out interrupt occurs and level of
Timer Output port toggle, then counter stops as reset state.
When used as Modulo-N Mode, T0MOD (T1MOD)
should be set “0”. Counter counts up until the value of Data
Register and occurs Time-out interrupt. The level of Timer
Output port toggle and repeats process of counting the value which is selected in Data Register. During Modulo-N
Mode, If interrupt select bit (T0IFS, T1IFS) of Mode Register is “0”, Interrupt occurs on every time-out. If it is “1”,
Interrupt occurs every second time-out.Timer output is
toggled whenever time-out happen.
[Single Mode]
8bit/16bit
counting
Timer Enable initial
value toggle
Timer-output toggle
Int. occurs
Count stop
[Module-N Mode]
8bit/16bit
counting
Timer Enable initial
value toggle
Timer-output toggle
Int. occurs (IFS=1) Each 2nd time out
Int. occurs (IFS=0) when Time out
Figure 13-8 Operation Diagram for Single/Modulo-N Mode
(4) Timer 2
Timer2 operates as an up-counter. The contents of T2DR
are compared with the contents of up-counter. If a match is
found, Timer2 interrupt (IFT2) is generated and the upcounter is cleared to “00h”. Therefore, Timer2 executes as
a interval timer. Interrupt period is determined by the count
source clock for the Timer2 and contents of T2DR.
44
When T2ST is set to “1”, count value of Timer 2 is cleared
and starts counting-up. For clearing and starting the
Timer2, T2ST have to set to “1” after set to “0”. In order to
write a value directly into the T2DR, T2ST should be set
to “0”. Counted value of Timer2 can be read at any time.
Sep. 2002 Ver 1.00
HMS81032ET
14. INTERRUPTS
The HMS81020ET/HMS81032ET interrupt circuits consist of Interrupt Mode Register (MOD), Interrupt enable
register (IENH, IENL), Interrupt request flags of IRQH,
IRQL, Priority circuit and Master enable flag ("I" flag of
PSW). 8 interrupt sources are provided. The configuration
of interrupt circuit is shown in Figure 14-1.
The HMS81020ET/HMS81032ET contains 8 interrupt
sources; 3 externals and 5 internals. Nested interrupt services with priority control is also possible. Software interrupt is non-maskable interrupt, the others are all maskable
interrupts.
- 8 interrupt source (2Ext, 3Timer, BIT, WDT and
Key Scan)
- 8 interrupt vector
- Nested interrupt control is possible
- Programmable interrupt mode
(Hardware and software interrupt accept mode)
- Read and write of interrupt request flag are possible.
- In interrupt accept, request flag is automatically cleared.
Internal Data Bus
00CEH
00CCH
0
IENL -
-
-
-
-
7
0
-
-
00CAH
0
7
-
7
IENH
-
-
IMOD
00CFH
IRQH
KSCN
.6&15
INT1R
INT2
INT2R
IFT0
T0R
IFT1
T1R
IFT2
T2R
IFWDT
I-flag
Priority Control
INT1
To CPU
Interrupt
V ector
A ddress
G enerator
8
IFBIT
RST
BITR
IRQL
00CDH
BRK
WDTR
Standby mode release
RESET
Figure 14-1 Block Diagram of Interrupt
Sep. 2002 Ver 1.00
45
HMS81032ET
14.1 Interrupt priority and sources
Each interrupt vector is independent and has its own priority. Software interrupt (BRK) is also available. Interrupt
source classification is shown in Table 14-1.
14.2 Interrupt control register
I flag of PSW is a interrupt mask enable flag. When I flag
= “0”, all interrupts become disable. When I flag = “1”, interrupts can be selectively enabled and disabled by contents of corresponding Interrupt Enable Register. When
interrupt is occurred, interrupt request flag is set, and Interrupt request is detected at the edge of interrupt signal. The
accepted interrupt request flag is automatically cleared
Mask
Non-maskable
Hardware Interrupt
Priority
during interrupt cycle process. The interrupt request flag
maintains “1” until the interrupt is accepted or is cleared in
program. In reset state, interrupt request flag register
(IRQH, IRQL) is cleared to “0”. It is possible to read the
state of interrupt register and to manipulate the contents of
register and to generate interrupt. (Refer to software interrupt)
Reset/Interrupt
Symbol
non-maskable
INT vector
low address
-
Hardware Reset
RESET
FFFFH
FFFEH
1
Key Scan
KSCNR
FFFBH
FFFAH
2
External Interrupt1
INT1R
FFF9H
FFF8H
3
External Interrupt2
INT2R
FFF7H
FFF6H
4
Timer0
T0R
FFF3H
FFF2H
5
Timer1
T1R
FFF1H
FFF0H
6
Timer2
T2R
FFEFH
FFEEH
7
Watch Dog Timer
WDTR
FFE9H
FFE8H
8
Basic Interval Timer
BITR
FFE7H
FFE6H
-
BRK Instruction
BRK
FFDFH
FFDEH
maskable
Software Interrupt
INT vector
high address
Table 14-1 Interrupt Source
46
Sep. 2002 Ver 1.00
HMS81032ET
-
IENL
R/W
R/W
WDTE
BITE
-
-
-
-
MSB
LSB
Watchdog timer
Basic Interval Timer
R/W
IENH
ADDRESS: 0CCH
INITIAL VALUE: -00- ----B
-
R/W
R/W
KSCNE INT1E INT2E
-
R/W
R/W
R/W
T0E
T1E
T2E
ADDRESS: 0CEH
INITIAL VALUE: 000- 000-B
-
MSB
VALUE
0: Disable
1: Enable
LSB
Key scan
Timer2
External interrupt 1
Timer1
External interrupt 2
Timer0
.
-
IRQL
R/W
R/W
WDTR
BITR
-
-
-
-
MSB
LSB
Watchdog timer
Basic Interval Timer
R/W
IRQH
ADDRESS: 0CDH
INITIAL VALUE: -00- ----B
-
R/W
R/W
KSCNR INT1R INT2R
-
R/W
R/W
R/W
T0R
T1R
T2R
MSB
ADDRESS: 0CFH
INITIAL VALUE: 000- 000-B
-
LSB
Key scan
Timer2
External interrupt 1
Timer1
External interrupt 2
Timer0
Figure 14-2 Interrupt Enable & Request Flag
14.3 Interrupt accept mode
The interrupt priority order is determined by bit (IM1,
IM0) of IMOD register. The condition allow for accepting
interrupt is set state of the interrupt mask enable flag and
Sep. 2002 Ver 1.00
the interrupt enable bit must be “1”. In Reset state, these
IP3 - IP0 registers become all “0”.
47
HMS81032ET
Interrupt mode register
IMOD
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
-
-
IM 1
IM 0
BTCL
IP 3
IP 2
IP1
IP0
Priority
00: Fixed by hardware
01: Changeable by IP3~IP0
1x: Interrupt is inhibited
ADDRESS: 0CAH
INITIAL VALUE: --000000B
Selection interrupt
0001: KSCNR
0010: INT1R
0011: INT2R
0101: T0R
0110: T1R
0111: T2R
1010: WDTR
1011: BITR
Figure 14-3 Interrupt Accept Mode & Selection by IP3~IP0
14.4 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the
interrupt latch is cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 8 fXIN after the completion of
the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction [RETI].
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to
“0” to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following
interrupts is temporarily disabled.
48
2. Interrupt request flag for the interrupt source accepted is
cleared to “0”.
3. The contents of the program counter (return address)
and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.
4. The entry address of the interrupt service program is
read from the vector table address and the entry address
is loaded to the program counter.
5. The instruction stored at the entry address of the interrupt service program is executed.
Sep. 2002 Ver 1.00
HMS81032ET
System clock
Instruction Fetch
SP
Address Bus
PC
Data Bus
Not used
SP-1
PCH
PCL
SP-2
PSW
V.L.
V.L.
V.H.
ADL
New PC
ADH
OP code
Internal Read
Internal Write
Interrupt Processing Step
Interrupt Service Task
V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.
Figure 14-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
External Interrupt1
Vector Table Address
0FFF8H
0FFF9H
012H
0E3H
Entry Address
0E312H
0E313H
0EH
2EH
the program status word are automatically saved on the stack, but
accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple
interrupt services are nested, it is necessary to avoid using the
same data memory area for saving registers.
The following method is used to save/restore the general-purpose
registers.
Example: Register save using push and pop instructions
Correspondence between vector table address for External Interrupt1
and the entry address of the interrupt service program.
INTxx:
A interrupt request is not accepted until the I-flag is set to “1”
even if a requested interrupt has higher priority than that of the
current interrupt being serviced.
When nested interrupt service is required, the I-flag should be set
to “1” by “EI” instruction in the interrupt service program. In this
case, acceptable interrupt sources are selectively enabled by the
individual interrupt enable flags.
PUSH
PUSH
PUSH
A
X
Y
;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.
interrupt processing
POP
POP
POP
RETI
Y
X
A
;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN
General-purpose register save/restore using push and pop instructions;
Saving/Restoring General-purpose Register
During interrupt acceptance processing, the program counter and
Sep. 2002 Ver 1.00
49
HMS81032ET
However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the Iflag is cleared to disable any further interrupt. But as user sets Iflag in interrupt routine, some further interrupt can be serviced
even if certain interrupt is in progress.
main task
acceptance of
interrupt
interrupt
service task
saving
registers
restoring
registers
interrupt return
14.5 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which has
the lowest priority order.
Interrupt vector address of BRK is shared with the vector of
TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from
TCALL 0.
Each processing step is determined by B-flag as shown in Figure
14-5
Example: During Timer1 interrupt is in progress, INT1 interrupt
serviced without any suspend.
TIMER1: PUSH
PUSH
PUSH
LDM
LDM
EI
:
:
:
:
LDM
LDM
POP
POP
POP
RETI
A
X
Y
IENH,#40H
IENL,#00H
IENH,#0FFH ;Enable all interrupts
IENL,#0FFH
Y
X
A
Main Program
service
B-FLAG
BRK or
TCALL0
;Enable INT1 only
;Disable other
;Enable Interrupt
=0
TIMER 1
service
enable INT1
disable other
=1
INT1
service
EI
BRK
INTERRUPT
ROUTINE
TCALL0
ROUTINE
RETI
RET
Occur
TIMER1 interrupt
Occur
INT1
enable INT1
enable other
Figure 14-5 Execution of BRK/TCALL0
14.6 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time
simultaneously, an internal polling sequence determines by hardware which request is serviced.
In this example, the INT1 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable “EI” in the TIMER1 routine.
Figure 14-6 Execution of Multi Interrupt
14.7 External Interrupt
The external interrupt on INT1 and INT2 pins are edge triggered
depending on the edge selection register IEDS (address 0D8H) as
50
shown in Figure14-7.
Sep. 2002 Ver 1.00
HMS81032ET
INT1 pin
IFINT1
INT1 INTERRUPT
INT2 pin
IFINT2
INT2 INTERRUPT
2
2
Edge selection
Register
IEDS
[0CBH]
Ext. Int. Edge Selection reg.
IEDS
7
6
-
-
W
5
W
4
W
3
W
2
IED2H IED 2L IE
BTCL
D1H IED1L
1
0
-
-
IED2*
01: Falling Edge Selection
10: Rising Edge Selection
11: Both Edge Selection
ADDRESS: 0CBH
INITIAL VALUE: --0000--B
IED1*
01: Falling Edge Selection
10: Rising Edge Selection
11: Both Edge Selection
Figure 14-7 External Interrupt Block Diagram
Response Time
The INT1 ~ INT2 edge are latched into IFINT1 ~ IFINT2 at every
machine cycle. The values are not actually polled by the circuitry
until the next machine cycle. If a request is active and conditions
are right for it to be acknowledged, a hardware subroutine call to
the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of
twelve complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution of the
first instruction of the service routine.
Figure 14-8 shows interrupt response timings.
max. 12 fXIN period
Interrupt Interrupt
goes
latched
active
8 fXIN period
Interrupt
processing
Interrupt
routine
Figure 14-8 Interrupt Response Timing Diagram
14.8 Key Scan Input Processing
Key Scan Interrupt is generated by detecting low or high
Input from each Input pin (R0, R1) is one of the sources
which release standby (SLEEP, STOP) mode. Key Scan
ports are all 16bit which are controlled by Standby Mode
Release Register (SMRR0, SMRR1). Key Input is considered as Interrupt, therefore, KSCNE bit of IEHN should be
Sep. 2002 Ver 1.00
set for correct interrupt executing, SLEEP mode and STOP
mode, the rest of executing is the same as that of external
Interrupt. Each SMRR Register bit is allowed for each port
(for Bit= “0”, no Key Input, for Bit= “1”, Key Input available). At reset, SMRR becomes “00h”. So, there is no Key
Input source.
51
HMS81032ET
Standby release level control register (SRLC) can select
the key scan input level “L” or “H” for standby release by
each bit pin (R0, R1). Standby release level control register
SMRR0
(SRLC) is write-only register and initialized as “00h” in reset state.
SRLC0
R00
R01
R 02
R 03
R 04
R 05
R 06
R 07
R0 PORT LOGIC
Internal
Key scan
Input
R10
R11
R 12
R 13
R 14
R 15
R 16
R 17
R1 PORT LOGIC
SMRR1
SMRR0
SRLC1
W
7
W
6
W
5
KR 07
KR 06
KR 05
W
4
W
3
W
2
K R04 BTCL
KR03 KR 02
W
1
W
0
K R01
K R00
W
1
W
0
K R11
K R10
W
1
W
0
ADDRESS: 0DCH
INITIAL VALUE: 00H
KR0[0:7]
1: Select
0: No S elect
SMRR1
W
7
W
6
W
5
KR 17
KR 16
KR 15
W
4
W
3
W
2
K R14 BTCL
KR13 KR 12
ADDRESS: 0DDH
INITIAL VALUE: 00H
KR1[0:7]
1: Select
0: No S elect
W
7
SRLC0
W
6
W
5
W
4
W
3
W
2
KLR07 K LR06 KLR05 KLR 04 BTCL
KLR03 K LR02 K LR01 K LR 00
ADDRESS: 0F6H
INITIAL VALUE: 00H
KLR [0:7]
1: High
0: Low
W
7
SRLC1
W
6
W
5
W
4
W
3
W
2
W
1
W
0
K LR 17 K LR 16 K LR15 KLR14 BTCL
K LR13 K LR 12 KLR 11 KLR10
ADDRESS: 0F7H
INITIAL VALUE: 00H
KLR1[0:7]
1: High
0: Low
Figure 14-9 Block Diagram of Key Scan Block
52
Sep. 2002 Ver 1.00
HMS81032ET
15. STANDBY FUNCTION
15.1 Sleep Mode
SLEEP mode can be entered by setting the bit of SLEEP
mode register (SLPM). In the mode, CPU clock stops but
oscillator keeps running. BIT and a part of peripheral hardware execute, but prescaler output which provide clock to
peripherals can be stopped by program. (Except, PS10
can’t stopped.) In SLEEP mode, more consuming power
can be saved by not using other peripheral hardware except
for BIT By setting ENPCK (peripheral clock control bit) of
CKCTLR (clock control register) to “0”, peripheral hardware halted, and SLEEP mode is entered. To release
SLEEP mode by BITR (basic interval timer interrupt),
bit10 of prescaler should be selected as BIT input clock before entering SLEEP mode. “NOP” instruction should be
follows setting of SLEEP mode for rising precharge time
of data bus line.
ADDRESS: 0F0H
INITIAL VALUE: -------0b
Sleep Mode Control Register (W)
-
SLPM
-
-
-
-
-
ADDRESS: 0C7H
INITIAL VALUE: --110111b
Clock Control Register (W)
CKCTLR
7
6
5
4
3
2
ENPCK
NOP
0
SLPM0
0: Sleep mode release
1: sleep mode
Example:
LDM
-
1
0
0: Stopped
1: Provided
SLPM, #01H ;setting of sleep
;mode
;NOP instruction
15.2 Stop Mode
STOP mode can be entered by STOP instruction during
program. In STOP mode, oscillator is stopped to make all
clocks stop, which leads to less power consumption. All
registers and RAM data are preserved. “NOP” instruction
should be follows STOP instruction for rising precharge
Sep. 2002 Ver 1.00
time of data bus line.
Example:
STOP
NOP
;STOP instruction
;NOP instruction
53
HMS81032ET
OSC
Circuit
Clock Pulse
G e nerator
CPU Clock
Clear
MUX
Basic
Interval
Timer
Prescaler
Clear
bit7
Clear
STOP
S
Q
Q
R
R
SLEEP
S
Overflow Detection
S
Q
R
Release Signal from Interrupt
RESETB
Figure 15-1 Block Diagram of Standby Circuit
15.3 Standby mode release
Release of STANDBY mode is executed by RESET input
and Interrupt signal. Register value is defined when Reset.
When there is a release signal of STOP mode (Interrupt,
RESET input), the instruction execution starts after stabilization oscillation time is set by value of BTS2 ~ BTS0
and set ENPCK to “1”.
Release Signal
SLEEP
STOP
RESET
O
O
KSCN(Key Input)
O
O
INT1,INT2
O
O
BIT, WDT
O
×
Table 15-1 Release Signal of Standby Mode
54
Sep. 2002 Ver 1.00
HMS81032ET
Release Factor
RESETB
KSCN(Key Input)
INT1,INT2
Release Method
By RESETB Pin=Low level, Standby mode is released and system is initialized
Standby mode is released by low input of selected pin by key scan Input(SMRR0,SMRR1).
In case of interrupt mask enable flag= “0”, program executes just after standby instruction,
if flag= “1” enters each interrupt service routine.
When external interrupt (INT1,INT2)enable flag is “1”, standby mode is released at the
rising edge of each terminal. When standby mode is released at interrupt. Mask Enable
flag= “0”, program executes from the next instruction of standby instruction. When “1”,
enters each interrupt service routine.
Basic Interval
Timer(IFBIT)
When BIT interrupt enable flag is “1”, SLEEP mode can be released by BIT overflow interrupt(IFBIT).
When SLEEP mode is released by interrupt. Mask enable flag= “0”, program executes
from the next instruction setting SLEEP mode. When “1”, enters each interrupt service routine.
Watch Dog
Timer(IFWDT)
When WDT interrupt enable flag is “1”, SLEEP mode can be released by WDT overflow
interrupt(IFWDT).
When SLEEP mode is released by interrupt. Mask enable flag= “0”, program executes
from the next instruction setting SLEEP mode. When “1”, enters each interrupt service routine.
Table 15-2 Standby mode release method
Sep. 2002 Ver 1.00
55
HMS81032ET
[SLEEP MODE]
SLEEP command
XIN
SLEEP mode
release by interrupt
RESET
Longer than 2 machine cycle
[STOP MODE]
XIN
STOP mode
Stable OSC.time
release by interrupt
Program setting time by CKCTLR
RESET
Longer than stable OSC. Time
Figure 15-2 Block Diagram of Standby Circuit
56
Sep. 2002 Ver 1.00
HMS81032ET
15.4 Operation of standby mode release
After standby mode is released, the operation begins according to content of related interrupt register just before
standby mode start (Figure 15-3).
STOP Command
Standby Mode
Interrupt Request GEN.
Int. enable reg.
0
1
Standby Mode Release
PSW
I Flag
0
1
Interrupt Service Routine
Standby Next Command
Execution
.
Figure 15-3 Standby Mode Release Flow
(1) Interrupt Enable Flag(I) of PSW = “0”
Release by only interrupt which interrupt enable flag =
“1”, and starts to execute from next to standby instruction
(SLEEP or STOP).
(2) Interrupt Enable Flag(I) of PSW = “1”
Note: When STOP instruction is used, BIT should guarantee the stabilization oscillation time. Thus, just before entering STOP mode, clock of bit10 (PS10) of prescaler is
selected or peripheral hardware clock control bit (ENPCK)
to “1”, Therefore the clock necessary for stabilization oscillation time should be input into BIT otherwise, standby
mode is released by reset signal. In case of interrupt request flag and interrupt enable flag are both “1”, standby
mode is not entered.
Released by only interrupt which each interrupt enable flag
= “1”, and jump to the relevant interrupt service routine.
Sep. 2002 Ver 1.00
57
HMS81032ET
Internal circuit
SLEEP mode
STOP mode
Oscillator
Active
Stop
Internal CPU
Stop
Stop
Register
Retained
Retained
RAM
Retained
Retained
I/O port
Retained
Retained
Prescaler
Active
Stop
Basic Interval Timer
PS10 selected:Active
Others: Stop
Stop
Watch-dog Timer
Active
Stop
Timer
Stop
Stop
Address Bus, Data Bus
Retained
Retained
Table 15-3 Operation State in Standby Mode
58
Sep. 2002 Ver 1.00
HMS81032ET
16. RESET FUNCTION
16.1 External RESET
The RESET pin should be held at low for at least 2machine
cycles with the power supply voltage within the operating
voltage range and must be connected 0.1uF capacitor for
stable system initialization. The RESET pin contains a
Schmitt trigger with an internal pull-up resistor.
RESET
0.1uF capacitor
GND
Figure 16-1 RESET Pin connection
16.2 Power on RESET
Power On Reset circuit automatically detects the rise of
power voltage (the rising time should be within 50ms) the
power voltage reaches a certain level, RESET terminal is
maintained at “L” Level until a crystal ceramic oscillator
oscillates stably. After power applies and starting of oscillation, this reset state is maintained for about oscillation
cycle of 219 (about 65.5ms: at 4MHz). The execution of
built-in Power On Reset circuit is as follows:
(1) Latch the pulse from Power On Detection Pulse Generator circuit, and reset Prescaler, BIT and BIT Overflow de-
Sep. 2002 Ver 1.00
tection circuit.
(2) Once BIT Overflow detection circuit is reset. Then,
Prescaler starts to count.
(3) Prescaler output is inputted into BIT and PS10 of Prescaler output is automatically selected. If overflow of BIT
is detected, Overflow detection circuit is set.
4) Reset circuit generates maximum period of reset pulse
from Prescaler and BIT
59
HMS81032ET
VDD
RESET
Internal Reset
Noise
Filter
0.1uF
GND
Q
Power on
Detect Pulse
Generator
R
S
SR Latch
GND
Clear
OSC
Prescaler
Circuit
Clear
Clear
PS10
Basic
Interval
MSB
Tim er
BIT
Overflow
Detection
Circuit
Figure 16-2 Block Diagram of Power On Reset Circuit
Note: When Power On Reset, oscillator stabilization time
doesn`t include OSC. Start time.
Prescaler Count Start
VDD
OSC. Start Time
Figure 16-3 Oscillator stabilizing diagram
60
Sep. 2002 Ver 1.00
HMS81032ET
1
?
?
4
5
6
7
~
~
?
?
FFFE FFFF Start
~
~ ~
~
?
?
?
?
FE
ADL
ADH
OP
~
~
DATA
BUS
3
~
~
RESET
ADDRESS
BUS
2
~
~
Oscillator
(XIN pin)
Stabilizing Time
RESET Process Step
MAIN PROGRAM
ADL and ADH are start addresses of interrupt service routine as vector contents.
Figure 16-4 Timing Diagram of Reset
16.3 Low voltage detection mode
(1) Low voltage detection condition
An on board voltage comparator checks that VDD is at the
required level to ensure correct operation of the device. If
VDD is below a certain level, Low voltage detector forces
the device into low voltage detection mode.
(2) Low Voltage Detection Mode
There is no power consumption except stop current, stop
mode release function is disabled. All I/O port is configured as input mode and Data memory is retained until voltage through external capacitor is worn out. In this mode,
Sep. 2002 Ver 1.00
all port can be selected with Pull-up resistor by Mask option. If there is no information on the Mask option sheet,
the default pull up option (all port connect to pull-up resistor) is selected.
(3) Release of Low Voltage Detection Mode
Reset signal result from new battery (normally 3V) wakes
the low voltage detection mode and come into normal reset
state. It depends on user whether to execute RAM clear
routine or not
61
HMS81032ET
LVD(V)
1.85
1.80
1.75
1.70
1.65
1.60
1.55
-25
-20 -15
-10
-5
0
5
10
15
20
25 30 35 40
Temperature (°C)
45
50
55
60
65
70
75
80
85
90
Figure 16-5 Low Voltage vs Temperature
(4)LVD Control register(LVDC)
LVDC
7
6
5
4
W
3
2
1
0
-
-
-
-
BTCL
LD
-
-
-
ADDRESS: 0F1H
INITIAL VALUE: ----0---B
LVD enable/disable bit when REMOUT outputs ‘High’
0: LVD enable
1: LVD disable at REMOUT=’H’
Figure 16-6 LVD control register(LVDC)
62
Sep. 2002 Ver 1.00
HMS81032ET
(5) SRAM BACK-UP after Low Voltage Detection.
about hours depend on VDD-GND capacitor
SRAM data backup
VDD
3V
Low voltage detection point
2V(Min.)
1.7V(typ.25°C )
Power on reset
(SRAM retention)
0.7V(VRET)
Power on reset
(SRAM unstable)
0V
Time
User replaces
batteries
User removes
batteries
Figure 16-7 Low voltage detection and protection
Interrupt
disable
Stop release
disable
All I/O port
input mode
Remout port
low level
OSC
STOP
All I/O port pull-up resistor
on
SRAM data
retention until VRET
Table 16-1 The operation after low voltage detection
Sep. 2002 Ver 1.00
63
HMS81032ET
(6) S/W flow chart example after Reset using SRAM Back-up
RESET
Stack Pointer initialize
Check the SRAM value
(RAM Pattern, Checksum)
N
SRAM DATA
VALID?
Y
Clear all Ram area
Use Saved SRAM value
Main routine
Figure 16-8 S/W flow chart example after Reset using SRAM Back-up
(7)Low voltage indication register(LVIR)
LVIR
7
6
5
4
3
2
R
1
R
0
-
-
-
-
BTC- L
-
LVI1
LV I0
Low voltage indication 1
0: VDD is above 2.0V (TYP.)
1: VDD is below 2.0V (TYP.)
ADDRESS: 0EFH
INITIAL VALUE: ------00B
Low voltage indication 0
0: VDD is above 2.2V (TYP.)
1: VDD is below 2.2V (TYP.)
Figure 16-9 Low voltage indication registor(LVIR)
Low voltage indication register(LVIR) is read only register. It is useful to display the consumption of batteries. If
VDD power level is below a certain level which is higher
than low voltage detection level, the bit of LVIR register
64
could be set according to the VDD level sequentially. The
VDD detection levels for indication are two, that is, Bit1
and Bit0 of LVIR registers. The detection levelof Bit0 is
higher than Bit1.
Sep. 2002 Ver 1.00
HMS81032ET
17. EPROM MODE
17.1 PIN ASSIGNMENT (Top View)
NC
NC
ALB
AHB
VDD
‘HIGH’
‘LOW’
A0/A8/D0
A1/A9/D1
A2/A10/D2
A3/A11/D3
MS
NC
NC
Sep. 2002 Ver 1.00
R13
R12
R11
R10
VDD
XOUT
XIN
R00
R01
R02
R03
R20
R21
R22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28PIN
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R14
R15
R16
R17
REMOUT
RESET
TEST
R07
R06
R05
R04
VSS
R24
R23
NC
NC
WEB
VEB
RDE
‘LOW’
VPP
D7/A15/A7
D6/A14/A6
D5/A13/A5
D4/A12/A4
GND
NC
NC
65
HMS81032ET
17.2 EPROM mode pin function
PIN NAME
PIN NUMBER
66
I/O TYPE
FUNCTION
-
-
-
R12
-
-
-
3
R11
ALB
INPUT
Address low input enable
4
R10
AHB
INPUT
Address high input enable
5
VDD
VDD
POWER
Positive power supply
6
XOUT
HIGH
OUTPUT
Logic high
7
XIN
LOW
INPUT
Logic low
8
R00
A0/A8/D0
I/O
9
R01
A1/A9/D1
I/O
10
R02
A2/A10/D2
I/O
11
R03
A3/A11/D3
I/O
12
R20
MS
INPUT
-
13
R21
-
-
-
14
R22
-
-
-
15
R23
-
-
-
16
R24
-
-
-
17
VSS
VSS
POWER
18
R04
A4/A12/D4
I/O
19
R05
A5/A13/D5
I/O
20
R06
A6/A14/D6
I/O
21
R07
A7/A15/D7
I/O
22
TEST
VPP
INPUT
Program voltage
23
RESET
LOW
INPUT
Logic low
24
REMOUT
RDE
INPUT
25
R17
VEB
INPUT
Verify enable
26
R16
WEB
INPUT
Program enable
27
R15
-
-
-
28
R14
-
-
-
STANDARD
MODE
EPROM MODE
1
R13
2
Input mode
- Address: 3~0
- Address: 11~8, Data:3~0
Output mode
- Data: 3~0
Ground
Input mode
- Address: 7~4
- Address: 15~12, Data:7~4
Output mode
- Data: 7~4
-
Sep. 2002 Ver 1.00
HMS81032ET
17.3 EPROM Mode setting
Setting mode
When setting mode
VPP
RDE
MS
VEB
WEB
ALB
AHB
PROM write & verify
11.5V
H
H
H
H
H
H
PROM verify
11.5V
H
H
H
H
H
H
LOCK bit write
11.5V
H
L
H
H
H
H
LOCK bit read
11.5V
H
L
H
H
H
H
Table 17-1 Setting mode
After setting mode
After setting mode
PROM write & verify
PROM verify
LOCK bit write
LOCK bit read
VPP
11.5V
11.5V
11.5V
11.5V
RDE
L
L
L
L
MS
H
H
L
L
VEB
WEB
ALB
AHB
Remark
H
H
H
L
Address high latch
H
H
L
H
Address low latch
H
L
H
H
PROM write
L
H
H
H
PROM verify
H
H
H
L
Address high latch
H
H
L
H
Address low latch
L
H
H
H
PROM verify
H
H
H
L
R0=6X: LOCK Bit
write data
H
L
H
H
program
H
H
H
L
LOCK latch
H
H
L
H
LOCK read
(R04 port high, R05 port low)
Table 17-2 after setting mode
Sep. 2002 Ver 1.00
67
HMS81032ET
17.4 General view of EPROM operation
Programming DC characteristics
(Ta= 25±5°°C))
Item
Symbol
Min.
Typ.
Max.
Unit
Test condition
Input ‘H’ voltage
VIH
4.5
VDD
VDD+0.3
V
-
Input ‘L’ voltage
VIL
-0.1
VSS
0.4
V
-
Output ‘H’ voltage
VOH
4.0
-
-
V
IOH = -2.5mA
Output ‘L’ voltage
VOL
-
-
0.4
V
IOL = 1mA
VDD current
IDD
-
-
100
mA
-
VPP current
IPP
-
-
100
mA
WEB=VIL
VDD voltage
VDD
4.5
5.0
5.5
V
-
VPP voltage
VPP
11.2
11.5
11.8
V
-
Table 17-3 Programming DC characteristics
Programming AC characteristics
(VDD=5.0V±0.5V, VPP =11.5V±0.3V, VSS =0V,Ta= 25±5°°C))
Item
Symbol
Min.
Typ.
Max.
Unit
High address setup time
TAHS
2
-
-
uS
High address pulse width
TAH
2
-
-
uS
High address hold time
TAHH
2
-
-
uS
Low address setup time
TALS
2
-
-
uS
Low address pulse width
TAL
2
-
-
uS
Low address hold time
TALH
2
-
-
uS
Program setup time
TWES
2
-
-
uS
Program pulse width
TWE
180
200
220
uS
Program hold time
TWEH
2
-
-
uS
Address delay time
TADD
-
-
170
nS
Data out delay time
TVED
-
-
150
nS
Data out time
TVE
2
-
-
uS
Data out floating time
TVEF
-
-
130
nS
Table 17-4 Programming AC characteristics
68
Sep. 2002 Ver 1.00
HMS81032ET
17.5 EPROM write & verify
VDD
5V
Min.
50ms
11.5V
VPP
(TEST)
0V
VSS
(RESET)
0V
RDE
(REMOUT)
Min.
2us
AHB
(R10)
Min.
10us
Latch Timing
‘H’
TAHH
TAHS TAH
ALB
(R11)
‘H’
WEB
(R16)
‘H’
Latch Timing
TALS
TAL
TALH
TWE
TWES
VEB
(R17)
‘H’
MS
(R20)
‘H’
TWEH
TVED
TVE TVEF
R0
[7:0]
AH
Mode selection
AL
DATA INPUT
1 Byte PGM
AH: High byte address input
AL: Low byte address input
DATA
OUTPUT
Verify
Repeat sector
1. AH and AL, inputs of R0[7:0] address are latched to IC at rising edge of R10 and R11.
2. DATA OUTPUT, output of R0[7:0] verify data is out during the period of R17 ‘Low’.
3. If writing is not completed in 200us of R16 ‘Low’ the action of repeat sector is done more again.
After confirming the writing success, it is repeated more 2 times. If the number of repeat action
is more 20, EPROM write & verify mode is failure.
4. When VPP is supplied, it is recommended to raise the voltage step by step for preventing voltage overshoot.
Figure 17-1 EPROM write & verify
Sep. 2002 Ver 1.00
69
HMS81032ET
17.6 EPROM verify
VDD
5V
Min.
50ms
11.5V
VPP
(TEST)
0V
VSS
(RESET)
0V
RDE
(REMOUT)
Min.
2us
AHB
(R10)
Min.
10us
Latch Timing
‘H’
TAHH
TAHS TAH
ALB
(R11)
Latch Timing
‘H’
TALS
TAL
WEB
(R16)
TALH
‘H’
TVED
VEB
(R17)
‘H’
TVE TVEF
MS
(R20)
‘H’
R0
[7:0]
AH
AL
Mode selection
DATA
OUTPUT
Verify
AH: High byte address input
AL: Low byte address input
1. AH and AL, inputs of R0[7:0] address are latched to IC at rising edge of R10 and R11.
2. DATA OUTPUT, output of R0[7:0] verify data is out during the period of R17 ‘Low’.
Figure 17-2 EPROM verify
70
Sep. 2002 Ver 1.00
HMS81032ET
17.7 LOCK bit write
VDD
5V
Min.
50ms
11.5V
VPP
(TEST)
0V
VSS
(RESET)
0V
RDE
(REMOUT)
Min.
2us
AHB
(R10)
Min.
10us
Latch Timing
‘H’
TAHH
TAHS TAH
ALB
(R11)
‘H’
WEB
(R16)
‘H’
VEB
(R17)
‘H’
MS
(R20)
‘H’
TWES
R0
[7:0]
TWE
TWEH
DIN
Mode selection
PGM
DIN=0110_XXXX: Lock bit write data
1. The steps of TWE is repeated 3 times. The period of TWE is 200us when R16 is ‘Low’
2. When VPP is supplied, it is recommended to raise the voltage step by step for preventing voltage overshoot.
Figure 17-3 LOCK bit write
Sep. 2002 Ver 1.00
71
HMS81032ET
17.8 LOCK bit read
VDD
5V
Min.
50ms
11.5V
VPP
(TEST)
0V
VSS
(RESET)
0V
RDE
(REMOUT)
Min.
2us
AHB
(R10)
‘H’
ALB
(R11)
‘H’
WEB
(R16)
‘H’
VEB
(R17)
‘H’
MS
(R20)
‘H’
Latch Timing
Min.
10us
TAHH
TAHS TAH
TADD TVE TVEH
TVED TVEF
R0
[7:0]
DOUT
Mode selection
LOCK Bit read
Lock bit write
Before
After
DOUT: Lock bit data output
R04
R05
L
H
H
L
1. Lock data is latched at rising edge of R10.
2. DOUT, output of R0[5:4] Lock bit read data, is out during the period of R11 ‘Low’
Figure 17-4 LOCK bit read
72
Sep. 2002 Ver 1.00
HMS81032ET
17.9 Considerations on programming
Writing must be occurred in recommended time and voltage. Programming voltage is 11.5V on EPROM mode. If
the voltage including the overshooting voltage is higher
than the recommendation, device will be broken out not to
be recoverable. When VPP is supplied, it is recommended
to raise the voltage step by step(0V→6V→10V→11.5V)
for preventing voltage overshoot. It is essential to check
the socket of EPROM writer and characteristics of socket
adapter before using them. If the user touch the socket
adapter or device on writing mode, writing error can be occurred by contact problem. Power capacitor and noise filtering capacitor should be located as near as possible from
VPP pin.
When the GANG writer is used writing pulse time(TWE) must have more 2us delay time per socket.
socket1
TWE
TWE
socket2
TWE
TWE
socket3
TWE
TWE
socket4
TWE
TWE
Min. 2us Delay
Min. 2us Delay
Figure 17-5 Writing pulse time
Sep. 2002 Ver 1.00
73
HMS81032ET
17.10 Programming flow chart
Start
Set EPROM write
to write/verify mode.
VDD=5V±0.5V
VPP=11.5V±0.3V
Start Address
n=0
n+1 → n
YES
N ≤ 20?
Data write:TWE=200us±10%
Verify
NO
Fail
Pass
Last Address?
NO
Address+1 → Address
YES
Set EPROM write
to verify mode.
high:VDD=5V±0.5V,VPP=11.5V
low:VDD=2.7V±0.5V,VPP=11.5V
Verify all address
Fail
Pass
Device pass
74
Device pass
Sep. 2002 Ver 1.00
HMS81032ET
18. Recommended circuit diagram of HMS81032ET
VDD
HMS81032ET
above 220 uF
1 R13
R14 24
2 R12
R15 23
3 R11
R16 22
4 R10
R17 21
5 VDD
REMOUT 20
Infrared LED
+ 0.1uF
about 1nF
TEST 18
R06 16
10 R02
R05 15
11 R03
R04 14
12 R20
VSS 13
1. Tr. and IR LED should be located as far as possible from the IC.
2. Power capacitor and noise filtering capacitor should be located
as near as possible from VDD pin.
3. Ceramic resonator should be located as near as possible from
the IC.
R10
9 R01
VSS
R11
R07 17
R12
8 R00
R13
Indicator LED
0.1uF
VDD
R14
7 XIN
VDD
RESET 19
R15
6 XOUT
R16
4 MHz
R17
DC 3V
alkaline battery
57
49
41 33
25
17
9
1
R00
58
50
42 34
26
18 10
2
R01
59
51
43 35
27
19 11
3
R02
60
52
44 36
28
20 12
4
R03
61
53
45 37
29
21 13
5
R04
62
54
46 38
30
22 14
6
R05
63
55
47 39
31
23 15
7
R06
64
56
48 40
32
24 16
8
R07
Figure 18-1 GENERAL CIRCUIT DIAGRAM OF HMS81032ET
Sep. 2002 Ver 1.00
75
HMS81032ET
76
Sep. 2002 Ver 1.00
HMS81032ET
APPENDIX
A. INSTRUCTION MAP
LOW 00000
HIGH
00
00001
01
SET1
dp.bit
00010
02
00011
03
BBS
BBS
A.bit,rel dp.bit,rel
00100
04
00101
05
00110
06
00111
07
01000
08
01001
09
ADC
#imm
ADC
dp
ADC
dp+X
ADC
!abs
ASL
A
ASL
dp
01010
0A
01011
0B
01100
0C
01101
0D
01110
0E
01111
0F
TCALL SETA1
0
.bit
BIT
dp
POP
A
PUSH
A
BRK
000
-
001
CLRC
SBC
#imm
SBC
dp
SBC
dp+X
SBC
!abs
ROL
A
ROL
dp
TCALL CLRA1
2
.bit
COM
dp
POP
X
PUSH
X
BRA
rel
010
CLRG
CMP
#imm
CMP
dp
CMP
dp+X
CMP
!abs
LSR
A
LSR
dp
TCALL
4
NOT1
M.bit
TST
dp
POP
Y
PUSH
Y
PCALL
Upage
011
DI
OR
#imm
OR
dp
OR
dp+X
OR
!abs
ROR
A
ROR
dp
TCALL
6
OR1
OR1B
CMPX
dp
POP
PSW
PUSH
PSW
RET
100
CLRV
AND
#imm
AND
dp
AND
dp+X
AND
!abs
INC
A
INC
dp
TCALL AND1
8
AND1B
CMPY
dp
CBNE
dp+X
TXSP
INC
X
101
SETC
EOR
#imm
EOR
dp
EOR
dp+X
EOR
!abs
DEC
A
DEC
dp
TCALL EOR1
10
EOR1B
DBNE
dp
XMA
dp+X
TSPX
DEC
X
110
SETG
LDA
#imm
LDA
dp
LDA
dp+X
LDA
!abs
TXA
LDY
dp
TCALL
12
LDC
LDCB
LDX
dp
LDX
dp+Y
XCN
DAS
111
EI
LDM
dp,#imm
STA
dp
STA
dp+X
STA
!abs
TAX
STY
dp
TCALL
14
STC
M.bit
STX
dp
STX
dp+Y
XAX
STOP
10011
13
10100
14
10101
15
10110
16
10111
17
11000
18
11001
19
11010
1A
11011
1B
11100
1C
11101
1D
11110
1E
11111
1F
ADC
{X}
ADC
!abs+Y
ADC
[dp+X]
ADC
[dp]+Y
ASL
!abs
ASL
dp+X
TCALL
1
JMP
!abs
BIT
!abs
ADDW
dp
LDX
#imm
JMP
[!abs]
TEST
!abs
SUBW
dp
LDY
#imm
JMP
[dp]
TCLR1 CMPW
!abs
dp
CMPX
#imm
CALL
[dp]
LOW 10000
HIGH
10
10001
11
10010
12
000
BPL
rel
001
BVC
rel
SBC
{X}
SBC
!abs+Y
SBC
[dp+X]
SBC
[dp]+Y
ROL
!abs
ROL
dp+X
TCALL
3
CALL
!abs
010
BCC
rel
CMP
{X}
CMP
!abs+Y
CMP
[dp+X]
CMP
[dp]+Y
LSR
!abs
LSR
dp+X
TCALL
5
MUL
011
BNE
rel
OR
{X}
OR
!abs+Y
OR
[dp+X]
OR
[dp]+Y
ROR
!abs
ROR
dp+X
TCALL
7
DBNE
Y
CMPX
!abs
LDYA
dp
CMPY
#imm
RETI
100
BMI
rel
AND
{X}
AND
!abs+Y
AND
[dp+X]
AND
[dp]+Y
INC
!abs
INC
dp+X
TCALL
9
DIV
CMPY
!abs
INCW
dp
INC
Y
TAY
101
BVS
rel
EOR
{X}
EOR
!abs+Y
EOR
[dp+X]
EOR
[dp]+Y
DEC
!abs
DEC
dp+X
TCALL
11
XMA
{X}
XMA
dp
DECW
dp
DEC
Y
TYA
110
BCS
rel
LDA
{X}
LDA
!abs+Y
LDA
[dp+X]
LDA
[dp]+Y
LDY
!abs
LDY
dp+X
TCALL
13
LDA
{X}+
LDX
!abs
STYA
dp
XAY
DAA
111
BEQ
rel
STA
{X}
STA
!abs+Y
STA
[dp+X]
STA
[dp]+Y
STY
!abs
STY
dp+X
TCALL
15
STA
{X}+
STX
!abs
CBNE
dp
XYX
NOP
CLR1
BBC
BBC
dp.bit
A.bit,rel
dp.bit,rel
Sep. 2002 Ver 1.00
i
HMS81032ET
B. INSTRUCTION SET
1. ARITHMETIC/ LOGIC OPERATION
NO.
ii
MNEMONIC
OP BYTE CYCLE
CODE NO
NO
04
2
2
1
ADC #imm
2
ADC dp
05
2
3
3
ADC dp + X
06
2
4
4
ADC !abs
07
3
4
5
ADC !abs + Y
15
3
5
6
ADC [ dp + X ]
16
2
6
7
ADC [ dp ] + Y
17
2
6
8
ADC { X }
14
1
3
9
AND #imm
AND dp
84
2
2
10
85
2
3
11
AND dp + X
86
2
4
12
AND !abs
87
3
4
13
AND !abs + Y
95
3
5
14
AND [ dp + X ]
96
2
6
15
AND [ dp ] + Y
97
2
6
16
AND { X }
94
1
3
17
ASL A
08
1
2
18
19
ASL dp
ASL dp + X
09
19
2
2
4
5
20
ASL !abs
18
3
5
21
CMP #imm
44
2
2
22
CMP dp
45
2
3
23
CMP dp + X
46
2
4
24
CMP !abs
47
3
4
25
CMP !abs + Y
55
3
5
26
CMP [ dp + X ]
56
2
6
27
CMP [ dp ] + Y
57
2
6
28
CMP { X }
54
1
3
29
CMPX #imm
5E
2
2
30
CMPX dp
6C
2
3
31
CMPX !abs
7C
3
4
32
CMPY #imm
7E
2
2
33
CMPY dp
8C
2
3
34
CMPY !abs
9C
3
4
35
COM dp
2C
2
4
FLAG
NVGBHIZC
OPERATION
Add with carry.
A←(A)+(M)+C
NV--H-ZC
Logical AND
A← (A)∧(M)
N-----Z-
Arithmetic shift left
C
7
6
5
4
3
2
1
N-----ZC
0
“0”
Compare accumulator contents with memory contents
(A) -(M)
N-----ZC
Compare X contents with memory contents
(X)-(M)
N-----ZC
Compare Y contents with memory contents
(Y)-(M)
N-----ZC
1’S Complement : ( dp ) ← ~( dp )
N-----Z-
36
DAA
DF
1
3
Decimal adjust for addition
N-----ZC
37
DAS
CF
1
3
Decimal adjust for subtraction
N-----ZC
38
DEC A
A8
1
2
Decrement
N-----Z-
39
DEC dp
A9
2
4
40
DEC dp + X
B9
2
5
41
DEC !abs
B8
3
5
42
DEC X
AF
1
2
43
DEC Y
BE
1
2
44
DIV
9B
1
12
M← (M)-1
N-----Z-
Divide : YA / X Q: A, R: Y
NV--H-Z-
Sep. 2002 Ver 1.00
HMS81032ET
NO.
MNEMONIC
45
EOR #imm
46
EOR dp
47
EOR dp + X
OP BYTE CYCLE
OPERATION
CODE NO
NO
A4
2
2
Exclusive OR
A5
2
3
A← (A)⊕(M)
A6
2
FLAG
NVGBHIZC
4
48
EOR !abs
A7
3
4
49
EOR !abs + Y
B5
3
5
50
EOR [ dp + X ]
B6
2
6
51
EOR [ dp ] + Y
B7
2
6
52
EOR { X }
B4
1
3
N-----Z-
53
INC A
88
1
2
54
INC dp
89
2
4
55
INC dp + X
99
2
5
56
INC !abs
98
3
5
57
INC X
8F
1
2
58
INC Y
9E
1
2
59
LSR A
48
1
2
60
LSR dp
49
2
4
61
LSR dp + X
59
2
5
62
LSR !abs
58
3
5
63
MUL
5B
1
9
Multiply : YA ← Y × A
64
OR #imm
64
2
2
Logical OR
65
OR dp
65
2
3
66
OR dp + X
66
2
4
67
OR !abs
67
3
4
68
OR !abs + Y
75
3
5
69
OR [ dp + X ]
76
2
6
70
OR [ dp ] + Y
77
2
6
71
OR { X }
74
1
3
72
ROL A
28
1
2
73
ROL dp
29
2
4
74
ROL dp + X
39
2
5
75
ROL !abs
38
3
5
76
ROR A
68
1
2
77
ROR dp
69
2
4
78
ROR dp + X
79
2
5
79
ROR !abs
78
3
5
Increment
N-----Z-
M← (M)+1
N-----Z-
Logical shift right
7
6
5
4
3
2
1
0
C
N-----ZC
“0”
N-----Z-
A ← (A)∨(M)
N-----Z-
Rotate left through carry
C
7
6
5
4
3
2
1
0
N-----ZC
Rotate right through carry
7
6
5
4
3
2
1
0
C
N-----ZC
80
SBC #imm
24
2
2
81
SBC dp
25
2
3
82
SBC dp + X
26
2
4
83
SBC !abs
27
3
4
84
SBC !abs + Y
35
3
5
85
SBC [ dp + X ]
36
2
6
86
SBC [ dp ] + Y
37
2
6
87
SBC { X }
34
1
3
88
TST dp
4C
2
3
Test memory contents for negative or zero
( dp ) - 00H
N-----Z-
89
XCN
CE
1
5
Exchange nibbles within the accumulator
A7~A4 ↔ A3~A0
N-----Z-
Sep. 2002 Ver 1.00
Subtract with carry
A ← ( A ) - ( M ) - ~( C )
NV--HZC
iii
HMS81032ET
2. REGISTER / MEMORY OPERATION
NO.
iv
MNEMONIC
OP
BYTE CYCLE
CODE NO
NO
C4
2
2
FLAG
NVGBHIZC
OPERATION
1
LDA #imm
2
LDA dp
C5
2
3
3
LDA dp + X
C6
2
4
4
LDA !abs
C7
3
4
5
LDA !abs + Y
D5
3
5
6
LDA [ dp + X ]
D6
2
6
7
LDA [ dp ] + Y
D7
2
6
8
LDA { X }
D4
1
3
9
LDA { X }+
DB
1
4
X- register auto-increment : A ← ( M ) , X ← X + 1
10
LDM dp,#imm
E4
3
5
Load memory with immediate data : ( M ) ← imm
11
LDX #imm
1E
2
2
Load X-register
12
LDX dp
CC
2
3
13
LDX dp + Y
CD
2
4
14
LDX !abs
DC
3
4
15
LDY #imm
3E
2
2
16
LDY dp
C9
2
3
17
LDY dp + X
D9
2
4
18
LDY !abs
D8
3
4
19
STA dp
E5
2
4
20
STA dp + X
E6
2
5
21
STA !abs
E7
3
5
22
STA !abs + Y
F5
3
6
23
STA [ dp + X ]
F6
2
7
24
STA [ dp ] + Y
F7
2
7
25
STA { X }
F4
1
4
Load accumulator
A←(M)
N-----Z-
X ←(M)
-------N-----Z-
Load Y-register
Y←(M)
N-----Z-
Store accumulator contents in memory
(M)←A
--------
26
STA { X }+
FB
1
4
X- register auto-increment : ( M ) ← A, X ← X + 1
27
STX dp
EC
2
4
Store X-register contents in memory
28
STX dp + Y
ED
2
5
29
STX !abs
FC
3
5
30
STY dp
E9
2
4
31
STY dp + X
F9
2
5
32
STY !abs
F8
3
5
33
TAX
E8
1
2
Transfer accumulator contents to X-register : X ← A
N-----Z-
34
TAY
9F
1
2
Transfer accumulator contents to Y-register : Y ← A
N-----Z-
(M)← X
--------
Store Y-register contents in memory
(M)← Y
--------
35
TSPX
AE
1
2
Transfer stack-pointer contents to X-register : X ← sp
N-----Z-
36
TXA
C8
1
2
Transfer X-register contents to accumulator: A ← X
N-----Z-
37
TXSP
8E
1
2
Transfer X-register contents to stack-pointer: sp ← X
N-----Z-
38
TYA
BF
1
2
Transfer Y-register contents to accumulator: A ← Y
N-----Z-
39
XAX
EE
1
4
Exchange X-register contents with accumulator :X ↔ A
--------
40
XAY
DE
1
4
Exchange Y-register contents with accumulator :Y ↔ A
--------
41
XMA dp
BC
2
5
Exchange memory contents with accumulator
42
XMA dp+X
AD
2
6
43
XMA {X}
BB
1
5
44
XYX
FE
1
4
(M)↔A
N-----Z-
Exchange X-register contents with Y-register : X ↔ Y
--------
Sep. 2002 Ver 1.00
HMS81032ET
3. 16-BIT OPERATION
NO.
MNEMONIC
OP BYTE CYCLE
CODE NO
NO
OPERATION
FLAG
NVGBHIZC
1
ADDW dp
1D
2
5
16-Bits add without carry
YA ← ( YA ) + ( dp +1 ) ( dp )
2
CMPW dp
5D
2
4
Compare YA contents with memory pair contents :
(YA) − (dp+1)(dp)
N-----ZC
3
DECW dp
BD
2
6
Decrement memory pair
( dp+1)( dp) ← ( dp+1) ( dp) - 1
N-----Z-
4
INCW dp
9D
2
6
Increment memory pair
( dp+1) ( dp) ← ( dp+1) ( dp ) + 1
N-----Z-
5
LDYA dp
7D
2
5
Load YA
YA ← ( dp +1 ) ( dp )
N-----Z-
6
STYA dp
DD
2
5
Store YA
( dp +1 ) ( dp ) ← YA
--------
7
SUBW dp
3D
2
5
16-Bits substact without carry
YA ← ( YA ) - ( dp +1) ( dp)
NV--H-ZC
NV--H-ZC
4. BIT MANIPULATION
NO.
MNEMONIC
OP BYTE CYCLE
OPERATION
CODE NO
NO
8B
3
4
Bit AND C-flag : C ← ( C ) ∧ ( M .bit )
1
AND1 M.bit
2
AND1B M.bit
8B
3
4
Bit AND C-flag and NOT : C ← ( C ) ∧ ~( M .bit )
3
BIT dp
0C
2
4
Bit test A with memory :
4
FLAG
NVGBHIZC
-------C
-------C
MM----Z-
BIT !abs
1C
3
5
Z ← ( A ) ∧ ( M ) , N ← ( M7 ) , V ← ( M6 )
5
CLR1 dp.bit
y1
2
4
Clear bit : ( M.bit ) ← “0”
6
CLRA1 A.bit
2B
2
2
Clear A bit : ( A.bit )← “0”
--------
7
CLRC
20
1
2
Clear C-flag : C ← “0”
-------0
--------
8
CLRG
40
1
2
Clear G-flag : G ← “0”
--0-----
9
CLRV
80
1
2
Clear V-flag : V ← “0”
-0--0---
10
EOR1 M.bit
AB
3
5
Bit exclusive-OR C-flag : C ← ( C ) ⊕ ( M .bit )
-------C
EOR1B M.bit
AB
3
5
Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M .bit)
-------C
11
12
LDC M.bit
CB
3
4
Load C-flag : C ← ( M .bit )
-------C
13
LDCB M.bit
CB
3
4
Load C-flag with NOT : C ← ~( M .bit )
-------C
14
NOT1 M.bit
4B
3
5
Bit complement : ( M .bit ) ← ~( M .bit )
--------
15
OR1 M.bit
6B
3
5
Bit OR C-flag : C ← ( C ) ∨ ( M .bit )
-------C
16
-------C
OR1B M.bit
6B
3
5
Bit OR C-flag and NOT : C ← ( C ) ∨ ~( M .bit )
17
SET1 dp.bit
x1
2
4
Set bit : ( M.bit ) ← “1”
--------
18
SETA1 A.bit
0B
2
2
Set A bit : ( A.bit ) ← “1”
--------
19
SETC
A0
1
2
Set C-flag : C ← “1”
-------1
20
SETG
C0
1
2
Set G-flag : G ← “1”
--1-----
21
STC M.bit
EB
3
6
Store C-flag : ( M .bit ) ← C
-------N-----ZN-----Z-
22
TCLR1 !abs
5C
3
6
Test and clear bits with A :
A - ( M ) , ( M ) ← ( M ) ∧ ~( A )
23
TSET1 !abs
3C
3
6
Test and set bits with A :
A-(M), (M)← (M)∨(A)
Sep. 2002 Ver 1.00
v
HMS81032ET
5. BRANCH / JUMP OPERATION
NO.
1
BBC A.bit,rel
2
BBC dp.bit,rel
OP BYTE CYCLE
OPERATION
CODE NO
NO
y2
2
4/6
Branch if bit clear :
y3
3
5/7
if ( bit ) = 0 , then pc ← ( pc ) + rel
FLAG
NVGBHIZC
--------
3
BBS A.bit,rel
x2
2
4/6
Branch if bit set :
4
BBS dp.bit,rel
x3
3
5/7
if ( bit ) = 1 , then pc ← ( pc ) + rel
5
BCC rel
50
2
2/4
Branch if carry bit clear
if ( C ) = 0 , then pc ← ( pc ) + rel
--------
6
BCS rel
D0
2
2/4
Branch if carry bit set
if ( C ) = 1 , then pc ← ( pc ) + rel
--------
7
BEQ rel
F0
2
2/4
Branch if equal
if ( Z ) = 1 , then pc ← ( pc ) + rel
--------
8
BMI rel
90
2
2/4
Branch if minus
if ( N ) = 1 , then pc ← ( pc ) + rel
--------
9
BNE rel
70
2
2/4
Branch if not equal
if ( Z ) = 0 , then pc ← ( pc ) + rel
--------
10
BPL rel
10
2
2/4
Branch if minus
if ( N ) = 0 , then pc ← ( pc ) + rel
--------
11
BRA rel
2F
2
4
Branch always
pc ← ( pc ) + rel
--------
12
BVC rel
30
2
2/4
Branch if overflow bit clear
if (V) = 0 , then pc ← ( pc) + rel
--------
13
BVS rel
B0
2
2/4
Branch if overflow bit set
if (V) = 1 , then pc ← ( pc ) + rel
--------
14
CALL !abs
3B
3
8
Subroutine call
15
CALL [dp]
5F
2
8
M( sp)←( pcH ), sp←sp - 1, M(sp)← (pcL), sp ←sp - 1,
if !abs, pc← abs ; if [dp], pc L← ( dp ), pcH← ( dp+1 ) .
--------
16
CBNE dp,rel
FD
3
5/7
Compare and branch if not equal :
--------
17
CBNE dp+X,rel
8D
3
6/8
18
DBNE dp,rel
AC
3
5/7
Decrement and branch if not equal :
DBNE Y,rel
7B
2
4/6
if ( M ) ≠ 0 , then pc ← ( pc ) + rel.
19
vi
MNEMONIC
--------
if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel.
--------
20
JMP !abs
1B
3
3
21
JMP [!abs]
1F
3
5
22
JMP [dp]
3F
2
4
23
PCALL upage
4F
2
6
U-page call
M(sp) ←( pcH ), sp ←sp - 1, M(sp) ← ( pcL ),
sp ← sp - 1, pcL ← ( upage ), pcH ← ”0FFH” .
--------
24
TCALL n
nA
1
8
Table call : (sp) ←( pcH ), sp ← sp - 1,
M(sp) ← ( pcL ),sp ← sp - 1,
pcL ← (Table vector L), pcH ← (Table vector H)
--------
Unconditional jump
pc ← jump address
--------
Sep. 2002 Ver 1.00
HMS81032ET
6. CONTROL OPERATION & etc.
NO.
MNEMONIC
OPERATION
FLAG
NVGBHIZC
0F
1
8
Software interrupt : B ← ”1”, M(sp) ← (pcH), sp ←sp-1,
M(s) ← (pcL), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1,
pcL ← ( 0FFDEH ) , pcH ← ( 0FFDFH) .
DI
60
1
3
Disable interrupts : I ← “0”
-----0--
EI
E0
1
3
Enable interrupts : I ← “1”
-----1--
NOP
FF
1
2
No operation
--------
POP A
0D
1
4
sp ← sp + 1, A ← M( sp )
1
BRK
2
3
4
5
OP BYTE CYCLE
CODE NO
NO
6
POP X
2D
1
4
sp ← sp + 1, X ← M( sp )
7
POP Y
4D
1
4
sp ← sp + 1, Y ← M( sp )
8
POP PSW
6D
1
4
sp ← sp + 1, PSW ← M( sp )
9
PUSH A
0E
1
4
M( sp ) ← A , sp ← sp - 1
10
---1-0--
-------restored
PUSH X
2E
1
4
M( sp ) ← X , sp ← sp - 1
11
PUSH Y
4E
1
4
M( sp ) ← Y , sp ← sp - 1
12
PUSH PSW
6E
1
4
M( sp ) ← PSW , sp ← sp - 1
--------
--------
13
RET
6F
1
5
Return from subroutine
sp ← sp +1, pcL ← M( sp ), sp ← sp +1, pcH ← M( sp )
14
RETI
7F
1
6
Return from interrupt
sp ← sp +1, PSW ← M( sp ), sp ← sp + 1,
pcL ← M( sp ), sp ← sp + 1, pcH ← M( sp )
restored
15
STOP
EF
1
3
Stop mode ( halt CPU, stop oscillator )
--------
Sep. 2002 Ver 1.00
vii