ETC PI74ALVCH16524

PI74ALVCH16524
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18-Bit Registered Bus Transceiver
With 3-State Outputs
Product Features
Product Description
• PI74ALVCH16524 is designed for low voltage operation
• VCC = 2.3V to 3.6V
• Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• Bus Hold retains last active bus state during 3-State
eliminating the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced using the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH16524 data flow in each direction is controlled
by output-enable (OEAB and OEBA) and clock-enable
(CLKENBA) inputs. For the A-to-B data flow, the data flows
through a single buffer. The B-to-A data can flow through a fourstage pipeline register path, or through a single register path,
depending on the state of the select (SEL) input.
Data is stored in the internal registers on the low-to-high
transition of the clock (CLK) input, provided that the appropriate
CLKENBA input is low. The B-to-A data transfer is synchronized
with CLK.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pull-up resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The PI74ALVCH16524 has “Bus Hold” which retains the data
input’s last state whenever the data input goes to high-impedance
preventing “floating” inputs and eliminating the need for pullup/
down resistors.
Logic Block Diagram
CLK
CLKENBA
30
28
2
OEAB
OEBA
SEL
27
55
1 of 18 Channels
G1
CE
A1
3
C1
1D
1
1
CE
CE
C1
1D
C1
1D
CE
C1
1D
54
B1
To 17 Other Channels
1
PS8447A
11/06/00
PI74ALVCH16524
18-Bit Registered Bus Transceiver
with 3-State Outputs
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Product Pin Description
Pin Name
CLKEN
SEL
CLK
Ax
Bx
GND
VCC
Truth Table(1)† B to A Storage (OEBA = L)
Description
Clock Enable Input (Active LOW)
Select (Active LOW)
Clock Input (Active HIGH)
Data I/O
Data I/O
Ground
Power
Inputs
Product Pin Configuration
GND
56
55
3
4
5
54
53
52
51
50
49
B3
A4
6
7
8
A5
A6
9
10
48
47
B5
GND
11
12
13
A1
GND
A2
A3
VCC
A7
A8
A9
56-Pin 46
A,V
45
44
SEL
B1
GND
B2
VCC
B4
B11
40
39
B12
19
20
21
38
37
36
B13
B14
22
23
24
35
34
33
VCC
A18
25
26
32
31
GND
B18
OEBA
CLKENBA
27
28
30
29
CLK
A14
A15
VCC
A16
A17
GND
X
X
X
A0‡
L
­
H
L
L
L
­
H
H
H
L
­
L
L
L§
L
­
L
H
H§
B8
B9
17
18
A13
H
B7
41
GND
B
GND
43
42
A12
SEL
B6
14
15
16
A10
A11
CLK
Note:
1. H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑ = LOW-to-HIGH Transition
‡ Output level before the indicated steady-state input
conditions were established.
§ Four positive CLK edges are needed to propagate
data from B to A when SEL is low.
GND
1
2
OEAB
CLKENBA
Outputs
A
B10
GND
B15
B16
B17
GND
2
PS8447A
11/06/00
PI74ALVCH16524
18-Bit Registered Bus Transceiver
with 3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................................. –65°C to +150°C
Supply Voltage Range, VCC .................................................... –0.5V to 4.6V
Input Voltage Range,VI: Except
I/O ports(1) .................................................................................. –0.5V to 4.6V
I/O ports(1,2) ................................................................... –0.5V to VCC + 0.5V
Output Voltage Range, VO(1,2) .................................. –0.5V to VCC + 0.5V
Input Clamp current, IIK (VI < 0) ................................................ –50mA
Output Clamp current, IOK (VO < 0) ........................................... –50mA
Continous Output Current, IO ................................................... ±50mA
Continous Current through each VCC or GND ........................ ±100mA
Maximum Power Dissipation:
A package ........................................................................................ 1W
V package ..................................................................................... 1.4W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Notes:
1. The input and output negative-voltage ratings maybe exceeded if the input and
outputclamp-current ratings are observed.
2. This value is limited to 4.6V maximum.
Recommended Operating Conditions(1)
Parame te rs
De s cription
Te s t Conditions
M in.
Typ.
VCC
Supply Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIN
Input Voltage
0
VCC
VOUT
Output Voltage
0
VCC
IOH
IOL
TA
∆t/∆v(2)
High- level Output Current
Low- level Output Current
2.3
M ax.
VCC = 2.3V to 2.7V
1.7
VCC = 2.7V to 3.6V
2.0
3.6
VCC = 2.3V to 2.7V
0.7
VCC = 2.7V to 3.6V
0.8
VCC = 2.3V
–12
VCC = 2.7V
–12
VCC = 3.0V
–24
VCC = 2.3V
12
VCC = 2.7V
12
VCC = 3.0V
24
Operating Free- Air Temperature
–40
Input Transition Rise or Fall
Units
V
mA
85
°C
10
ns/V
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
2. See test circuit and waveforms.
3
PS8447A
11/06/00
PI74ALVCH16524
18-Bit Registered Bus Transceiver
with 3-State Outputs
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DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%)
Parame te rs
VCC(1)
M in.
Min. to Max.
VCC - 0.2
VIH = 1.7V
2.3V
2.0
VIH = 1.7V
2.3V
1.7
VIH = 2.0V
2.7V
2.2
VIH = 2.0V
3.0V
2.4
VIH = 2.0V
3.0V
2.0
Te s t Conditions
IOH = - 100 µA
IOH = - 6 MA
VOH
IOH = - 12 mA
IOH = - 24 mA
IOL = 100 µA
VOL
IOL = 6 mA
IOL = 12 mA
IOL = 24 mA
II
V
Min. to Max.
0.2
VIL = 0.7V
2.3V
0.4
VIL = 0.7V
2.3V
0.7
VIL = 0.8V
2.7V
0.4
VIL = 0.8V
3.0V
0.55
3.6V
±5
VI = VCC or GND
VI = 0.7V
2.3V
VI = 1.7V
II (Hold)(3)
Typ.(2) M ax. Units
VI = 0.8V
3.0V
VI = 2.0V
45
- 45
75
µA
- 75
VI = 0 to 3.6V
3.6V
±500
IOZ(4)
VO = VCC or GND
3.6V
±10
ICC
VI = VCC or GND
3.6V
40
∆ICC
One input at VCC - 0.6V, Other inputs at VCC or GND
3V to 3.6V
750
CI Control Inputs
IO = 0
VI = VCC or GND
CIO A or B ports VO = VCC or GND
3.3V
3
pF
3.3V
7
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device typ e.
2. Typical values are at V CC = 3.3V, +25°C ambient and maximum loading.
3. Bus Hold maximum dynamic current required to switch the input from one state to another.
4. For I/O ports, the IOZ includes the input leakage current.
4
PS8447A
11/06/00
PI74ALVCH16524
18-Bit Registered Bus Transceiver
with 3-State Outputs
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Timing Requirements over Operating Range
Parame te rs
VCC = 2.5V ± 0.2V
D e s cription
VCC = 2.7V
VCC = 3.3V ± 0.3V
M in.
M ax.
M in.
M ax.
M in.
M ax.
120
0
125
0
150
fCLOCK
Clock frequency
0
tW Pulse
Duration
CLK high or low
3.2
3.2
3.0
B Data before CLK↑
1.5
1.2
1.1
SEL before CLK↑
2.7
2.4
2.1
CLK ENBA before CLK↑
2.7
2.6
2.0
B Data after CLK↑
1.0
0.6
1.2
SEL after CLK↑
0.5
0.2
0.8
CLK ENBA after CLK↑
0.1
0.1
0.3
tSU Setup
time
tH Hold
time
Units
MHz
ns
Switching Characteristics Over Operating Range(1)
Parame te rs
From
(Input)
To
(Output)
fMAX
VCC = 2.5V ± 0.2V
M in.(2)
M ax.
120
VCC = 2.7V
M in.(2)
VCC = 3.3V ± 0.V
M ax. M in.(2)
125
M ax.
150
MHz
tPD
A
B
3.9
3.8
3.2
tPD
CLK
A
6.1
6.2
5.2
tEN
OEAB or
OEBA
A or B
6.1
6.1
tDIS
OEAB or
OEBA
A or B
6.3
5.4
1.0
1.0
Units
ns
5.1
4.9
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating Characteristics, TA = 25ºC
Parame te r
CPD Power Dissipation
Capacitance
Te s t Conditions
Outputs Enabled
Outputs Disabled
CL = 50pF
f = 10 MHz
5
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Typical
160
Units
pF
PS8447A
11/06/00
PI74ALVCH16524
18-Bit Registered Bus Transceiver
with 3-State Outputs
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Parameter Measurement Information
VCC = 2.5V ±0.2V
Load Circuit
2 x VCC
500Ω
From Output
S1
Open
GND
Under Test
500Ω
CL = 30pF
(See Note A)
Voltage Waveforms Setup and Hold Times
Te s t
S1
tpd
O pen
tPLZ/tPZL
2 x VCC
tPHZ/tPZH
GND
Voltage Waveforms Pulse Duration
tw
VCC
Timing
VCC
VCC/2
Input
Input
VCC/2
0V
VCC/2
0V
tsu
th
VCC
Data
VCC/2
Input
Voltage Waveforms Enable and Disable Times
VCC/2
0V
VCC
Output
VCC/2
Control
(Low-level
enabling)
tPLH
OUTPUT
VCC
VCC/2
VCC/2
VCC/2
VCC/2
VOL +0.15V
(see Note B)
tPZH
0V
tPHL
tPLZ
VCC
Waveform 1
S1 at 2 x VCC
VCC/2
0V
tPZL
Output
Voltage Waveforms Propagation Delay Times
INPUT
VCC/2
tPHZ
Output
Waveform 2
S1 at GND
VOH
VOL
VCC/2
VOH -0.15V
VOH
0V
(see Note B)
VOL
Figure 1. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All inputs pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tr ≤ 2ns, tf ≤ 2ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as tten.
G. tPLH and tPHL are the same as tpd.
.
6
PS8447A
11/06/00
PI74ALVCH16524
18-Bit Registered Bus Transceiver
with 3-State Outputs
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Parameter Measurement Information
VCC = 2.7V and 3.3V ±0.3V
Load Circuit
6V
S1
500Ω
From Output
S1
tpd
O pen
tPLZ/tPZL
6V
tPHZ/tPZH
GND
GND
Under Test
500Ω
CL = 50pF
Te s t
Open
(See Note A)
Voltage Waveforms Setup and Hold Times
Voltage Waveforms Pulse Duration
2.7V
Timing
tw
1.5V
2.7V
Input
1.5V
Input
0V
1.5V
0V
tsu
th
2.7V
Data
1.5V
Input
Voltage Waveforms Enable and Disable Times
1.5V
0V
2.7V
Output
1.5V
Control
1.5V
(Low-level
enabling)
Voltage Waveforms Propagation Delay Times
3V
1.5V
S1 at 6V
1.5V
INPUT
tPLH
OUTPUT
tPHL
1.5V
1.5V
tPLZ
Output
Waveform 1
1.5V
0V
tPZL
2.7V
(see Note B)
0V
Output
tPZH
Waveform 2
S1 at GND
VOL +0.3V
tPHZ
1.5V
VOH
VOH -0.3V
0V
(see Note B)
VOH
VOL
VOL
Figure 2. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as tten.
G. tPLH and tPHL are the same as tpd.
.
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8447A
11/06/00