ETC PI74AVC+16268A

PI74AVC+16268
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12-Bit to 24-Bit Registered Bus
Exchanger with 3-State Outputs
Product Features
Product Description
• PI74AVC+16268 is designed for low-voltage operation,
VCC = 1.65V to 3.6V
Pericom Semiconductor’s PI74AVC+ series of logic circuits are
produced using the Company’s advanced submicron CMOS
technology, achieving industry leading speed.
• True ±24mA Balanced Drive @ 3.3V
The PI74AVC+16268, a 12-bit to 24-bit registered bus exchanger
designed for 1.65V to 3.6V VCC operation, is used for applications
in which data must be transferred from a narrow high-speed bus to
a wide, lower frequency bus. It provides synchronous data exchange
between the two ports. Data is stored in internal registers on the lowto-high transition of the clock (CLK) input when appropriate clockenable (CLKEN) inputs are low. The select (SEL) line is synchronous
with CLK and selects 1B or 2B input data for the A outputs.
• IOFF supports partial power-down operation
• 3.6 I/O Tolerant Inputs and Outputs
• All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
• Industrial operation: –40°C to +85°C
• Available Packages:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 173 mil wide plastic TVSOP (K)
For data transfer in the A-to-B direction, a two-stage pipeline is
provided in the A-to-1B path, with a single storage register in the
A-to-2B path. Proper control of these inputs allows two sequential
12-bit words to be presented synchronously as a 24-bit word on the
B-port. Data flow is controlled by the active-low output enables
(OEA, OEB). These control terminals are registered so bus direction
changes are synchronous with CLK.
To ensure the high-impedance state during power up or power
down, a clock pulse should be applied as soon as possible and OE
should be tied to VCC through a pullup resistor, the minimum value
of the resistor is determined by the current-sinking capability of the
driver. Because OE is being routed through a register, the active
state of the outputs cannot be determined prior to the arrival of the
first clock pulse.
Logic Block Diagram
CLK
CLKEN1B
29
2
CLKEN2B 27
30
CLKENA2
55
V
CLKENA1
V
56
OEB
28
SEL
C1
C1
1D
1D
1
OEA
CE
1D
C1
V
V
G1
V
8
1B1
CE
1
C1
1D
1
6
2B1
CE
CE
V
C1
1D
C1
1D
V
CE
C1
1D
V
A1
23
1D
C1
1 of 12 Channels
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PS8551
07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
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Pin Description
Pin Name
Pin Configuration
D e s cription
OE
O utput Enable Input (Active LO W)
CLK
Clock
SEL
Select (Active Low)
CLK EN
Clock Enable (Active Low)
A,1B,2B
3- State O utputs
GND
Ground
VCC
Power
Truth Tables
(1)
1
56
CLKEN1B
2
55
OEB
CLKENA2
2B3
3
54
2B4
GND
4
53
GND
2B2
2B1
5
52
6
51
2B5
2B6
VCC
A1
7
8
50
49
VCC
2B7
9
10
48
47
2B8
11
12
13 56-Pin
14 A, K
46
45
44
GND
2B12
A8
15
16
43
42
41
A9
17
40
GND
18
39
A10
A12
19
20
21
38
37
36
1B10
GND
1B9
VCC
22
35
1B1
1B2
23
34
VCC
1B6
24
33
1B5
GND
25
32
1B3
26
31
GND
1B4
CLKEN2B
27
30
CLKENA1
SEL
28
29
CLK
A2
Output Enable
A3
Inputs
CLK
OEA
Outputs
OEA
OEB
A
GND
1B,2B
A4
—
H
H
Z
Z
A5
—
H
L
Z
Active
A6
—
L
H
Active
Z
—
L
L
Active
Active
A to B STORAGE (OEB = L)
Inputs
CLKENA1 CLKENA2
H
H
L
L
L
L
X
L
X
L
CLK
X
↑
↑
↑
↑
A
X
L
H
L
H
A7
Outputs
1B
2B
1B0(2) 2B0(3)
L(2)
X
H(2)
X
X
L
X
H
A11
B to A STORAGE (OEA = L)
Inputs
CLKEN1B
CLKEN2B CLK SEL 1B
2B
Outputs
A
H
X
X
H
X
X
A0(3)
X
H
X
L
X
X
A0(3)
L
X
↑
H
L
X
L
L
X
↑
H
H
X
H
X
L
↑
L
X
L
L
X
L
↑
L
X
H
H
2B9
2B10
2B11
1B12
1B11
1B8
1B7
Notes:
1. H = High Signal Level, L = Low Signal Level, X = Irrelevant,
Z = High Impedance, ↑ = Transition, Low to High
2. Two CLK edges are needed to propagate data
3. Output level before indicated steady state input conditions
were established.
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PS8551
07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired.
For user guidelines, not tested.)
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Supply voltage range, VCC .............................. –0.5V to +4.6V
Input voltage range, VI .................................... –0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, VO(1) ....... –0.5V to +4.6V
Voltage range applied to any output in the
high or low state, VO(1,2) .......................... –0.5V to VCC +0.5V
Input clamp current, IIK (VI <0) .................................... –50mA
Output clamp current, IOK (VO <0) ............................... –50mA
Continuous output current, IO ..................................... ±50mA
Continuous current through each VCC or GND .......... ±100mA
Package thermal impedance, θJA(3): package A ......... 64°C/W
package K .................48°C/W
Storage Temperature range, Tstg ..................... –65°C to 150°C
Notes:
1. Input & output negative-voltage ratings may be exceeded if the
input and output curent rating are observed.
2. Output positive-voltage rating may be exceeded up to 4.6V
maximum if theoutput current rating is observed.
3. The package thermal impedance is calculated in accordance with
JESD 51.
Recommended Operating Conditions(1)
VCC
VIH
Supply Voltage
High- level Input Voltage
M in.
M ax.
Operating
1.65
3.6
Data retention only
1.2
VCC = 1.2V
VCC
VCC = 1.65V to 1.95V
VCC = 2.3V to 2.7V
VCC = 3V to 3.6V
VIL
Low- level Input Voltage
0.65 x VCC
1.7
2
VCC = 1.2V
GND
VCC = 1.65V to 1.95V
VI
Input Voltage
VO
Output Voltage
IOH
IOL
High- level output current
Low- level output current
∆t∆v Input transition rise or fall rate
TA
Units
V
0.35 x VCC
VCC = 2.3V to 2.7V
0.7
VCC = 3V to 3.6V
0.8
0
3.6
Active State
0
VCC
3- State
0
3.6
VCC = 1.65V to 1.95V
–6
VCC = 2.3V to 2.7V
– 12
VCC = 3V to 3.6V
– 24
mA
VCC = 1.65V to 1.95V
6
VCC = 2.3V to 2.7V
12
VCC = 3V to 3.6V
24
VCC = 1.65V to 3.6V
5
ns/V
85
°C
Operating free- air temperature
–40
Notes:
1. All unused inputs must be held at VCC or GND to ensure proper device operation.
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PS8551
07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
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DC Electrical Characteristics (Over the Operating Range, TA = –40°C +85°C)
Te s t Conditions (1)
Parame te rs
IOH = –100µA
VOH
VOL
VCC
M in.
1.65V to 3.6V
VCC –0.2V
IOH = –6mA
VIH = 1.07V
1.65V
1.2
IOH = –12mA
VIH = 1.7V
2.3V
1.75
IOH = –24mA
VIH = 2V
3V
2.0
IOL = 100µA
M ax.
1.65V to 3.6V
0.2
IOL = 6mA
VIH = 0.57V
1.65V
0.45
IOL = 12mA
VIH = 0.7V
2.3V
0.55
IOL = 24mA
VIH = 0.8V
3V
0.8
VI = VCC or GND
3.6V
±2.5
IOFF
VI or VO = 3.6V
0
±10
IOZ
VI = VCC or GND
3.6V
±10
ICC
VO = VCC or GND
3.6V
40
2.5V
4
3.3V
4
2.5V
6
3.3V
6
2.5V
8
3.3V
8
II
CI
Control Inputs
Control Inputs
IO = 0
VI = VCC or GND
Data Inputs
CO
Outputs
VO = VCC or GND
Units
V
µA
pF
Note:
1. Typical values are measured at TA = 25°C.
4
PS8551
07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
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Timing Requirements (Over Operating Range)
VCC = 1.2V
Parame te rs
De s cription
fCLOCK
Clock
frequency
tW
Pulse
duration,
CLK high
or low
tSU
tH
VCC = 1.5V
±0.1V
VCC = 1.8V
±0.15V
VCC = 2.5V
±0.2V
M in. M ax. M in. M ax. M in. M ax. M in.
150
M ax.
VCC = 3.3V
±0.3V
M in.
180
180
3
3
3
A data before CLK↑
2.2
2.2
2.0
1.5
1.5
B data before CLK↑
1.6
1.5
1.5
1.0
0.8
SEL before CLK↑
2.0
1.8
1.5
1.3
1.1
CLKENA1 or
CLKENA2
before CLK↑
3.2
2.2
2.0
1.8
1.7
CLKENB1 or
CLKENB2
before CLK↑
3.2
2.4
2.0
1.8
1.7
OE before CLK↑
3.2
2.5
2.2
2.2
2.0
Hold time A data after CLK↑
0.5
0.5
0.2
0.2
0.1
B data after CLK↑
1.0
1.0
1.0
1.0
1.0
SEL after CLK↑
1.4
1.4
1.0
1.0
0.8
CLKENA1 or
CLKENA2
after CLK↑
0
0
0.2
0.6
0.6
CLKENB1 or
CLKEΝB2
after CLK↑
0
0
0.1
0.6
0.6
OE after CLK↑
0
0.2
0.2
0.5
0.5
Setup
time
M ax. Units
MHz
ns
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
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PS8551
07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
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Switching Characteristics (Over Operating Range)
From
(Input)
Parame te r
To
(Output)
VCC = 1.2V
Typical
VCC = 1.5V
±0.1V
M in.
M ax. M in.
M ax.
150
fmax
tpd
VCC = 1.8V
±0.15V
VCC = 3.3V
±0.3V
M in.
M in.
M ax.
180
180
MHz
8.1
5.0
2.0
4.8
1.8
4.0
1.3
3.1
A(1B)
9.0
5.5
2.1
5.0
1.7
4.2
1.2
3.4
B(2B)
8.0
5.5
2.1
5.0
1.8
4.3
1.3
3.4
A(SEL)
9.3
6.5
2.5
5.4
2.4
4.3
1.7
3.6
B
9.3
6.4
2.8
5.8
2.6
4.4
1.8
3.8
tdis
B
9.0
7.0
3.0
6.0
2.5
3.8
1.8
3.8
ten
A
9.0
6.5
2.1
5.5
1.8
4.2
1.3
3.6
tdis
A
8.8
6.3
2.3
5.5
2.1
3.5
1.5
3.8
CLK
Units
M ax.
B
ten
CLK
VCC = 2.5V
±0.2V
ns
Notes:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating Characteristics, TA= 25°C
Parame te rs
Cpd Power
Dissipation
Capacitance
Outputs
Enabled
Outputs
Disabled
Te s t Conditions
CL = 0pF,
f = 10 MHz
VCC = 1.8V
±0.15V
VCC = 2.5V
±0.2V
VCC = 3.3V
±0.3V
Typical
Typical
Typical
60
65
76
Units
pF
40
45
6
55
PS8551
07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.2V and 1.5V ±0.1V
2xVCC
S1
2Ω
From Output
Under Test
CL = 15pF
Open
GND
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
VOL
tPHZ
VCC/2
VOH –0.1V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
7
PS8551
07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.8V ±0.15V
2xVCC
S1
12ΩkΩ
From Output
Under Test
CL = 30
15pF
Open
GND
2Ω
1 kΩ
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
0.15V
VOL
tPHZ
VCC/2
VOH –0.1V
0.15V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 2. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
8
PS8551
07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ±0.2V
2xVCC
S1
500Ω
2Ω
From Output
Under Test
CL =30
15pF
Open
GND
500Ω
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.15V
VOL
tPHZ
VCC/2
VOH –0.15V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 3. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
9
PS8551
07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 3.3V ±0.3V
2xVCC
S1
500Ω
2Ω
From Output
Under Test
CL = 30
15pF
Open
GND
500Ω
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
0.3V
VOL
tPHZ
VCC/2
VOH –0.1V
0.3V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 4. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
10
PS8551
07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
56-pin TSSOP (A) Package
56
.236
.244
1
.547
.555
6.0
6.2
13.9
14.1
1.20
SEATING PLANE
.047
Max.
.004 0.09
.008 0.20
.0197
BSC
0.50
.007
.011
0.17
0.27
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.319 BSC
8.1
56-pin TVSOP (K) Package
56
4.30
4.50
.169
.177
1
.441
.449
0.45 .018
0.75 .030
.031
.041
0.80
1.05
11.20
11.40
0.09
0.20
.0035
.008
.252
BSC
6.4
SEATING
PLANE
.016
BSC
0.40
X.XX
X.XX
.002
.006
0.05
0.15
.005
.009
0.13
0.23
.047
1.20
Max.
DENOTES DIMENSIONS
IN MILLIMETERS
Ordering Information
Orde ring D ata
D e s cription
PI74AVC+16268A
56- pin, 240 mil wide plastic TSSO P
PI74AVC+16268K
56- pin, 173 mil wide plastic TVSO P
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
11
PS8551
07/31/01