PF861-02 SRM20V512SLMT7 512K-Bit Static RAM ge lta o n V w tio Lo pera cts O odu Pr ● Wide Temperature Range ● Low Supply Current ● Access Time 70ns ● 65,536 words×8 bit Asynchronous ■ DESCRIPTION The SRM20V512SLMT7 is a 65,536 words×8-bit asynchronous, static, random access memory on a monolithic CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage with back-up batteries. And –40 to 85°C operating tempereture range wakes it idial for portable equipment. The asynchronous and static nature of the memory requires no external clock or refreshing circuit. Both the input and output ports are TTL compatible and the 3-state output allows easy expansion of memory capacity. ■ PIN CONFIGURATION ■ FEATURES (SOP6) ■ BLOCK DIAGRAM CS2 OE WE X Decoder Address Buffer 9 512 Memory Cell Array 512×128×8 Y Decoder 128×8 7 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/08 I/07 I/06 I/05 I/04 (TSOP/Slim-TSOP) A11 A9 A8 A13 WE CS2 A15 VDD N.C. N.C. A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SRM20V512SLTT/KT 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/08 I/07 I/06 I/05 I/04 VSS I/03 I/02 I/01 A0 A1 A2 A3 128 Column Gate A4 A5 A6 A7 A12 A14 N.C. N.C. VDD A15 CS2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 I/01 I/02 I/03 VSS I/04 I/05 I/06 I/07 I/08 CS1 A10 OE SRM20V512SLRT/YT ■ PIN DESCRIPTION CS1, CS2 Control Logic CS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (TSOP-R1/Slim-TSOP-R1) OE, WE Control Logic A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 N.C. N.C. A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/01 I/02 I/03 VSS SRM20V512SLMT ● Wide tempereture range ................. –40 to 85°C ● Fast Access time ............................. SRM20V512SLMT7 70ns ● Low supply current .......................... standby : 0.3µA (Typ.) operation : 8mA/1MHz (Typ.) ● Completely static ............................. No clock required ● Single power supply ........................ 2.7V to 3.6V ● TTL compatible inputs and outputs ● 3-state output with wired-OR capability ● Non-volatile storage with back-up batteries ● Package ...... SRM20V512SLMT7 SOP6-32pin (plastic) SRM20V512SLTT7 TSOP ( I )-32pin (plastic) SRM20V512SLRT7 TSOP ( I )-32pin-R1 (plastic) SRM20V512SLKT7 Slim-TSOP ( I )-32pin (plastic) SRM20V512SLYT7 Slim-TSOP ( I )-32pin-R1 (plastic) 8 I/O Buffer I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 A0 to A15 WE OE CS1 CS2 I/O1 to 8 VDD VSS N. C. Address Input Write Enable Output Enable Chip Select 1 Chip Select 2 Data I/O Power Supply (2.7V to 3.6V) Power Supply (0V) No connection SRM20V512SLMT7 ■ ABSOLUTE MAXIMUM RATINGS (VSS = 0V) Parameter Symbol Supply voltage VDD Input voltage VI Input/Output voltage VI/O Power dissipation PD Operating temperature Topr Storage temperature Tstg Soldering temperature and time Tsol Unit Ratings –0.5 to 4.6 –0.5✻ to VDD+0.3 –0.5✻ to VDD+0.3 0.5 –40 to 85 –65 to 150 260°C, 10s (at lead) V V V W °C °C — ✻ –3.0V when Pulse width is less or equal 50ns ■ DC RECOMMENDED OPERATING CONDITIONS Parameter Supply voltage Input voltage Symbol VDD VSS VIH VIL (Ta = –40 to 85°C) Min. Typ. Max. Unit 2.7 0 2.2 –0.3✻ 3.0 0 — — 3.6 0 VDD+0.3 0.4 V V V V ✻ If pulse width is less than 50ns, it is –3.0V ■ ELECTRICAL CHARACTERISTICS ● DC Electrical Characteristics Parameter Symbol Input Leakage ILI Output teakage ILO High level output voltage VOH Low level output voltage VOL IDDS Standby supply current IDDS1 IDDA Average operating current IDDA1 Operating supply current IDDO Conditions VI = 0 to VDD CS1 = VIH or CS2 = VIL or WE = VIL or OE = VIH, VIO = 0 to VDD VDD≥3V, IOH = –2.0mA IOH = –100µA VDD≥3V, IOL = –2.0mA IOL = 100µA CS1 = VIH or CS2 = VIL CS1 = CS2≥VDD–0.2V or CS2≤0.2V VI = VIL, VIH II/O = 0mA, tcyc = Min. VI = VIL, VIH II/O = 0mA, tcyc = 1us VI = VIL, VIH II/O = 0mA (VDD = 2.7 to 3.6V, VSS = 0V, Ta = –40 to 85°C) SRM20V512SLMT7 Unit Max. Min. Typ.✻ — 1.0 µA –1.0 µA –1.0 — 1.0 2.4 VDD–0.2 — — — — — — — — — — 0.4 0.2 1.0 mA — 0.3 30 µA — 20 35 mA — 8 15 mA — 8 15 mA Min. — — — Typ. — — — V V ✻ Typical values are measured at Ta = 25°C and VDD = 3.0V ● Terminal Capa citance Parameter Address Capacitance Input Capacitance I/O Capacitance (f = 1MHz, Ta = 25°C) Symbol CADD CI CI/O Conditions VADD = 0V VI = 0V VI/O = 0V Note ••• This parameter is made by the inspection data of sample, not of all products. 2 Max. 8 8 10 Unit pF pF pF SRM20V512SLMT7 ● AC Electrical Characteristics ❍ Read Cycle Parameter Symbol (VSS = 0V, VDD = 2.7V to 3.6V, Ta = –40 to 85°C) SRM20V512SLMT7 Unit Min. Max. ns — 70 Conditions Read cycle time tRC 1 Address access time tACC 1 — 70 ns Chip select 1 access time tACS1 1 — 70 ns Chip select 2 access time tACS2 1 — 70 ns Output enable access time tOE 1 — 40 ns Chip select 1 output set time tCLZ1 2 5 — ns Chip select 1 output floating tCHZ1 2 — 30 ns ns Chip select 2 output set time tCLZ2 2 5 — Chip select 2 output floating tCHZ2 2 — 30 ns Output enable output set time tOLZ 2 0 — ns Output enable output floating tOHZ 2 — 30 ns Output hold time tOH 1 10 — ns ❍ Write Cycle Parameter (VSS = 0V, VDD = 2.7V to 3.6V, Ta = –40 to 85°C) SRM20V512SLMT7 Unit Min. Max. ns — 70 Symbol Conditions Write cycle time tWC 1 Chip select time 1 tCW1 1 60 — ns Chip select time 2 tCW2 1 60 — ns Address enable time tAW 1 60 — ns Address setup time tAS 1 0 — ns Write pulse width tWP 1 55 — ns Address hold time tWR 1 0 — ns Input data setup time tDW 1 30 — ns Input data hold time tDH 1 0 — ns WE Output floating tWHZ 2 — 30 ns WE Output setup time tOW 2 5 — ns ✻1 Test Conditions ✻2 Test Conditions 1. Input pulse level : 0.4V to 2.4V 1. Input pulse level : 0.4V to 2.4V 2. tr = tf = 5ns 2. tr = tf = 5ns 3. Input and output timing reference levels : 1.5V 3. Input timing reference levels : 1.5V 4. Output load CL = 100pF 4. Output timing reference levels: ±200mV (the level displaced from stable output voltage level) 5. Output load CL = 5pF +3V +3V 1.0KΩ 1.0KΩ I/O I/O 100pF 920Ω 5pF 920Ω 3 SRM20V512SLMT7 ● Timing Chart ❍Read Cycle✻1 ❍Write Cycle 1 (CS1 Control)✻2 tRC tWC Address tACC tACS1 tOH CS1 tCLZ1 tACS2 tCHZ1 Address CS1 tAW tCW1 tAS tWR CS2 CS2 tCLZ2 tWP tCHZ2 WE tOE OE tWHZ tCLZ1 tOHZ tOLZ Dout tDW Dout ❍Write Cycle 2 (CS2 Control)✻2 ❍Write Cycle 3 (WE Control) ✻3 • ✻4 tWC tWC Address Address tAW tCW2 tAW CS1 CS1 tAS tWR tAS CS2 tWR CS2 tWP WE tWP WE tWHZ Dout tCLZ2 tWHZ tDW tDH Din Note) tDH Din tOW Dout tDW tDH Din ✻1 During read cycle time, WE is to be "H" level. During write cycle time that is controlled by CS1 or CS2, Input/output Buffer is in high impedance state whether OE level is "H"or "L". ✻3 During write cycle time that is controlled by WE, Input/output Buffer is high impedance state if OE is "H" level. ✻4 When I/O terminals are output mode, be careful that do not give the epposite signals to the I/O terminals. ✻2 ● DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY (VSS = 0V, Ta = –40 to 85°C) Min. Typ.✻ Max. Unit 2.0 — 3.6 V — 0.25 25 µA tCDR 0 — — ns tR 5 — — ms Parameter Symbol Data retention supply voltage VDDR Data retention current IDDR Chip select data hold time Conditions VDD = 2.7V Operation recovery time CS1 = CS2≥VDD–0.2V or CS2≤0.2V ✻ : Ta = 25°C Data retention timing 1 (CS1 Control) VDD 2.7V tCDR CS1 2.7V tR CS1≥VDD \0.2V VIH 4 Data hold mode VDDR≥2.0V VIH Date retention timing 2 (CS2 Control) VDD 2.7V tCDR CS2 VIL Data hold mode VDDR≥2.0V 2.7V tR VIL CS2≤0.2V SRM20V512SLMT7 ■ FUNCTIONS ● Truth Table CS1 CS2 OE WE DATA I/O MODE IDD H X X X Hi—Z Unselected IDDS, IDDS1 X L X X Hi—Z Unselected IDDS, IDDS1 L H X L Input data Write IDDA, IDDA1 L H L H Ouput data Read IDDA, IDDA1 L H H H Hi—Z Output disable IDDA, IDDA1 X : "H" or "L" ● Reading data Data is able to be read when the address is setted while holding CS1 = "L", CS2 = "H", OE = "L" and WE = "H". Since Data I/O terminals are in high impedance state when OE = "H", the data bus line can be used for any other objective, then access time apparently is able to be cut down. ● Writing data There are the following four ways of writing data into the memory. (1) Hold CS2 = "H", WE = "L", set addresses and give "L" pulse to CS1. (2) Hold CS1 = "L", WE = "L", set addresses and give "H" pulse to CS2. (3) Hold CS1 = "L", CS2 = "H", set addresses and give "L" pulse to WE. (4) After setting addresses, give "L" pulse to CS1, WE and give "H" pulse to CS2. Anyway, data on the Data I/O terminals are latched up into the chip at the end of the period that CS1, WE are "L" level, and CS2 is "H" level. As Data I/O terminals are in high impedance state when any of CS1, OE = "H", or CS2 = "L", the contention on the data bus can be avoided. ● Standby mode When CS1 is "H" or CS2 is "L" level, the chip is in the standby mode which has retaning data operation. In this case Data I/O terminals are Hi-Z, and all inputs of addresses, WE and data can be any "H" or "L". When CS1 and CS2 level are in the range over VDD-0.2V, or CS2 level is in the range under 0.2V, in the chip there is almost no current flow except through the high resistance parts of the memory. ● Data Retention at low Voltage Power Supply During standby mode in which the data is retentive, the supply voltage (VDD) can be in low voltage until VDD = VDDR. At this mode data reading and writing are impossible. 5 SRM20V512SLMT7 ■ PACKAGE DIMENSIONS Plastic SOP6-32pin 20.85max (0.82max) ±0.1 20.45+0.004 (0.805 –0.003 ) ±0.3 14.135 +0.012 ±0.1 11.295 +0.003 (0.556 –0.011 ) 17 (0.445 –0.004 ) 32 2.7±0.1 +0.004 16 3.1max (0.122max) 1 (0.106 –0.003 ) 0° 8° 0.15±0.05 +0.001 (0.006 –0.002 ) Plastic TSOP(I)-32pin 0.8±0.2 +0.008 (0.031 –0.007 ) 0.2 (0.016 –0.004 ) (0.008) 0.4±0.1 +0.003 1.27 (0.05) Unit : mm (inch) 1.42 (0.056) Plastic TSOP(I)-32pin-R1 20±0.2 +0.008 20±0.2 +0.008 (0.787 –0.007 ) (0.787 –0.007 ) ±0.2 18.4+0.008 (0.724 –0.007 ) ±0.2 18.4+0.008 (0.724 –0.007 ) 1 16 32 17 8±0.2 8±0.2 (0.315±0.007) (0.315±0.007) INDEX INDEX 17 32 1 ±0.1 0.5+0.003 +0.07 0.15 –0.075 +0.002 (0.006 –0.003 ) ±0.1 0.5+0.003 0.2±0.1 +0.003 0.5 (0.02) (0.02 –0.004 ) (0.008 –0.004 ) Unit : mm(inch) Plastic Slim-TSOP(I)-32pin 17 0.5±0.2 0.5±0.2 +0.10 0.15–0.05 1.2MAX 32 +0.03 0.15–0 +0.10 0.15–0.05 1.2MAX 0°–7° +0.03 0.15–0 1 0.5±0.2 11.8±0.1 0°–7° 17 0.5±0.2 0.5±0.2 Unit : mm 6 16 +0.07 0.20–0.02 8.0±0.1 32 13.4±0.2 8.0±0.1 0.50 0.50 11.8±0.1 +0.07 0.20–0.02 0.5±0.2 Unit : mm(inch) Plastic Slim-TSOP(I)-32pin-R1 13.4±0.2 16 0.2±0.1 +0.003 (0.008 –0.004 ) 0.8±0.2 +0.008 (0.031 –0.007 ) 0.8±0.2 +0.008 (0.031 –0.007 ) 1 1 1 1.27max (0.039) 0.5 (0.02) (0.02 –0.004 ) (0.05max) +0.07 0.15 –0.075 +0.002 (0.006 –0.003 ) 1.27max (0.05max) 0° 10° 0° 10° (0.039) 16 Unit : mm SRM20V512SLMT7 ■ CHARACTERISTICS CURVES Normalized IDDA—Ta Normalized IDDA—Frequency 1.7 VDD = 3.0V READ, WRITE 1.6 1.5 1 1.6 0.9 1.5 Ta = 25°C VDD = 3.0V 0.8 1.4 1.3 Normalized IDDA—VDD Ta = 25°C READ, WRITE 1.4 0.7 1.3 0.6 1.2 0.5 1.1 WRITE READ 1.2 1.1 WRITE 1 1 0.4 READ WRITE READ 0.3 0.9 0.9 0.8 0.2 0.8 0.7 0.1 0.7 0.6 0 –40 –20 0 20 40 Ta (°C) 60 80 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) 1/tRC, 1/tWC Normalized IDDS1—Ta 0.6 2.4 Normalized IDDS1—VDD 100 3 3.3 VDD (V) 3.6 3.9 Normalized IOH—VOH 100 VDD=3.0V 2.7 Ta = 25°C 2.4 Ta = 25°C VDD = 3.0V 2.2 2 10 1.8 1.6 1.4 1 1 1.2 1 0.8 0.1 0.6 0.4 0.2 0.01 –40 –20 0 20 40 Ta (°C) 60 80 0.1 2.4 2.7 3 3.3 VDD (V) 3.6 3.9 0 0.5 1 1.5 2 2.5 VOH (V) 3 3.5 7 SRM20V512SLMT7 tACC Normalized tACS1—Ta tACS2 tACC Normalized tACS1—VDD tACS2 1.4 Normalized IOL—VOL 2.2 1.3 VDD=3.0V 1.3 1.2 Ta=25°C 1.25 2 1.2 1.8 1.6 1.15 1.4 1.1 1.1 Ta=25°C VDD=3.0V 1.2 1.05 1 1.0 1 0.8 0.95 0.9 0.8 0.4 0.85 0.2 0.7 –40 –20 0 20 40 Ta (°C) 60 0.6 0.9 80 0.8 2.4 tACC Normalized tACS1—CL tACS2 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0 2.7 3 3.3 VDD (V) 3.6 3.9 0 0.2 0.4 0.6 VOL (V) 0.8 1 Normalized IDDR—Ta 100 VDD2.7V Ta=25°C VDD=3.0V 10 1 0.1 0.01 0 100 200 300 CL (pF) 400 –40 –20 0 20 40 60 Ta (°C) 80 NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. 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This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. © Seiko Epson Corporation 1999 All right reserved. ELECTRONIC DEVICES MARKETING DIVISION IC Marketing & Engineering Group ED International Marketing Department I (Europe & U.S.A.) 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone : 042-587-5812 FAX : 042-587-5564 ED International Marketing Department II (Asia) 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone : 042-587-5814 FAX : 042-587-5110