DATA SHEET MOS INTEGRATED CIRCUIT µPD16634A 300-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64 GRAY SCALE) DESCRIPTION The µPD16634A is a source driver for TFT-LCDs capable of dealing with displays 64 gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the ★ output dynamic range is as large as VSS2+0.1 V to VDD2−0.1 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also to be able to deal with dot-line inversion when mounted on a single side, this source driver equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequent of 40 MHz when drivng at 3.0 V, this driver is applicable to XGA-standard TFT-LCD panels. FEATURES • 300 outputs • CMOS level input • Input of 6 bits (gradation data) by 6 dots • Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter ★ • Output dynamic range : VSS2+0.1 V to VDD2−0.1 V ★ • Logic part supply voltage (VDD1) : 3.3 V ± 0.3 V ★ • Driver part supply voltage (VDD2) : 8.0 V ± 0.5 V • High-speed data transfer: fMAX=40 MHz MIN.(internal data transfer rate when operating at 3.0 V) • Output voltage polarity inversion is possible (POL) • Display data inversion function (POL2) • Single bank arrangement is possible(loaded with slim TCP). ORDERING INFORMATION Part Number Package µPD16634AN-xxx TCP (TAB package) Remark The TCP’s external shape is customized. To order your TCP’s external shape, please contact a NEC salesperson. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S12595EJ2V0DS00 (2nd edition) Date Published March 1999 NS CP (K) Printed in Japan The mark • shows major revised points. © 1998 µPD16634A 1. BLOCK DIAGRAM STHR R,/L CLK STB STHL VDD1 VSS1 50-bit bidirectional shift register C1 C2 C49 C50 D00 - D05 D10 - D15 D20 - D25 D30 - D35 D40 - D45 D50 - D55 POL2 Data register POL Latch VDD2 Level shifter VSS2 V0 - V 9 D/A converter Voltage follower output S1 Remark 2 S2 S3 S300 /xxx indicates active low signal. Data Sheet S12595EJ2V0DS00 µPD16634A 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 V4 V5 S299 S300 5 ····· V0 S2 Multiplexer 6-bit D/A converter 5 ····· ★ V9 POL Data Sheet S12595EJ2V0DS00 3 µPD16634A 3. PIN CONFIGURATION (µPD16634AN-xxx) Caution S300 S299 S298 S297 (Copper Plated Surface) VSS2 VDD2 VSS1 R,/L POL STB D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 STHL V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 CLK STHR D30 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 POL2 TEST VDD1 VDD2 VSS2 S4 S3 S2 S1 This figure does not specify the TCP package. Therefore POL2 pins can be reduced by opening or short-circuiting to VSS2 by TCP wiring. POL2 pin can short to VSS1 on TCP. So when you not use “data inversion function”, can reduce input pins. 4 Data Sheet S12595EJ2V0DS00 µPD16634A 4. PIN FUNCTIONS Pin Symbol Pin Name S1 to S300 Driver output D00 to D05 Display data input Description The D/A converted 64-gray-scale analog voltage is output The display data is input with a width of 36 bits, viz., the gray scale data D10 to D15 (6 bits) by 6 dots (2 pixels). D20 to D25 DX0 : LSB, DX5 : MSB D30 to D35 D40 to D45 D50 to D55 R,/L Shift direction switching input STHR STHL Right shift start pulse input/output Left shift start pulse input/output CLK Shift clock input STB Latch input POL Polarity input POL2 Data inversion input V0 to V9 γ-corrected power supplies TEST Test pin These refer to the start pulse input/output pins when cascades are connected. The shift directions of the shift registers are as follows. R,/L = H : STHR input, S1→S300, STHL output R,/L = L : STHL input, S300→S1, STHR output R,/L = H : Becomes the start pulse input pin. R,/L = L : Becomes the start pulse output pin. R,/L = H : Becomes the start pulse input pin. R,/L = L : Becomes the start pulse output pin. Refers to the shift register’s shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 50th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. The initiallevel driver’s 50th clock becomes valid as the next-level driver’s start pulse is input. If 52 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. The contents of the data register are transferred to the latch at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL = L ; The S2n-1 output uses V0 to V4 as the reference supply; and the S2n output uses V5 to V9 as the reference supply. POL = H ; The S2n-1 output uses V5 to V9 as the reference supply; and the S2n output uses V0 to V4 as the reference supply. S2n-1 indicates the odd output; and S2n indicates the even output. Input of the POL signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge. POL2 = H : Display data is inverted. POL2 = L : Display data is not inverted. Input the γ-corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2 Set it to open. VDD1 Logic circuit power supply 3.3 V ± 0.3 V VDD2 Driver circuit power supply 8.0 V ± 0.5 V VSS1 Logic ground Grounding VSS2 Driver ground Grounding Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down.(Simultaneous power application to VDD2 and V0 to V9 is possible.) 2. To stabilize the supply voltage, please be sure to insert 0.1 µF bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increase precision of the D/A converter, insertion of a bypass capacitor of about 0.01 µF is also advised between the γ-corrected power supply terminals(V0,V1,V2...,V9) and VSS2. 3. We recommend to use Operational Amplifier to lower input impedance of γ-corrected voltage. Data Sheet S12595EJ2V0DS00 5 µPD16634A 5. RELATIONHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE This product incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors r0 to r62 are so designed that the ratios between the LCD panel’s γ-corrected voltages and V0’ to V63’, V0” to V63” are roughly equal; and their respective resistance values are as shown in Table 6-1. Among the 5-by 2 γ-corrected voltages, input gray scale voltages of the same polarity with respect to the common voltage, for the respective five γ-corrected voltages of V0 to V4 and V5 to V9. If fine gray scale voltage precision is not necessary, the voltage follower circuit supplied to the γ-corrected power supplies V1 to V3 and V6 to V8 can be deleted. Figure 5-1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2, common electrode potential VCOM, and γ-corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage relationships of VDD2 > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2. Figure 6-1 and 6-2 show the relationship between the input data and the output data. This driver IC is designed for single-sided mounting. Therefore, please do not use it for γ-corrected power supply level inversion in double-sided mounting. Figure 5-1. Relationship between Input Data and Output Voltage ★ VDD2 Split interval V0 16 V1 16 V2 16 V3 15 V4 VCOM V5 15 V6 16 V7 16 V8 16 V9 VSS2 00 6 08 10 18 20 28 Data Sheet S12595EJ2V0DS00 30 38 3F Input data (HEX) µPD16634A 6. RESISTOR STRINGS Figure 6-1. Relationship Between Input Data and Output Voltage : VDD2 > V0 > V1 > V2 > V3 > V4 > V5, POL2 = L V 0’ V0 r0 V1’ r1 V2’ r2 V3’ r3 r14 V15’ r15 V16’ V1 r16 V17’ r17 r30 V31’ r31 V32’ V2 r32 V33’ r33 r46 V47’ r47 V48’ V3 r48 V49’ r49 r60 V61’ r61 V62’ r62 V63’ V4 V63’’ V5 r62 V62’’ Data DX5 DX4 DX3 DX2 DX1 DX0 Output Voltage 00H 01H 02H 03H 04H 05H 06H 07H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V 0’ V 1’ V 2’ V 3’ V 4’ V 5’ V 6’ V 7’ V0 V1 + (V0 – V1) × V1 + (V0 – V1) × V1 + (V0 – V1) × V1 + (V0 – V1) × V1 + (V0 – V1) × V1 + (V0 – V1) × V1 + (V0 – V1) × 7250/8050 6500/8050 5800/8050 5150/8050 4550/8050 4000/8050 3450/8050 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V 8’ V 9’ V10’ V11’ V12’ V13’ V14’ V15’ V1 + (V0 – V1) × V1 + (V0 – V1) × V1 + (V0 – V1) × V1 + (V0 – V1) × V1 + (V0 – V1) × V1 + (V0 – V1) × V1 + (V0 – V1) × V1 + (V0 – V1) × 2950/8050 2450/8050 2050/8050 1650/8050 1300/8050 950/8050 600/8050 300/8050 10H 11H 12H 13H 14H 15H 16H 17H 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V16’ V17’ V18’ V19’ V20’ V21’ V22’ V23’ V1 V2 + (V1 – V2) × V2 + (V1 – V2) × V2 + (V1 – V2) × V2 + (V1 – V2) × V2 + (V1 – V2) × V2 + (V1 – V2) × V2 + (V1 – V2) × 2450/2750 2200/2750 1950/2750 1700/2750 1500/2750 1300/2750 1100/2750 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V24’ V25’ V26’ V27’ V28’ V29’ V30’ V31’ V2 + (V1 – V2) × V2 + (V1 – V2) × V2 + (V1 – V2) × V2 + (V1 – V2) × V2 + (V1 – V2) × V2 + (V1 – V2) × V2 + (V1 – V2) × V2 + (V1 – V2) × 950/2750 800/2750 650/2750 500/2750 400/2750 300/2750 200/2750 100/2750 20H 21H 22H 23H 24H 25H 26H 27H 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V32’ V33’ V34’ V35’ V36’ V37’ V38’ V39’ V2 V3 + (V2 – V3) × V3 + (V2 – V3) × V3 + (V2 – V3) × V3 + (V2 – V3) × V3 + (V2 – V3) × V3 + (V2 – V3) × V3 + (V2 – V3) × 1500/1600 1400/1600 1300/1600 1200/1600 1100/1600 1000/1600 900/1600 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V40’ V41’ V42’ V43’ V44’ V45’ V46’ V47’ V3 + (V2 – V3) × V3 + (V2 – V3) × V3 + (V2 – V3) × V3 + (V2 – V3) × V3 + (V2 – V3) × V3 + (V2 – V3) × V3 + (V2 – V3) × V3 + (V2 – V3) × 800/1600 700/1600 600/1600 500/1600 400/1600 300/1600 200/1600 100/1600 30H 31H 32H 33H 34H 35H 36H 37H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V48’ V49’ V50’ V51’ V52’ V53’ V54’ V55’ V3 V4 + (V3 – V4) × V4 + (V3 – V4) × V4 + (V3 – V4) × V4 + (V3 – V4) × V4 + (V3 – V4) × V4 + (V3 – V4) × V4 + (V3 – V4) × 3350/3450 3250/3450 3150/3450 3050/3450 2950/3450 2800/3450 2650/3450 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V56’ V57’ V58’ V59’ V60’ V61’ V62’ V63’ V4 + (V3 – V4) × V4 + (V3 – V4) × V4 + (V3 – V4) × V4 + (V3 – V4) × V4 + (V3 – V4) × V4 + (V3 – V4) × V4 + (V3 – V4) × V4 Data Sheet S12595EJ2V0DS00 2500/3450 2300/3450 2100/3450 1850/3450 1600/3450 1300/3450 800/3450 7 µPD16634A Figure 6-2. Relationship Between Input Data and Output Voltage : V4 > V5 > V6 > V7 > V8 > V9 > VSS2, POL2 = L Data r62 V62’ V5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V0’’ V1’’ V2’’ V3’’ V4’’ V5’’ V6’’ V7’’ V9 V9 + (V8 – V9) V9 + (V8 – V9) V9 + (V8 – V9) V9 + (V8 – V9) V9 + (V8 – V9) V9 + (V8 – V9) V9 + (V8 – V9) × 800/8050 × 1550/8050 × 2250/8050 × 2900/8050 × 3500/8050 × 4050/8050 × 4600/8050 V61’’ 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V8’’ V9’’ V10’’ V11’’ V12’’ V13’’ V14’’ V15’’ V9 + (V8 – V9) V9 + (V8 – V9) V9 + (V8 – V9) V9 + (V8 – V9) V9 + (V8 – V9) V9 + (V8 – V9) V9 + (V8 – V9) V9 + (V8 – V9) × × × × × × × × 5100/8050 5600/8050 6000/8050 6400/8050 6750/8050 7100/8050 7450/8050 7750/8050 V49’’ 10H 11H 12H 13H 14H 15H 16H 17H 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V16’’ V17’’ V18’’ V19’’ V20’’ V21’’ V22’’ V23’’ V8 V8 + (V7 – V8) V8 + (V7 – V8) V8 + (V7 – V8) V8 + (V7 – V8) V8 + (V7 – V8) V8 + (V7 – V8) V8 + (V7 – V8) 300/2750 550/2750 800/2750 1050/2750 1250/2750 1450/2750 1650/2750 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V24’’ V25’’ V26’’ V27’’ V28’’ V29’’ V30’’ V31’’ V8 + (V7 – V8) V8 + (V7 – V8) V8 + (V7 – V8) V8 + (V7 – V8) V8 + (V7 – V8) V8 + (V7 – V8) V8 + (V7 – V8) V8 + (V7 – V8) × × × × × × × × × × × × × × × 20H 21H 22H 23H 24H 25H 26H 27H 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V32’’ V33’’ V34’’ V35’’ V36’’ V37’’ V38’’ V39’’ V7 V7 + (V6 – V7) V7 + (V6 – V7) V7 + (V6 – V7) V7 + (V6 – V7) V7 + (V6 – V7) V7 + (V6 – V7) V7 + (V6 – V7) 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V40’’ V41’’ V42’’ V43’’ V44’’ V45’’ V46’’ V47’’ V7 + (V6 – V7) V7 + (V6 – V7) V7 + (V6 – V7) V7 + (V6 – V7) V7 + (V6 – V7) V7 + (V6 – V7) V7 + (V6 – V7) V7 + (V6 – V7) 30H 31H 32H 33H 34H 35H 36H 37H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V48’’ V49’’ V50’’ V51’’ V52’’ V53’’ V54’’ V55’’ V6 V6 + (V5 – V6) V6 + (V5 – V6) V6 + (V5 – V6) V6 + (V5 – V6) V6 + (V5 – V6) V6 + (V5 – V6) V6 + (V5 – V6) 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V56’’ V57’’ V58’’ V59’’ V60’’ V61’’ V62’’ V63’’ V6 + (V5 – V6) V6 + (V5 – V6) V6 + (V5 – V6) V6 + (V5 – V6) V6 + (V5 – V6) V6 + (V5 – V6) V6 + (V5 – V6) V5 V63’’ r62 V62’’ r61 r60 r49 r48 V6 V48’’ r47 V47’’ r46 r33 V33’’ r32 V7 V32’’ r31 V31’’ r30 r17 V17’’ r16 V8 V16’’ r15 V15’’ r14 r3 V3’’ r2 V2’’ r1 V1’’ r0 V9 8 Output Voltage 00H 01H 02H 03H 04H 05H 06H 07H V63’ V4 DX5 DX4 DX3 DX2 DX1 DX0 V0’’ Data Sheet S12595EJ2V0DS00 × × × × × × × × × × × × × × × × × × × × × × × × × × × × × 1800/2750 1950/2750 2100/2750 2250/2750 2350/2750 2450/2750 2550/2750 2650/2750 100/1600 200/1600 300/1600 400/1600 500/1600 600/1600 700/1600 800/1600 900/1600 1000/1600 1100/1600 1200/1600 1300/1600 1400/1600 1500/1600 100/3450 200/3450 300/3450 400/3450 500/3450 650/3450 800/3450 950/3450 1150/3450 1350/3450 1600/3450 1850/3450 2150/3450 2650/3450 µPD16634A Table 6-1. Ladder Resistance Values (r0 to r62) : Reference Value V0, V9 V1, V8 V2, V7 Resistor Name Resistance Value (Ω) Resistor Name Resistance Value (Ω) r0 800 r32 100 r1 750 r33 100 r2 700 r34 100 r3 650 r35 100 r4 600 r36 100 r5 550 r37 100 r6 550 r38 100 r7 500 r39 100 r8 500 r40 100 r9 400 r41 100 r10 400 r42 100 r11 350 r43 100 r12 350 r44 100 r13 350 r45 100 r14 300 r46 100 r15 300 r47 100 r16 300 r48 100 r17 250 r49 100 r18 250 r50 100 r19 250 r51 100 r20 200 r52 100 r21 200 r53 150 r22 200 r54 150 r23 150 r55 150 r24 150 r56 200 r25 150 r57 200 r26 150 r58 250 r27 100 r59 250 r28 100 r60 300 r29 100 r61 500 r30 100 r62 r31 100 Total Data Sheet S12595EJ2V0DS00 800 15850 V2, V7 V3, V6 V4, V5 9 µPD16634A 7. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format : 6 bits x 2 RGBs (6 dots) Input width : 36 bits (2-pixel data) (1) R,/L = H (right shift) Output S1 S2 S3 S4 S5 … S299 S300 Data D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 … D40 to D45 D50 to D55 (2) R,/L = L (left shift) Output S1 S2 S3 S4 S5 … S299 S300 Data D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 … D40 to D45 D50 to D55 POL S2n-1 S2n L V0 to V4 V5 to V9 H V5 to V9 V0 to V4 Remark S2n-1 (Odd output), S2n (Even output)n = 1,2,.......,150 8. RELATIONSHIP BETWEEN STB, POL, AND OUTPUT WAVEFORM The output voltage is written to the LCD panel synchronized with the STB falling edge. STB POL S2n–1 Selected voltage of V0 to V4 Selected voltage of V5 to V9 Selected voltage of V0 to V4 S2n Selected voltage of V5 to V9 Hi-Z 10 Selected voltage of V0 to V4 Hi-Z Selected voltage of V5 to V9 Hi-Z Data Sheet S12595EJ2V0DS00 µPD16634A 9. CAUTIONS ABOUT FRAME INVERSION In the case of dot inversion, n frame last line and (n+1) frame first line is the same polarity. When write the same polarity twice; there are two cases as follows. (1) Last line output in n frame > First line output in (n+1) frame → Positive to write (2) Last line output in n frame < First line output in (n+1) frame → Not possible to write µPD16634A has charge buffer and discharge buffer, so need to inversion polarity and write in the case of both ways. Vertical intervals (n+1) frame first line n frame last line STB (n+1) frame second line Charge buffer Discharge buffer POL S2N VCOM Hi-Z Hi-Z Hi-Z Vertical intervals (n+1) frame first line n frame last line STB (n+1) frame second line POL S2N VCOM Hi-Z Hi-Z Hi-Z Data Sheet S12595EJ2V0DS00 Hi-Z 11 µPD16634A 10. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 °C,VSS1 = VSS2 = 0 V) Parameter ★ Symbol Ratings Unit Logic part supply voltage VDD1 –0.5 to +5.0 V Driver part supply voltage VDD2 –0.5 to +10.0 V Logic part input voltage VI1 –0.5 to VDD1 + 0.5 V Driver part input voltage VI2 –0.5 to VDD2 + 0.5 V Logic part output voltage VO1 –0.5 to VDD1 + 0.5 V Driver part output voltage VO2 –0.5 to VDD2 + 0.5 V Operating ambient temperature TA –10 to +75 °C Storage temperature Tstg –55 to +125 °C Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended Operating Range (TA = –10 to +75 °C, VSS1 = VSS2 = 0 V) Parameter Symbol MIN. TYP. MAX. Unit Logic part supply voltage VDD1 3.0 3.3 3.6 V Driver part supply voltage VDD2 7.5 8.0 8.5 V High-level input voltage VIH 0.7VDD1 VDD1 V Low-level input voltage VIL 0 0.3VDD1 V γ-corrected supply voltage V0 to V9 VSS2 VDD2 V Driver part output voltage VO VSS2 + 0.1 VDD2 – 0.1 V Maximum clock frequency fMAX. 12 40 Data Sheet S12595EJ2V0DS00 MHz µPD16634A Electrical Characteristics (TA = –10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 8.0 V ± 0.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. Input leakage current IIL High-level output voltage VOH STHR(STHL),IO=0 mA Low-level output voltage VOL STHR(STHL),IO=0 mA γ -corrected supply current Iγ V0−V9 = 8 V TYP. V0,V9 0.3 IVOL VX=1 V, VOUT=7 V Note1 ∆VO Input data : 00H to 3FH ±5 Average output voltage variation ∆VAV Input data : 00H to 3FH ±10 Output voltage range VO Input data : 00H to 3FH Logic part dynamic current IDD1 VDD1, when with no load IDD2 VDD2, when with no load Note2 Output voltage deviation Note3 ±1.0 µA V VX=7 V, VOUT=1 V IVOH Unit VDD1−0.1 Note1 Driver output current MAX. 0.1 V 0.6 mA −0.5 mA 0.5 mA ±20 mV mV VDD2−0.1 V 0.5 3.5 mA 2.2 8.0 mA 0.1 consumptionNotes4,5 ★ Driver part dynamic current Notes4,5 consumption Notes 1. VX refers to the output voltage of analog output pins S1 to S300. VOUT refers to the voltage applied to analog output pins S1 to S300. 2. The output voltage deviation refers to the voltage difference between adjoining output pins when the display data is the same (within the chip). 3. The average output voltage variation refers to the average output voltage difference between chips. The average output voltage refers to the average voltage between chips when the display data is the same. 4. The STB cycle is defined to be 20 µs at fCLK = 40 MHz. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 5. Refers to the current consumption per driver when cascades are connected under the assumption of SVGA single-sided mounting (10 units). Switching Characteristics (TA = −10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 8.0 V ± 0.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Start pulse delay time TYP. MAX. Unit 13 20 ns 3.7 8 µs tPHL3 5.3 14 µs tPLH2 3.0 8 µs tPLH3 5.3 14 µs 5.4 15 pF 7.6 15 pF tPLH1 Driver output delay time Input capacitance tPHL2 C1 Condition MIN. CL = 25 pF CL = 125 pF, RL = 4 kΩ Note STHR,STHL excluded, TA = 25 °C C2 Note Load condition RL RL RL RL RL = 1kΩ output CL = 25pF CL CL CL CL CL Data Sheet S12595EJ2V0DS00 13 µPD16634A Timing Requirements (TA = −10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VSS1 = VSS2 = 0 V, tr = tf = 8.0 ns) Parameter Symbol Condition MIN. TYP. MAX. Unit Clock pulse width PW CLK 25 ns Clock pulse low period PW CLK (L) 6 ns Clock pulse high period PW CLK (H) 6 ns Data setup time tSETUP1 6 ns Data hold time tHOLD1 6 ns Start pulse setup time tSETUP2 5 ns Start pulse hold time tHOLD2 5 ns Start pulse low period tSPL 6 ns POL2 setup time tSETUP3 6 ns POL2 hold time tHOLD3 6 ns STB pulse width PW STB 1 µs Data invalid period tINV 1 CLK Final data timing tLDT 2 CLK ★ CLK-STB time tCLK-STB CLK↑→STB↑ 6 ns ★ STB-CLK time tSTB-CLK STB↑ →CLK↑ 6 ns Time between STB and start pulse tSTB-STH STB↓ →CLK↑ 60 ns POL-STB time tPOL-STB POL↑or↓ →STB↑ −5 ns STB-POL time tSTB-POL STB↓ →POL↑ or↓ 6 ns 14 Data Sheet S12595EJ2V0DS00 ★ 2 PWCLK(H) 3 tr tf VDD1 90% 50 51 52 1025 tSETUP2 tHOLD2 1026 1 tCLK-STB tSTB-CLK 2 10% VSS1 tSPL VDD1 STHR (1st Dr.) VSS1 tSETUP1 tHOLD1 tSTB-STH VDD1 Dn0 to Dn5 INVALID D1 to D6 D7 to D12 D289 to D294 D295 to D300 D301 to D306 D3067 to D3072 INVALID D1 to D6 D7 to D12 VSS1 tSETUP3 tHOLD3 VDD1 POL2 INVALID INVALID Data Sheet S12595EJ2V0DS00 VSS1 tPLH1 VDD1 STHL (1st Dr.) VSS1 tLDT tINV PWSTB VDD1 STB VSS1 11. SWITCHING CHARACTERISTIC WAVEFORM(R,/L= H) 1 CLK PWCLK Unless otherwise specified, the input level is defined to be 0.5 VDD1. PWCLK(L) tSTB-POL tPOL-STB VDD1 POL VSS1 tPLH3 Hi-Z tPLH2 Target Voltage ±0.1VDD2 VOUT 6-bit accuracy 15 µPD16634A tPHL2 tPHL3 µPD16634A 12. RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for mounting conditions of the µPD16634A. For more details, refer to the Semiconductor Device Mounting Technology Manual(C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. µPD16634AN-xxx : TCP(TAB Package) Mounting Condition Thermocompression Mounting Method Condition Heating tool 300 to 350 °C, heating for 2 to 3 sec ; pressure 100g(per Soldering solder) ACF Temporary bonding 70 to 100 °C ; pressure 3 to 8 kg/cm ; time 3 to 5 (Adhesive Conductive sec. Real bonding 165 to 180 °C pressure 25 to 45 kg/cm time 30 to Film) 40secs(When using the anisotropy conductive film SUMIZAC1003 of 2 2 Sumitomo Bakelite,Ltd). Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time. 16 Data Sheet S12595EJ2V0DS00 µPD16634A [MEMO] Data Sheet S12595EJ2V0DS00 17 µPD16634A [MEMO] 18 Data Sheet S12595EJ2V0DS00 µPD16634A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S12595EJ2V0DS00 19 µPD16634A Reference Documents NEC Semiconductor Device Reliability/Quality Control System(C10983E) Quality Grades to NEC’s Semiconductor Devices(C11531E) • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8