AN3726: MA31750 - Application Note 3 AN3726 MA31750 - Use Of Console Mode Application Note Replaces January 2000 version, AN3726-4.0 The following information applies to the N- iteration of the MA31750. Console Mode is an optional feature of MIL-STD-1750 processors in general and is mentioned in MIL-STD-1750. The mode is provided within the MA31750 to allow the system designer to control, monitor and modify internal operation of the processor without having to substantially rewrite system software. This Applications Note describes this mode in detail, giving information on the commands available and the external hardware required to support the Console. This Note updates and corrects the previous issues for the relevant iterations. OVERVIEW The processor can operate in one of a number of different modes. One of these is Console mode where the normal MILSTD-1750 operation is suspended and a special debugging interface is presented instead. Console mode may be entered by either hardware or software means. When in Console mode the processor receives its instructions from a fixed IO-mapped location. Operands and results (as appropriate) associated with these instructions are passed between system and processor via two other fixed locations in the IO map. Any number of Console commands may be performed before issuing a special command which returns control back to the interrupted 1750 program. Note that the two interval timers, Timer A and Timer B, are stopped on entry to Console mode, in accordance with MILSTD-1750. ENTERING CONSOLE MODE USING CONREQN Asserting CONREQN low for 2 machine cycles during normal operation will cause the processor to enter Console mode following the completion of the current instruction (but see note on Console inhibit). Whilst CONREQN is low, the device will loop round three machine cycles, one of which will perform a read of the command register (8402 16). The command is not executed whilst CONREQN remains low. CONREQN may stay low for as long as required. The user should load the system Console Command register with the desired command before asserting CONREQN high, at which point the requested command will be executed. The flowchart shows the remainder of the command operation. See Table 1 for command information. ENTERING CONSOLE MODE WITH BPT If the processor encounters a BPT instruction the processor will enter Console mode (but see note on Console inhibit) and will immediately process the Console command contained in the Command register. It is important, therefore, that the Command register is loaded before any BPT instructions may be encountered. Operation then continues as for CONREQN-initiated commands (see flowchart). AN3726-4.1 July 2002 CONSOLE INHIBIT When CONREQN is asserted low, the CPU checks its internal copy of the configuration register to see if a console is present. If console is entered via the BPT instruction, the CPU reads the system configuration word, hence giving dynamic control over console entry by BPT. If no console is declared in the configuration, CONREQN is ignored and BPT instructions are treated as NOPs. CONTROLLING THE PROCESSOR IN CONSOLE MODE When in Console mode the processor communicates with the system console via a number of locations in IO space, as listed below: Address 840216 C00016 400016 C00116 400116 Function Console command input Data input Data output Read Console Status (not used in MA31750) Clear Console (not used in MA31750) The user should provide a method of supplying values when these addresses are polled by the processor. A typical approach is to implement three IO-mapped registers which respond to the above addresses and which may be loaded from an external controller or banks of switches. The required action is communicated to the processor by placing the appropriate command at IO location 840216 and asserting CONREQN high. If the command takes an operand (such as a value to Write Register) then this should first be placed at location C00016. Following completion of the command, any results are returned via location 400016. Note that during XIO and Next XIO operations, external read XIO commands execute an extra read of the Data input register. This does not affect the operation in any way. Also note that the IO addresses C00116 and 400116 are enabled when Console mode is selected, but is not used as part of the Console Mode operation. Following the execution of the first command, the processor will halt (provided the command is not ‘continue’) and wait for a further negative edge on CONREQN. The next command to be executed should be set at address 840216 before the rising edge of CONREQN. Any number of commands may be issued in this way, using CONREQN to control execution and to signal the presence of a new command code to the processor. LEAVING CONSOLE MODE To release the MA31750 from Console mode, a ‘continue’ command should be issued. The instruction pipeline will be refilled with the 1750 instruction immediately following the point at which the Console request or BPT was registered; normal instruction execution then resumes from that point. 1/5 AN3726: MA31750 - Application Note 3 SINGLE STEP COMMAND SUMMARY Single step operation is also accomplished using a ‘continue’ command. Once Console mode has been entered, raising CONREQN will cause the processor to execute the command and leave Console mode. If the user reasserts CONREQN low after the 2nd internal cycle after the read and before the 2nd pipe-line pre-fetch, then exactly one 1750 instruction will be executed before the processor returns to Console mode. This allows the processor to step through the 1750 code one instruction at a time. Table 1 shows a summary of all commands available in Console mode, with a description of their function. Commands should be constructed according to Figure 1. It should be noted that although many of the internal registers are made available in Console mode, attempting to change them may produce predictable but unexpected results. In particular, temporary registers T0, T1 and T9-T11 are used by the Console interface to store operands such as the IC register prior to Console Mode entry. Command Continue Function Resumes normal MIL-STD-1750 operation. This command is also used for single stepping instructions. Read Register Places the contents of a specified internal register into the Console Output register (IO address 4000). The register to be accessed is specified as a value placed in the lower 12 bits of the Command register according to Table 2. Write Register Places the contents of the Console Input register (IO location C000) into a specified internal register. The register to be accessed is specified as a value placed in the lower 12 bits of the Command register according to Table 2. Read and Clear Places the contents of the 1750 Fault register into the Console Fault Register Output register and then clears the Fault Register. Write Status Word Copies the contents of the Console Input register to the 1750defined Status Word register. Note that the A reg is changed to 200E. Read memory The contents of operand memory space at address A (the contents of the Alternate Address register) are placed in the Console Output register. Write memory The contents of the Console Input register are placed in operand memory space at address A. Read next memory The contents of the A register is incremented. The contents of operand memory space at address A are then placed in the Console Output register. Write next memory The contents of the A register is incremented. The contents of the Console Input register are then placed in operand memory space at address A. XIO The XIO command specified by the content of the A register is performed using data read from the Console Input register. If the XIO command is illegal the command is ignored. No Status Word Processor State checking is performed. Next XIO As above, but the command in A is incremented before the XIO is attempted. Disable Console operation is suspended pending a new Console request or an interrupt. If an interrupt occurs then the Instruction Counter will be restored and normal MIL-STD-1750 operation will be resumed with the interrupt service routine. Reserved Reserved for internal use by GPS - do not use. Other... Any other command not described above is ignored and has no action. User should reload Command register with correct value as for a new instruction. Code 0 1 2 3 4 5 6 7 8 9 A B C X Table 1: Console Instructions 0 3 Command Code 4 10 0000000 Figure 1: Command Register Format 2/5 11 15 Register Code AN3726: MA31750 - Application Note 3 Register R0-R15 T0-T11 A IC Register Description General purpose register R0-R15 Microcode registers T0-T11 Operand or alternate address register Instruction Counter (take great care when modifying this value) Code (bottom 12 bits) 000-00F 010-01B 01C 01D Table 2: Register Map CONREQN low Is console present in internal config word? No BPT instruction Yes Has current 1750 instruction finished? Processor waits for CONREQN high before proceeding. Read system configuration word No Yes Continue with normal operation No Is console present? Read command register @ 8402 No Yes Is CONREQN high? ** Processor executes Console Command immediately Yes Disable Processor leaves Console Mode if a Pending Interrupt is asserted Execute command Specified operation is performed. Pending Interrupt? Continue Processor leaves Console Mode Yes No No Is CONREQN low? No Is CONREQN low? Yes Yes ** CONREQN is sampled during the 1st internal cycle in the console loop Processor exits console mode with CONREQN high. Pipeline is refilled and normal execution is resumed. At least one 1750 instruction is executed. Figure 2: Console Operation Flowchart 3/5 AN3726: MA31750 - Application Note 3 7 internal cycles 7 internal cycles A[0:15] x x+1 x+2 8402 x+1 x+2 x+1 x+2 AS CONREQN console cmd reg 0000 Figure 3: Entering Console Mode 6 internal cycles A[0:15] 8402 8402 AS CONREQN console cmd reg 0000 Figure 4: Exiting Console Mode 4/5 POWER ASSEMBLY CAPABILITY The Power Assembly group was set up to provide a support service for those customers requiring more than the basic semiconductor, and has developed a flexible range of heatsink and clamping systems in line with advances in device voltages and current capability of our semiconductors. We offer an extensive range of air and liquid cooled assemblies covering the full range of circuit designs in general use today. The Assembly group offers high quality engineering support dedicated to designing new units to satisfy the growing needs of our customers. Using the latest CAD methods our team of design and applications engineers aim to provide the Power Assembly Complete Solution (PACs). HEATSINKS The Power Assembly group has its own proprietary range of extruded aluminium heatsinks which have been designed to optimise the performance of Dynex semiconductors. Data with respect to air natural, forced air and liquid cooling (with flow rates) is available on request. For further information on device clamps, heatsinks and assemblies, please contact your nearest sales representative or Customer Services. http://www.dynexsemi.com e-mail: [email protected] HEADQUARTERS OPERATIONS DYNEX SEMICONDUCTOR LTD Doddington Road, Lincoln. Lincolnshire. LN6 3LF. United Kingdom. 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