CXK77920TM/YM-11/12/15 262144-word x 9-bit High Speed Synchronous Static RAM Description The CXK77920TM/YM is a high speed CMOS synchronous static RAM with common l/O pins, organized as 262144-word-by-9-bit. This synchronous SRAM integrates input registers, high speed SRAM and output registers onto a single monolithic IC. All input signals are latched at the positive edge of an external clock (CLK). The RAM data from the previous cycle is presented at the positive edge of the subsequent clock cycle. Write operation is initiated by the positive edge of CLK and is internally self-timed. This feature eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals. 90MHz operation is obtained from a single 5V power supply. CXK77920YM 44pin TSOP (II) (Plastic) CXK77920TM 44pin TSOP (II) (Plastic) Structure Silicon gate CMOS IC Features Function There are three possible user transactions with the STRAM: Read operation, write operation and deselect operation. • The read operation requires WE = “HIGH” and OE = CE = “LOW” on the positive edge of CLK. • Fast cycle time: (Cycle) (Frequency) CXK77920TM/YM-11 11.0ns 90MHz CXK77920TM/YM-12 12.5ns 80MHz CXK77920TM/YM-15 15.0ns 66.7MHz • Fast clock to data valid The memory location pointed to by the contents of the Address registers is read internally and the contents of the location are captured in the Data-out registers on the next positive edge of CLK. The state of Data-out will reflect the contents of the Data-out registers. • The write operation requires CE = WE = “LOW” on the positive edge of CLK. The memory location pointed to by the contents of the Address registers is written with the contents of the Data-in registers. The write operation is entirely self-timed, eliminating critical timing edges. • The deselect cycle requires CE = “HIGH” or OE = WE = “HIGH” on the positive edge of CLK. Write operation and internal read operation are disabled during the clock cycle. The data outputs are forced to a high impedance state during the next clock cycle. During the deselect cycle by CE = “HIGH”, STRAM turns to power down mode. CXK77920TM/YM-11 6.0ns CXK77920TM/YM-12 6.5ns CXK77920TM/YM-15 7.0ns • High speed, low power consumption • Single +5V power supply: 5V±5% • Separate output power supply: 3.15 to 5.25V • Inputs and outputs are TTL compatible (3.3V l/O compatible) • Common data input and output • All inputs and outputs are registered on a single clock edge • Self-timed write cycle • Package line-up: 400mil, 44 pin TSOP II with 0.8mm pitch Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93Z08-ST CXK77920TM/YM Pin Configuration (Top View) CXK77920TM Pin Description (1) Symbol Description A0 to A17 Address input I/O0 to l/O8 Data input/output CLK Clock CE Chip enable input WE Write enable input OE Output enable input VCCQ Output power supply VCC +5V power supply VSS/VSSQ Ground 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 A3 OE VCCQ I/O0 I/O1 I/O2 VSSQ VSS VCC VCCQ I/O3 I/O4 VSSQ CLK A4 A5 A6 A7 A8 A0 A1 A2 A3 OE VCCQ I/O0 I/O1 I/O2 VSSQ VSS VCC VCCQ I/O3 I/O4 VSSQ CLK A4 A5 A6 A7 A8 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A17 A16 A15 A14 A13 CE VSSQ I/O8 I/O7 VCCQ VCC VSS VSSQ I/O6 I/O5 VCCQ WE A12 A11 A10 A9 NC Block Diagram CLK CE WE OE Register A17 A0 Register CLK Decoder Self-Timed Write Logic 256KX9 RAM CLK Sense Amp Register CLK I/O0 –2– CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Register A17 A16 A15 A14 A13 CE VSSQ I/O8 I/O7 VCCQ VCC VSS VSSQ I/O6 I/O5 VCCQ WE A12 A11 A10 A9 NC CXK77920YM Register I/O8 CXK77920TM/YM Pin Description (2) CLK (Clock, positive edge triggered) WE (Synchronous Write Enable, active low) All timing is controlled by the rising or positive edge of CLK. All synchronous input and output signals are registered on the positive edge of CLK with set-up and hold times referenced to that edge. Since only one edge of CLK is referenced, the duty cycle of CLK is not critical. WE is used to indicate whether a read or write operation is to be performed. WE is “LOW” to perform a write operation. WE is registered on every positive edge of CLK with set-up and hold times referenced to that edge. The internal timing required to store data into the memory array is self-timed. A0 to A17 (Address) The Address inputs are decoded on-chip to select one of 262,144 words. The state of the Address inputs is registered into the Address register on the positive edge of CLK. The Address inputs must be valid during every positive edge with all set-up and hold times referenced to that edge. I/O0 to l/O8 (Data input/output) I/O terminals are three-state and data input/output common. The state is defined by the Control block (refer to the truth table on page 4). The data inputs for write operation must be valid during every positive edge of CLK with all set-up and hold times referenced to that edge. The data outputs are triggered by the positive edge of CLK and the contents of the Output-Registers are presented. CE (Synchronous Chip Enable, active low) CE is used to select the Synchronous SRAM when low (or deselect when high). When selected, the Synchronous SRAM will perform a read or write operation (refer to the truth table on page 4). The state of CE is registered on every positive edge of CLK with set-up and hold times referenced to that edge. OE (Synchronous Output Enable, active low) OE is used to indicate that a read operation is to be performed. If the Synchronous SRAM is selected, the OE is low to perform a read operation (refer to the truth table on page 4). The state of OE is registered on every positive edge of CLK with set-up and hold times referenced to that edge. –3– CXK77920TM/YM Absolute Maximum Ratings (Ta = +25°C, GND = 0V) Item Symbol Rating Unit Supply voltage VCC –0.5 to +7.0 V Input voltage VIN –0.5 to VCC+0.5 V Output voltage VO –0.5 to VCC+0.5 V Allowable power dissipaiton PD 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +150 °C Tsolder 235 • 10 °C l sec Soldering temperature • time Truth Table CLK CE (tn) WE (tn) OE (tn) Mode I/O0 to l/O8 VCC Current H X X Deselect Hi-Z ISB L H H Read Hi-Z ICC L H L Read Data out (1) ICC L L X Write Data in ICC NOTES: 1. Data comes out on the next positive edge of CLK. X: “H” or “L” DC Recommended Operating Conditions Item Supply voltage Output supply voltage (Ta = +25°C, GND = 0V) Symbol Min. Typ. Max. Unit VCC 4.75 5.0 5.25 V VCCQ 3.15 — 5.25 V Input high voltage VIH 2.2 — VCC +0.3 V Input low voltage VIL –0.3(1) — 0.8 V NOTE: 1. VIL = –1.5V min. for pulse width less than 1ns. –4– CXK77920TM/YM Electrical Characteristics DC Characteristics Item (VCC = 5V ±5%, GND = 0V, Ta = 0 to = +70°C) Symbol Test Conditions Min. Max. Unit Input leakage current ILI VIN = GND to VCC –1 1 µA Output leakage current ILO VO = GND to VCC OE = VIH –1 1 µA Average operating ICC Duty = 100% Cycle = 90MHz — 180 IOUT = 0mA Cycle = 80MHz — 170 current Cycle = 66.7MHz mA — 160 Standby current ISB CE ≥ VIH Cycle Min, Duty = 100% — 130 mA Output high voltage VOH IOH = –2.0mA 2.4 — V Output low voltage VOL IOL = 4.0mA — 0.4 V I/O Capacitance Item (Ta = +25°C, f = 1MHz) Symbol Test Conditions Min. Max. Unit Input capacitance CIN VIN = 0V — 5 pF I/O capacitance CI/O Vl/O = 0V — 7 pF NOTE: This parameter is sampled and is not 100% tested. AC Characteristics AC Test Conditions (VCC = 5V±5%, Ta = 0 to +70°C) Item Conditions Input pulse high level VIH = 3.0V Input pulse low level VIL = 0V Input rise time tr = 3ns Input fall time tf = 3ns Input reference level 1.5V Output reference level 1.5V Output load conditions Figure 1 Output load (1) Output load (2)*2 5V I/O I/O 50pF*1 5pF*1 480Ω Ω 255Ω Ω *1. Including scope and jig capacitance. *2. tCKHQZ, tCKHQX Figure 1 –5– CXK77920TM/YM Read Cycle Item Symbol -11 Min. Max. -12 Min. Max. -15 Min. Max. Unit Read cycle time tCKHCKH 11 — 12.5 — 15 — ns Clock high pulse width tCKHCKL 3.5 — 4.0 — 5.0 — ns Clock low pulse width tCKLCKH 3.5 — 4.0 — 5.0 — ns Clock to data valid tCKHQV — 6.0 — 6.5 — 7.0 ns Address setup to clock high tAVCKH 2.5 — 2.5 — 3.0 — ns Address hold from clock high tCKHAX 0.5 — 0.5 — 0.5 — ns Chip enable setup to clock high tCEVCKH 2.5 — 2.5 — 3.0 — ns Chip enable hold from clock high tCKHCEX 0.5 — 0.5 — 0.5 — ns Output enable setup to clock high tOEVCKH 2.5 — 2.5 — 3.0 — ns Output enable hold from clock high tCKHOEX 0.5 — 0.5 — 0.5 — ns Clock high to output low-Z tCKHQX(1) 1.5 — 1.5 — 1.5 — ns Clock high to output high-Z tCKHQZ(1) — 4.5 — 5.0 — 6.0 ns NOTE: 1. Transition is measured +200mV from steady voltage with specified loading in Figure 1-(2). This parameter is sampled and is not 100% tested. Write Cycle Item Symbol -11 Min. Max. -12 Min. Max. -15 Min. Max. Unit Read cycle time tCKHCKH 11 — 12.5 — 15 — ns Clock high pulse width tCKHCKL 3.5 — 4.0 — 5.0 — ns Clock low pulse width tCKLCKH 3.5 — 4.0 — 5.0 — ns Address setup to clock high tAVCKH 2.5 — 2.5 — 3.0 — ns Address hold from clock high tCKHAX 0.5 — 0.5 — 0.5 — ns Chip enable setup to clock high tCEVCKH 2.5 — 2.5 — 3.0 — ns Chip enable hold from clock high tCKHCEX 0.5 — 0.5 — 0.5 — ns Write enable setup to clock high tWEVCKH 2.5 — 2.5 — 3.0 — ns Write enable hold from clock high tCKHWEX 0.5 — 0.5 — 0.5 — ns Input data setup to clock high tDVCKH 2.5 — 2.5 — 3.0 — ns Input data hold from clock high tCKHDX 0.5 — 0.5 — 0.5 — ns –6– CXK77920TM/YM Timing Waveform Read Cycle CLK tAVCKH tCKHAX tCKHCKH tCKHCKL n Address n+1 tCKLCKH n+2 WE tWEVCKH tCKHWEX tCEVCKH tCKHCEX CE OE tOEVCKH tCKHOEX Data out tCKHQV (1) (1) Qn–2 Qn–1 NOTE: 1. Valid data from CLK high is the data from the previous cycle. –7– (1) Qn CXK77920TM/YM Write Cycle: OE = VIH or VIL CLK tAVCKH tCKHAX Address tCKHCKH tCKHCKL n tCKLCKH n+1 n+2 Dn+1 Dn+2 tCEVCKH tCKHCEX CE tWEVCKH tCKHWEX WE tOECKH tCKHOEX OE tDVCKH tCKHDX Data in Dn –8– CXK77920TM/YM Read/Write Cycle CLK tAVCKH tCKHAX n Address tCKHCKL tCKHCKH n+1 tCKLCKH n+2 tCECKH tCKHCEX CE tWEVCKH tCKHWEX WE tOEVCKH tCKHOEX OE tDVCKH tCKHDX I/O Qn-2 tCKHQX Dn Qn+1 tCKHQZ tCKHQV –9– CXK77920TM/YM Example of Representative Characteristics Supply Current vs. Ambient Temperature Supply Current vs. Supply Voltage 1.4 ICC—Supply Current (Normalized) ICC—Supply Current (Normalized) 1.4 1.2 ICC 1.0 0.8 Ta = +25°C 0.6 4.5 5.25 4.75 5.0 VCC—Supply Voltage (V) 1.2 ICC 1.0 0.8 VCC = 5.0V 0.6 5.5 0 60 80 tCKHQV — Access Time (Normalized) 1.4 1.0 Read, Write 0.8 0.6 VCC = 5.0V Ta = +25°C 0.4 1.2 1.0 0.8 VCC = 5.0V Ta = +25°C 0.6 20 40 60 80 75 25 50 CL—Load Capacitance (pF) 0 100 Frequency (1/tCKHCKH) (MHz) 1.4 tCKHCKH — Cycle Time, tCKHQV — Access Time (Normalized) 1.4 1.2 tCKHQV 1.0 tCKHQV tCKHCKH tCKHCKH 0.8 Ta = +25°C 0.6 4.5 100 Cycle Time (minimum) / Access Time vs. Ambient Temperature Cycle Time (minimum) / Access Time vs. Supply Voltage tCKHCKH — Cycle Time, tCKHQV — Access Time (Normalized) 40 Access Time vs. Load Capacitance Supply Current vs. Frequency 1.2 ICC—Supply Current (Normalized) 20 Ta—Ambient Temperature (°C) 4.75 5.0 5.25 1.2 tCKHCKH 1.0 tCKHQV 0.8 VCC = 5.0V 0.6 5.5 VCC—Supply Voltage (V) 0 20 40 60 Ta—Ambient Temperature (°C) –10– 80 CXK77920TM/YM Standby Current vs. Ambient Temperature Standby Current vs. Supply Voltage 1.8 ISB—Standby Current (Normalized) ISB—Standby Current (Normalized) 1.4 1.2 ISB 1.0 0.8 Ta = +25°C 0.6 4.5 1.4 1.0 0.6 VCC = 5.0V 0.2 4.75 5.0 5.25 5.5 0 20 VCC—Supply Voltage (V) 80 1.4 VIL, VIH—Input Voltage (Normalized) VIL, VIH—Input Voltage (Normalized) 60 Input Voltage Level vs. Ambient Temperature Input Voltage Level vs. Supply Voltage 1.4 1.2 1.0 VIH, VIL 0.8 Ta = +25°C 0.6 4.5 1.2 VIH 1.0 VIL 0.8 VCC = 5.0V 0.6 4.75 5.0 5.25 0 5.5 20 40 60 80 VCC—Supply Voltage (V) Ta—Ambient Temperature (°C) Output Low Current vs. Output Low Voltage Output High Current vs. Output High Voltage 1.8 4 IOH, Output High Current (Normalized) IOL, Output Low Current (Normalized) 40 Ta—Ambient Temperature (°C) 1.4 1.0 0.6 VCC = 5.0V Ta = +25°C 0.2 0 0.2 0.4 0.6 2 1 0 0.8 VOL—Output Low Voltage (V) VCC = 5.0V Ta = +25°C 3 0 1 2 3 VOH—Output High Voltage (V) –11– 4 CXK77920TM/YM Package Dimensions Unit: mm 44 PIN TSOP (II) (PLASTIC) 400MIL CXK77920TM 1.2MAX *18.41±0.1 0.1 44 1 11.76±0.2 *10.16±0.1 23 +0.05 0.125-0.02 22 0.8 0.3±0.1 A 0.13 M B (0.125) (0.3) 0.145±0.55 0.32±0.08 0.5 ±0.1 +0.1 0.1 -0.05 0°-10° Detail A Detail B NOTE>Dimension “*” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE TSOP(II)-44P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE TSOP(II)044-P-0400-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.5g JEDEC CODE 44 PIN TSOP (II) (PLASTIC) 400MIL CXK77920YM 1.2MAX *18.41 ±0.1 0.1 1 11.76±0.2 44 *10.16±0.1 22 0.13 M +0.05 0.125-0.02 23 0.8 0.3±0.1 A B 0.145±0.55 (0.3) (0.125) 0.32±0.08 0.5 ±0.1 +0.1 0.1 -0.05 0°-10° Detail A Detail B NOTE>Dimension “*” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE TSOP(II)-44P-L01R LEAD TREATMENT SOLDER PLATING EIAJ CODE TSOP(II)044-P-0400-B LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.5g JEDEC CODE –12–