AD ADG659YRU

+3 V/+5 V/±5 V CMOS 4-/8-Channel
Analog Multiplexers
ADG658/ADG659
FEATURES
±2 V to ±6 V Dual Supply
2 V to 12 V Single Supply
Automotive Temperature Range –40oC to +125oC
<0.1 nA Leakage Currents
45  On Resistance over Full Signal Range
Rail-to-Rail Switching Operation
Single 8-to-1 Multiplexer ADG658
Differential 4-to-1 Multiplexer ADG659
16-Lead LFCSP/TSSOP Packages
Typical Power Consumption <0.1 W
TTL/CMOS Compatible Inputs
Package Upgrades to 74HC4051/74HC4052 and
MAX4051/MAX4052/MAX4581/MAX4582
APPLICATIONS
Automotive Applications
Automatic Test Equipment
Data Acquisition Systems
Battery-Powered Systems
Communication Systems
Audio and Video Signal Routing
Relay Replacement
Sample-and-Hold Systems
Industrial Control Systems
FUNCTIONAL BLOCK DIAGRAM
ADG658
ADG659
S1
S1A
DA
S4A
D
S1B
DB
S8
S4B
1 OF 8
DECODER
A0
A1
A2
1 OF 4
DECODER
EN
A0
A1
EN
SWITCHES SHOWN FOR A LOGIC 1 INPUT
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG658 and ADG659 are low voltage, CMOS analog
multiplexers comprised of eight single channels and four differential channels, respectively. The ADG658 switches one of
eight inputs (S1–S8) to a common output, D, as determined by
the 3-bit binary address lines A0, A1, and A2. The ADG659
switches one of four differential inputs to a common differential
output, as determined by the 2-bit binary address lines A0 and
A1. An EN input on both devices is used to enable or disable
the device. When disabled, all channels are switched off.
1. Single- and dual-supply operation. The ADG658 and
ADG659 offer high performance and are fully specified
and guaranteed with ±5 V, +5 V, and +3 V supply rails.
2. Automotive temperature range –40 oC to +125oC.
3. Low power consumption, typically <0.1 W.

4. 16-lead 4 mm  4 mm LFCSP packages and 16-lead
TSSOP package.
These parts are designed on an enhanced process that provides
lower power dissipation yet gives high switching speeds. These
parts can operate equally well as either multiplexers or demultiplexers and have an input range that extends to the supplies. All
channels exhibit break-before-make switching action, preventing momentary shorting when switching channels. All digital
inputs have 0.8 V to 2.4 V logic thresholds, ensuring TTL/
CMOS logic compatibility when using single +5 V or dual
±5 V supplies.
The ADG658 and ADG659 are available in 16-lead TSSOP
packages and 16-lead 4 mm  4 mm LFCSP packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks
and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
ADG658/ADG659–SPECIFICATIONS
DUAL SUPPLY1 (V
DD
= +5 V ±10%, VSS = –5 V ±10%, GND = 0 V, unless otherwise noted.)
Parameter
+25C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON )
45
75
1.3
3
10
16
On Resistance Match between
Channels ((RON )
On Resistance Flatness (R FLAT(ON))
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
B Version
–40C
to +85C
Y Version
–40C
to +125C
VSS to V DD
90
100
3.2
3.5
17
18
±0.005
±0.2
±0.005
±0.2
±0.1
±0.005
±0.2
±0.1
Unit
Test Conditions/Comments
V
 typ
 max
 typ
 max
 typ
 max
V DD = +4.5 V, VSS = –4.5 V
VS = ±4.5 V, IS = 1 mA;
Test Circuit 1
VS = 3.5 V, IS = 1 mA
V DD = +5 V, VSS = –5 V;
VS = ±3 V, IS = 1 mA
V DD = +5.5 V, VSS = –5.5 V
V D = ±4.5 V, VS = 4.5 V;
Test Circuit 2
V D = ±4.5 V, VS = 4.5 V;
Test Circuit 3
±5
±2.5
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
2.4
0.8
V min
V max
±1
µA typ
µA max
pF typ
V IN = V INL or V INH
Off Isolation
2
4
–90
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC max
dB typ
R L = 300 , CL = 35 pF
VS = 3 V; Test Circuit 5
R L = 300 , CL = 35 pF
VS = 3 V; Test Circuit 7
R L = 300 , CL = 35 pF
VS = 3 V; Test Circuit 7
R L = 300 , CL = 35 pF
VS1 = VS2 = 3 V; Test Circuit 6
VS = 0 V, R S = 0 ,
CL = 1 nF; Test Circuit 8
R L = 50 , CL = 5 pF,
f = 1 MHz; Test Circuit 9
Total Harmonic Distortion, THD + N
0.025
% typ
Channel-to-Channel Crosstalk
(ADG659)
–3 dB Bandwidth
ADG658
ADG659
CS (OFF)
CD (OFF)
ADG658
ADG659
CD, CS (ON)
ADG658
ADG659
–90
dB typ
RL = 600 , 2 V p-p,
f = 20 Hz to 20 kHz
210
400
4
MHz typ
MHz typ
pF typ
R L = 50 , CL = 5 pF;
Test Circuit 10
f = 1 MHz
23
12
pF typ
pF typ
f = 1 MHz
f = 1 MHz
28
16
pF typ
pF typ
f = 1 MHz
f = 1 MHz
0.01
µA typ
µA max
µA typ
µA max
Drain OFF Leakage I D (OFF)
ADG658
ADG659
Channel ON Leakage I D, IS (ON)
ADG658
ADG659
DIGITAL INPUTS
Input High Voltage, V INH
Input Low Voltage, V INL
Input Current
I INL or I INH
2
tOFF (EN)
Break-Before-Make Time Delay, t BBM
Charge Injection
ISS
V D = VS = ±4.5 V; Test Circuit 4
2
tON (EN)
POWER REQUIREMENTS
I DD
±5
±2.5
0.005
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS
tTRANS
±5
80
115
80
115
30
45
50
140
165
140
165
50
55
10
1
0.01
1
R L = 50 , CL = 5 pF,
f = 1 MHz; Test Circuit 11
V DD = +5.5 V, VSS = –5.5 V
Digital Inputs = 0 V or 5.5 V
Digital Inputs = 0 V or 5.5 V
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C. Y Version: –40°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
1
SINGLE SUPPLY
ADG658/ADG659
(VDD = 5 V ±10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
Parameter
+25C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON )
On Resistance Match between
Channels ((RON )
On Resistance Flatness (R FLAT(ON))
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
DIGITAL INPUTS
Input High Voltage, V INH
Input Low Voltage, V INL
Input Current
I INL or I INH
Break-Before-Make Time Delay, t BBM
POWER REQUIREMENTS
I DD
9
14
10
16
V
 typ
 max
 typ
 max
 typ
V DD = 4.5 V, VSS = 0 V
VS = 0 V to 4.5 V, IS = 1 mA;
Test Circuit 1
VS = 3.5 V, IS = 1 mA
V DD = 5 V, VSS = 0 V
VS = 1.5 V to 4 V, IS = 1 mA
V DD = 5.5 V
VS = 1 V/4.5 V, V D = 4.5 V/1 V;
Test Circuit 2
VS = 1 V/4.5 V, V D = 4.5 V/1 V;
Test Circuit 3
±5
±2.5
2.4
0.8
V min
V max
±1
µA typ
µA max
pF typ
V IN = V INL or V INH
0.5
1
–90
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC max
dB typ
–90
dB typ
R L = 300 , CL = 35 pF
VS = 3 V; Test Circuit 5
R L = 300 , CL = 35 pF
VS = 3 V; Test Circuit 7
R L = 300 , CL = 35 pF
VS = 3 V; Test Circuit 7
R L = 300 , CL = 35 pF
VS1 = VS2 = 3 V; Test Circuit 6
VS = 2.5 V, R S = 0 , CL = 1 nF;
Test Circuit 8
R L = 50 , CL = 5 pF, f = 1 MHz;
Test Circuit 9
R L = 50 , CL = 5 pF; f = 1 MHz;
Test Circuit 11
180
330
5
MHz typ
MHz typ
pF typ
R L = 50 , CL = 5 pF;
Test Circuit 10
f = 1 MHz
29
15
pF typ
pF typ
f = 1 MHz
f = 1 MHz
30
16
pF typ
pF typ
f = 1 MHz
f = 1 MHz
0.01
µA typ
µA max
±5
±5
±2.5
120
200
120
190
35
50
100
270
300
245
280
60
70
10
1
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C. Y Version: –40°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
Test Conditions/Comments
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
2
tOFF (EN)
Channel-to-Channel Crosstalk
(ADG659)
–3 dB Bandwidth
ADG658
ADG659
CS (OFF)
CD (OFF)
ADG658
ADG659
CD, CS (ON)
ADG658
ADG659
200
Unit
VS = V D = 1 V or 4.5 V, Test Circuit 4
2
tON (EN)
Off Isolation
160
0.005
CIN, Digital Input Capacitance
Charge Injection
Y Version
–40C
to +125C
0 to VDD
±0.005
±0.2
±0.005
±0.2
±0.1
±0.005
±0.2
±0.1
Drain OFF Leakage I D (OFF)
ADG658
ADG659
Channel ON Leakage I D, IS (ON)
ADG658
ADG659
DYNAMIC CHARACTERISTICS
tTRANS
85
150
4.5
8
13
B Version
–40C
to +85C
–3–
V DD = 5.5 V
Digital Inputs = 0 V or 5.5 V
ADG658/ADG659–SPECIFICATIONS
SINGLE SUPPLY1 (V
DD
= 2.7 V to 3.6 V, VSS = 0 V, GND = 0 V, unless otherwise noted.)
Parameter
+25C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON )
185
300
2
4.5
On Resistance Match between
Channels ((RON )
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
DIGITAL INPUTS
Input High Voltage, V INH
Input Low Voltage, V INL
Input Current
I INL or I INH
Break-Before-Make Time Delay, t BBM
POWER REQUIREMENTS
I DD
6
7
Test Conditions/Comments
V
 typ
 max
 typ
 max
V DD = 2.7 V, VSS = 0 V
VS = 0 V to 2.7 V, IS = 0.1 mA;
Test Circuit 1
VS = 1.5 V, IS = 0.1 mA
V DD = 3.3 V
VS = 1 V/3 V, V D = 3 V/1 V;
Test Circuit 2
VS = 1 V/3 V, V D = 3 V/1 V;
Test Circuit 3
±5
±2.5
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
2.0
0.5
V min
V max
±1
µA typ
µA max
pF typ
V IN = V INL or V INH
1
2
–90
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC max
dB typ
–90
dB typ
R L = 300 , CL = 35 pF
VS = 1.5 V; Test Circuit 7
R L = 300 , CL = 35 pF
VS = 1.5 V; Test Circuit 7
R L = 300 , CL = 35 pF
VS = 1.5 V; Test Circuit 7
R L = 300 , CL = 35 pF
VS1 = VS2 = 1.5 V; Test Circuit 6
VS = 1.5 V, R S = 0 , CL = 1 nF;
Test Circuit 8
R L = 50 , CL = 5 pF, f = 1 MHz;
Test Circuit 9
R L = 50 , CL = 5 pF, f = 1 MHz;
Test Circuit 11
160
300
5
MHz typ
MHz typ
pF typ
R L = 50 , CL = 5 pF;
Test Circuit 10
f = 1 MHz
29
15
pF typ
pF typ
f = 1 MHz
f = 1 MHz
30
16
pF typ
pF typ
f = 1 MHz
f = 1 MHz
0.01
µA typ
µA max
±5
±5
±2.5
2
tOFF (EN)
Channel-to-Channel Crosstalk
(ADG659)
–3 dB Bandwidth
ADG658
ADG659
CS (OFF)
CD (OFF)
ADG658
ADG659
CD, CS (ON)
ADG658
ADG659
400
Unit
VS = V D = 1 V or 3 V; Test Circuit 4
2
tON (EN)
Off Isolation
350
0.005
CIN, Digital Input Capacitance
Charge Injection
Y Version
–40C
to +125C
0 to V DD
±0.005
±0.2
±0.005
±0.2
±0.1
±0.005
±0.2
±0.1
Drain OFF Leakage I D (OFF)
ADG658
ADG659
Channel ON Leakage I D, IS (ON)
ADG658
ADG659
DYNAMIC CHARACTERISTICS
tTRANS
B Version
–40C
to +85C
200
370
230
370
50
80
200
440
490
440
490
90
110
10
1
V DD = 3.6 V
Digital Inputs = 0 V or 3.6 V
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C. Y Version: –40°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. 0
ADG658/ADG659
␪JA Thermal Impedance, 16-Lead TSSOP . . . . . 150.4°C/W
␪JA Thermal Impedance (4-Layer Board),
16-Lead LFCSP . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 kV
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C, unless otherwise noted.)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +13 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –6.5 V
Analog Inputs2 . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
Digital Inputs2 . . . . . . . . . . . . GND – 0.3 V to VDD + 0.3 V
or 10 mA, whichever occurs first
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . 40 mA
(Pulsed at 1 ms, 10% duty cycle max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature Range
Automotive (Y Version) . . . . . . . . . . . . –40°C to +125°C
Industrial (B Version) . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability. Only one
absolute maximum rating may be applied at any one time.
2Overvoltages at A
X, EN, S, or D will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the ADG658/
ADG659 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected
to high energy electrostatic discharges. Therefore, proper ESD precautions are recom mended to avoid
per for mance deg radation or loss of functionality.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADG658YRU
ADG658YCP
ADG659YRU
ADG659YCP
–40°C to +125°C
–40°C to +85°C
–40°C to +125°C
–40°C to +85°C
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP)
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP)
RU-16
CP-16
RU-16
CP-16
PIN CONFIGURATIONS
Table I. ADG658 Truth Table
A2
A1
A0
EN
Switch Condition
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
NONE
1
2
3
4
5
6
7
8
TSSOP
S5 1
16
VDD
S1B 1
16
VDD
S7 2
15
S3
S3B 2
15
S3A
14
S2
DB 3
14
S2A
TOP VIEW 13 S1
S6 5 (Not to Scale) 12 S4
S4B 4
D 3
ADG658
S8 4
ADG659
TOP VIEW 13 DA
S2B 5 (Not to Scale) 12 S1A
EN 6
11
A0
EN 6
11
S4A
VSS 7
10
A1
VSS 7
10
A0
GND 8
9
A2
GND 8
9
A1
X = Don’t Care
1
0
0
0
0
NONE
1
2
3
4
16 15 14 13
D 1
S8 2
S6 3
EN 4
REV. 0
TOP VIEW
(Not to Scale)
5
VSS
X = Don’t Care
–5–
16 15 14 13
S2
S1
10 S4
9 A0
12
ADG658
6
7
8
S3A
X
0
1
0
1
11
DB 1
S4B 2
S2B 3
EN 4
S2A
DA
10 S1A
9 S4A
12
ADG659
TOP VIEW
(Not to Scale)
5
VSS
X
0
0
1
1
6
7
8
GND
A1
A0
On Switch Pair
S3
EN
S7
S5
VDD
A0
GND
A2
A1
A1
S3B
S1B
VDD
LFCSP
Table II. ADG659 Truth Table
11
ADG658/ADG659
TERMINOLOGY
Parameter
VDD
VSS
IDD
ISS
GND
S
D
AX
EN
VD (VS)
RON
RON
RFLAT(ON)
IS (OFF)
ID (OFF)
ID, IS (ON)
VINL
VINH
IINL(IINH)
CS (OFF)
CD (OFF)
CD, CS (ON)
CIN
tON
tOFF
tBBM
Charge Injection
Off Isolation
Crosstalk
Bandwidth
On Response
Insertion Loss
Description
Most Positive Power Supply Potential.
Most Negative Power Supply Potential.
Positive Supply Current.
Negative Supply Current.
Ground (0 V) Reference.
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input.
Active Low Digital Input. When high, device is disabled and all switches are OFF. When low, AX logic inputs
determine ON switch.
Analog Voltage on Terminals D, S.
Ohmic Resistance between D and S.
On Resistance Match between Any Two Channels, i.e., RON max – RON min.
Flatness is defined as the difference between the maximum and minimum value of ON Resistance as
measured over the specified analog signal range.
Source Leakage Current with the Switch OFF.
Drain Leakage Current with the Switch OFF.
Channel Leakage Current with the Switch ON.
Maximum Input Voltage for Logic 0.
Minimum Input Voltage for Logic 1.
Input Current of the Digital Input.
OFF Switch Source Capacitance. Measured with reference to ground.
OFF Switch Drain Capacitance. Measured with reference to ground.
ON Switch Capacitance. Measured with reference to ground.
Digital Input Capacitance.
Delay between Applying the Digital Control Input and the Output Switching ON. See Test Circuit 7.
Delay between Applying the Digital Control Input and the Output Switching OFF.
ON Time. Measured between 80% points of both switches when switching from one address state to another.
Measure of the Glitch Impulse Transferred from the Digital Input to the Analog Output during Switching.
Measure of Unwanted Signal Coupling through an OFF Switch.
Measure of Unwanted Signal Coupled through from One Channel to Another as a Result of Parasitic Capacitance.
The Frequency at which the Output is Attenuated by 3 dB.
The Frequency Response of the ON Switch.
The Loss Due to the ON Resistance of the Switch.
–6–
REV. 0
Typical Performance Characteristics–ADG658/ADG659
250
100
40
VDD, VSS = 5.5V
VDD, VSS = 4.5V
VDD = 3V
150
VDD = 3.3V
100
VDD = 4.5V
VDD = 5.5V
50
VDD, VSS = 5V
10
0
–5.5
–3.5
–1.5
0.5
VD, VS – V
2.5
0
4.5
TPC 1. On Resistance vs. VD (VS)
for Dual Supply
140
ON RESISTANCE – 
80
+25C
60
40
–40C
0
1.0
0.5
10
6
8
VD, VS – V
+85C +125C
QINJ – PC
ID (OFF)
IS, ID (ON)
–2.5
200
150
100
+25C
20
40
60
80
100
TEMPERATURE C
3
4
5
0
0.5
IS (OFF)
0
–0.5
ID (OFF)
–1.0
IS, ID (ON)
–2.0
VDD = 3V
VSS = 0V
1.0
1.5
2.0
VD, VS – V
2.5
3.0
–2.5
0
100
40
60
80
TEMPERATURE C
20
120
TPC 6. Leakage Currents vs.
Temperature (Dual Supply)
140
TA = 25C
120
VDD = +5V
VSS = –5V
100
4
VDD = 5V
VSS = –5V
tON
80
60
tOFF
40
0
120
–4
20
VDD = 5V
VSS = 0V
–2
TPC 7. Leakage Currents vs.
Temperature (Single Supply)
REV. 0
2
–1.5
–40C
6
2
VDD = 3V
VSS = 0V
VD =  2.4V
VS =  1V
0
VDD = 5V
VSS = –5V
VD =  4V
VS =  4V
1.0
8
–2.0
–2 –1 0
1
VD, VS – V
10
0
–1.5
–5 –4 –3
0.5
12
–1.0
0
12
1.5
14
–0.5
VDD = 5V
VSS = –5V
10
TPC 5. On Resistance vs. VD (VS)
for Different Temperatures
(Single Supply)
IS (OFF)
–40C
300
0
1.5
VDD = 5V
VSS = 0V
VD =  4V
VS =  1V
40
30
TPC 3. On Resistance vs. VD (VS)
for Different Temperatures
(Dual Supply)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VD, VS – V
TPC 4. On Resistance vs. VD (VS)
for Different Temperatures
(Single Supply)
+25C
50
TPC 2. On Resistance vs. VD (VS)
for Single Supply
50
VDD = 5V
VSS = 0V
+85C
60
TIME – ns
ON RESISTANCE – 
+85C
20
CURRENT – nA
4
2
70
20
VDD = 10V
250
100
0
0
VDD = 5V
VDD = 12V
+125C
120
ON RESISTANCE – 
VDD, VSS = 3V
50
+125C
80
CURRENT – nA
60
ON RESISTANCE – 
ON RESISTANCE – 
200
70
20
90
VDD = 2.7V
VDD, VSS = 2.7V
80
30
100
TA = 25C
TA = 25C
90
–5 –4
–3 –2 –1
1
0
VS – V
2
3
TPC 8. Charge Injection vs.
Source Voltage
–7–
4
5
0
–40 –20
0
20
40 60 80
TEMPERATURE – C
100 120
TPC 9. tON/tOFF Times vs.
Temperature (Dual Supply)
ADG658/ADG659
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
VSS = 0V
VDD = 3V
300
200
VDD = 5V
dB
tON
150
100
VDD = 3V
50
tOFF
0
–40 –20
0
VDD = 5V
20
40 60 80
TEMPERATURE – C
100 120
–4
–6
–8
–10
–16
–18
VDD = +5V
VSS = –5V
TA = 25C
100k
TPC 10. tON/tOFF Times vs.
Temperature (Single Supply)
0
–10
VDD = +5V
VSS = –5V
TA = 25C
–22
1M
10M
FREQUENCY – Hz
–24
100M
100
–30
–50
dB
–60
–70
–80
–80
100k
1M
10M
100M
FREQUENCY – Hz
600
IN AND OUT
VDD = +5V
VSS = –5V
TA = 25C
10
–40
–60
VDD = +5V
VSS = –5V
TA = 25C
TPC 12. ON Response vs.
Frequency (ADG659)
VDD = –5V
VSS = +5V
TA = 25C
–20
–40
dB
–20
TPC 11. ON Response vs.
Frequency (ADG658)
0
–20
–12
–14
THD + N – %
TIME – ns
250
0
–2
dB
350
1
–90
0.1
–100
–100
–110
–120
–130
–120
100k
1M
10M
100M
FREQUENCY – Hz
TPC 13. OFF Isolation vs. Frequency
LOGIC THRESHOLD VOLTAGE – V
1000
VDD = 12V
IDD – A
100
VDD = 5V
VDD = 3V
0.1
0.01
0
2
4
6
8
V(EN) – V
10
50 100 200
500 1k 2k
5k 10k 20k
FREQUENCY – Hz
TPC 15. THD + Noise
3.0
VSS = 0V
1
0.01
20
1M
10M
100M
FREQUENCY – Hz
TPC 14. Crosstalk vs. Frequency
10000
10
100k
12
TPC 16. VDD Current vs. Logic Level
2.5
2.0
1.5
1.0
0.5
0
0
2
4
6
VDD – V
8
10
12
TPC 17. Logic Threshold
Voltage vs. Supply Voltage
–8–
REV. 0
ADG658/ADG659
Test Circuits
IDS
VDD
VSS
VDD
VSS
V1
S1
D
S
D
S2
VS
ID (OFF)
A
VO
S8
VS
EN
GND
LOGIC 1
RON = V1/I DS
Test Circuit 3. ID (OFF)
Test Circuit 1. On Resistance
IS (OFF)
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
S1
A
S1
D
S2
VS
S8
VD
LOGIC 1
EN
GND
VIN
50
VSS
VDD
A2
VSS
A1
A0
GND
Test Circuit 4. ID (ON)
ADDRESS
DRIVE (VIN)
VS1
S8
VS8
50%
RL
300
VS1
VOUT
D
GND
50%
0V
S2 THRU S7
EN
VD
3V
S1
ADG658*
A
EN
VS
Test Circuit 2. IS (OFF)
VDD
ID (ON)
D
S8
CL
35pF
90%
VOUT
90%
VS8
*SIMILAR CONNECTION FOR ADG659
tTRANSITION
tTRANSITION
Test Circuit 5. Switching Time of Multiplexer, tTRANSITION
VIN
50
VDD
VSS
VDD
A2
VSS
A1
A0
3V
ADDRESS
DRIVE (VIN)
VS
S1
0V
S2 THRU S7
ADG658*
S8
VOUT
D
EN
GND
RL
300
CL
35pF
VOUT
80%
tBBM
*SIMILAR CONNECTION FOR ADG659
Test Circuit 6. Break-Before-Make Delay, tBBM
REV. 0
80%
–9–
ADG658/ADG659
VDD
VSS
VDD
VSS
A2
3V
ENABLE
DRIVE (VIN)
VS
S1
A1
50%
0V
A0
S2–S8
tOFF (EN)
ADG658*
D
EN
VIN
50%
GND
50
CL
35pF
RL
300
VO
VOUT
0.9VO
0.9VO
OUTPUT
0V
tON (EN)
*SIMILAR CONNECTION FOR ADG659
Test Circuit 7. Enable Delay, tON (EN
( ), tOFF (EN
(EN)
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Test Circuit 8. Charge Injection
VDD
VDD
A1
A0
NETWORK
ANALYZER
VSS
50
LOGIC 1
A1
A0
VS
D
EN
RL
50
GND
VS
VOUT
RL
50
GND
VOUT
VS
INSERTION LOSS = 20 LOG
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Test Circuit 10. Bandwidth
VDD
VSS
0.1F
A1
0.1F
VDD
VSS
A0
VS
50
S
D
Test Circuit 9. OFF Isolation
50
VSS
EN
VOUT
OFF ISOLATION = 20 LOG
NETWORK
ANALYZER
0.1F
VDD
A2
50
S
VSS
0.1F
0.1F
0.1F
A2
VDD
VSS
50
EN
ADG659
S1A
DA
S1B
DB
DB
DA
NETWORK
ANALYZER
RL
50
VOUT
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
VOUT
VS
Test Circuit 11. Channel-to-Channel Crosstalk
–10–
REV. 0
ADG658/ADG659
OUTLINE DIMENSIONS
16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.20
0.09
0.75
0.60
0.45
8
0
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153AB
16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm  4 mm Body
(CP-16)
Dimensions shown in millimeters
4.0
BSC SQ
PIN 1
INDICATOR
0.65 BSC
3.75
BSC SQ
TOP
VIEW
12 MAX
1.00
0.90
0.80
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
0.75
0.55
0.35
13
12
16
1
BOTTOM
VIEW
9
4
8
5
1.95 BSC
1.00 MAX
0.65 NOM
0.05 MAX
0.02 NOM
SEATING
PLANE
0.38
0.30
0.23
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
REV. 0
–11–
2.25
1.70 SQ
0.75
–12–
PRINTED IN U.S.A.
C03273–0–2/03(0)