AD ADG788

a
2.5 , 1.8 V to 5.5 V, 2.5 V Triple/Quad
SPDT Switches in Chip Scale Packages
ADG786/ADG788
FEATURES
1.8 V to 5.5 V Single Supply
2.5 V Dual Supply
2.5 On Resistance
0.5 On Resistance Flatness
100 pA Leakage Currents
19 ns Switching Times
Triple SPDT: ADG786
Quad SPDT: ADG788
20-Lead 4 mm 4 mm Chip Scale Packages
Low Power Consumption
TTL/CMOS-Compatible Inputs
For Functionally-Equivalent Devices in 16-Lead TSSOP
Packages, See ADG733/ADG734
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Battery-Powered Systems
GENERAL DESCRIPTION
The ADG786 and ADG788 are low voltage, CMOS devices
comprising three independently selectable SPDT (single pole,
double throw) switches and four independently selectable SPDT
switches respectively.
Low power consumption and operating supply range of 1.8 V to
5.5 V and dual ± 2.5 V make the ADG786 and ADG788 ideal
for battery powered, portable instruments and many other
applications. All channels exhibit break-before-make switching action preventing momentary shorting when switching
channels. An EN input on the ADG786 is used to enable or
disable the device. When disabled, all channels are switched OFF.
FUNCTIONAL BLOCK DIAGRAMS
ADG786
S1B
S1A
S4A
D2
D1
D1
S3A
S1A
S1B
S4B
IN1
IN4
D3
S3B
ADG788
S2A
D2
IN2
IN3
S2B
S3B
S2B
D2
LOGIC
S2A
A0
A1 A2
D3
S3A
EN
SWITCHES SHOWN FOR A LOGIC “1” INPUT
PRODUCT HIGHLIGHTS
1. Small 20-Lead 4 mm × 4 mm Chip Scale Packages (CSP).
2. Single/Dual Supply Operation. The ADG786 and ADG788
are fully specified and guaranteed with 3 V ± 10% and
5 V ± 10% single supply rails, and ± 2.5 V ± 10% dual
supply rails.
3. Low On Resistance (2.5 Ω typical).
4. Low Power Consumption (<0.01 µW).
5. Guaranteed Break-Before-Make Switching Action.
These multiplexers are designed on an enhanced submicron
process that provides low power dissipation yet gives high switching speed, very low on resistance, high signal bandwidths and
low leakage currents. On resistance is in the region of a few
ohms, is closely matched between switches and very flat over
the full signal range. These parts can operate equally well in
either direction and have an input signal range which extends to
the supplies.
The ADG786 and ADG788 are available in small 20-lead
chip scale packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADG786/ADG788–SPECIFICATIONS1 (V
B Version
–40C
+25C
to +85C
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
0 V to VDD
2.5
4.5
On-Resistance Match between
Channels (∆RON)
On-Resistance Flatness (RFLAT(ON))
5.0
0.1
0.4
0.5
1.2
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
± 0.01
± 0.1
± 0.01
± 0.1
0.005
CIN, Digital Input Capacitance
DD
= 5 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to VDD, IDS = 10 mA
VS = 0 V to VDD, IDS = 10 mA
VDD = 5.5 V
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 2
VD = VS = 1 V, or 4.5 V;
Test Circuit 3
± 0.5
nA typ
nA max
nA typ
nA max
2.4
0.8
V min
V max
± 0.1
µA typ
µA max
pF typ
VIN = VINL or VINH
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF;
VS1A = 3 V, VS1B = 0 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 6
VS = 2 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
RL = 50 Ω, CL = 5 pF, Test Circuit 10
f = 1 MHz
f = 1 MHz
± 0.3
4
2
DYNAMIC CHARACTERISTICS
tON
19
34
tOFF
7
ADG786 tON(EN)
20
12
40
tOFF(EN)
7
12
Break-Before-Make Time Delay, tD
13
Charge Injection
±3
Off Isolation
–72
dB typ
Channel-to-Channel Crosstalk
–67
dB typ
–3 dB Bandwidth
CS (OFF)
CD, CS (ON)
160
11
34
MHz typ
pF typ
pF typ
0.001
µA typ
µA max
POWER REQUIREMENTS
IDD
1
1.0
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
ADG786/ADG788
SPECIFICATIONS1 (V
DD
= 3 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
B Version
–40C
+25C
to +85C
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On-Resistance Match between
Channels (∆RON)
On-Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
± 0.01
± 0.1
± 0.01
± 0.1
0.005
CIN, Digital Input Capacitance
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IDS = 10 mA
± 0.5
nA typ
nA max
nA typ
nA max
VDD = 3.3 V
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 2
VS = VD = 1 V or 3 V;
Test Circuit 3
2.0
0.8
V min
V max
± 0.1
µA typ
µA max
pF typ
VIN = VINL or VINH
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF;
VS1A = 2 V, VS1B = 0 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 6
VS = 1 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
RL = 50 Ω, CL = 5 pF, Test Circuit 10
f = 1 MHz
f = 1 MHz
0 V to VDD
6
11
Unit
12
0.1
0.5
3
± 0.3
4
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to VDD, IDS = 10 mA
2
DYNAMIC CHARACTERISTICS
tON
28
55
tOFF
9
ADG786 tON(EN)
29
16
60
tOFF(EN)
9
16
Break-Before-Make Time Delay, tD
22
Charge Injection
±3
Off Isolation
–72
dB typ
Channel-to-Channel Crosstalk
–67
dB typ
–3 dB Bandwidth
CS (OFF)
CD, CS (ON)
160
11
34
MHz typ
pF typ
pF typ
0.001
µA typ
µA max
POWER REQUIREMENTS
IDD
1
1.0
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–3–
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
ADG786/ADG788–SPECIFICATIONS1
DUAL SUPPLY
(VDD = +2.5 V 10%, VSS = –2.5 V 10%, GND = 0 V, unless otherwise noted.)
B Version
–40C
+25C
to +85C
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
VSS to VDD
2.5
4.5
On-Resistance Match between
Channels (∆RON)
On-Resistance Flatness (RFLAT(ON))
5.0
0.1
0.4
0.5
1.2
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
± 0.01
± 0.1
± 0.01
± 0.1
0.005
CIN, Digital Input Capacitance
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
VS = VSS to VDD, IDS = 10 mA;
Test Circuit 1
VS = VSS to VDD, IDS = 10 mA
VS = VSS to VDD, IDS = 10 mA
VDD = +2.75 V, VSS = –2.75 V
VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V;
Test Circuit 2
VS = VD = +2.25 V/–1.25 V, Test Circuit 3
± 0.5
nA typ
nA max
nA typ
nA max
1.7
0.7
V min
V max
± 0.1
µA typ
µA max
pF typ
VIN = VINL or VINH
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF;
VS1A = 1.5 V, VS1B = 0 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, Test Circuit 6
VS = 0 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
RL = 50 Ω, CL = 5 pF, Test Circuit 10
f = 1 MHz
f = 1 MHz
± 0.3
4
2
DYNAMIC CHARACTERISTICS
tON
21
35
tOFF
10
ADG786 tON(EN)
21
tOFF(EN)
10
16
40
16
Break-Before-Make Time Delay, tD
13
Charge Injection
±5
Off Isolation
–72
dB typ
Channel-to-Channel Crosstalk
–67
dB typ
–3 dB Bandwidth
CS (OFF)
CD, CS (ON)
160
11
34
MHz typ
pF typ
pF typ
0.001
µA typ
µA max
µA typ
µA max
POWER REQUIREMENTS
IDD
1
1.0
ISS
0.001
1.0
VDD = +2.75 V
Digital Inputs = 0 V or 2.75 V
VSS = –2.75 V
Digital Inputs = 0 V or 2.75 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. 0
ADG786/ADG788
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –3.5 V
Analog Inputs2 . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Digital Inputs2 . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
20 Lead CSP, θJA Thermal Impedance . . . . . . . . . . . 32°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at A, EN, IN, S, or D will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG786/ADG788 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADG786BCP
ADG788BCP
–40°C to +85°C
–40°C to +85°C
Chip Scale Package (CSP)
Chip Scale Package (CSP)
CP-20
CP-20
6
7
8
9
10
VSS
GND
A2
A1
A0
EN 5
S1B 2
13 D1
VSS 3
12 S1B
GND 4
11 S1A
S2B 5
–5–
D4
IN4
S4A
14 VDD
ADG788
13 S3B
TOP VIEW
(Not to Scale)
12 D3
11 S3A
6
7
8
9
10
NC = NO CONNECT
EXPOSED PAD TIED TO SUBSTRATE, V SS
REV. 0
15 S4B
NC
TOP VIEW
(Not to Scale)
S3A 4
14 NC
PIN 1
IDENTIFIER
IN3
ADG786
D3 3
D1 1
IN2
S3B 2
20 19 18 17 16
15 D2
D2
PIN 1
IDENTIFIER
S2A
20 19 18 17 16
S2A 1
IN1
S1A
VDD
NC
NC
NC
S2B
PIN CONFIGURATIONS
ADG786/ADG788
Table II. ADG788 Truth Table
Table I. ADG786 Truth Table
A2
A1
A0
EN
ON Switch
Logic
Switch A
Switch B
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
None
D1-S1A, D2-S2A, D3-S3A
D1-S1B, D2-S2A, D3-S3A
D1-S1A, D2-S2B, D3-S3A
D1-S1B, D2-S2B, D3-S3A
D1-S1A, D2-S2A, D3-S3B
D1-S1B, D2-S2A, D3-S3B
D1-S1A, D2-S2B, D3-S3B
D1-S1B, D2-S2B, D3-S3B
0
1
OFF
ON
ON
OFF
TERMINOLOGY
VDD
VSS
IDD
ISS
GND
S
D
IN
VD (VS)
RON
∆RON
RFLAT(ON)
IS (OFF)
ID, IS (ON)
VINL
VINH
IINL(IINH)
CS (OFF)
CD, CS(ON)
CIN
tON
tOFF
tON(EN)
tOFF(EN)
tOPEN
Charge
Off Isolation
Crosstalk
On Response
Insertion Loss
Most Positive Power Supply Potential
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to
ground close to the device.
Positive Supply Current
Negative Supply Current
Ground (0 V) Reference
Source Terminal. May be an input or output
Drain Terminal. May be an input or output
Logic Control Input
Analog Voltage on Terminals D, S
Ohmic Resistance between D and S
On Resistance Match between Any Two Channels, i.e., RONmax – RONmin.
Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured
over the specified analog signal range.
Source Leakage Current with the Switch “OFF”
Channel Leakage Current with the Switch “ON”
Maximum Input Voltage for Logic “0”
Minimum Input Voltage for Logic “1”
Input Current of the Digital Input
“OFF” Switch Source Capacitance. Measured with reference to ground.
“ON” Switch Capacitance. Measured with reference to ground.
Digital Input Capacitance
Delay time measured between the 50% and 90% points of the digital inputs and the switch “ON” condition.
Delay time measured between the 50% and 90% points of the digital input and the switch “OFF” condition.
Delay time between the 50% and 90% points of the EN digital input and the switch “ON” condition.
Delay time between the 50% and 90% points of the EN digital input and the switch “OFF” condition.
“OFF” time measured between the 80% points of both switches when switching from one address state to another.
A measure of the glitch impulse transferred Injection from the digital input to the analog output during switching.
A measure of unwanted signal coupling through an “OFF” switch.
A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic
capacitance.
The Frequency Response of the “ON” Switch
The Loss Due to the ON Resistance of the Switch.
–6–
REV. 0
Typical Performance Characteristics– ADG786/ADG788
8
8
TA = 25C
VSS = 0V
VDD = 3.3V
5
VDD = 4.5V
4
3
2
7
7
6
6
ON RESISTANCE – VDD = 2.7V
6
ON RESISTANCE – ON RESISTANCE – 7
8
TA = 25C
5
VDD = +2.5V
VSS = –2.5V
4
3
2
VDD = 5V
VSS = 0V
5
4
+25C
+85C
3
2
VDD = 5.5V
–40C
1
0
1
0
1
2
3
4
0
–3
5
VD, VS, DRAIN OR SOURCE VOLTAGE – V
1
–2
–1
0
1
2
0
3
8
2
VDD = 5V
VSS = GND
TA = 25C
+85C
4
–40C
3
+25C
2
6
CURRENT – nA
ON RESISTANCE – ON RESISTANCE – 0.05
5
5
4
+25C
+85C
3
0
0
–3
1.0
1.5
2.0
2.5
3.0
0.5
VD, VS, DRAIN OR SOURCE VOLTAGE – V
IS (OFF)
–0.10
–2
–1
0
2
1
0.25
VDD = +2.5V
VSS = –2.5V
TA = 25C
0.10
CURRENT – nA
IS, ID (ON), VD = VS
0
–0.02
–0.04
2
VDD = +2.5V
VSS = –2.5V
VD = +2.25V/–1.25V
VS = –1.25V/+2.25V
0.20
0.15
0.04
0.02
1
3
5
4
TPC 6. Leakage Currents as a
Function of VD(VS)
0.15
VDD = 3V
VSS = GND
TA = 25C
0.06
0
VS, (VD = VDD –VS) – V
TPC 5. On Resistance as a Function
of VD(VS) for Different Temperatures,
Dual Supply
0.10
0.08
0.05
IS, ID (ON), VD = VS
0
–0.05
VDD = 5V
VSS = GND
VD = 4.5V/1.0V
VS = 1.0V/4.5V
0.10
IS, ID (ON)
0.05
0
–0.06
IS (OFF)
IS (OFF)
–0.10
0
0.5
1.0
1.5
2.0
2.5
VS, (VD = VDD –VS) – V
TPC 7. Leakage Currents as a
Function of VD(VS)
REV. 0
3.0
–0.15
–3
IS (OFF)
–0.05
–0.08
–0.10
–0.15
3
VD, VS, DRAIN OR SOURCE VOLTAGE – V
TPC 4. On Resistance as a Function
of VD(VS) for Different Temperatures,
Single Supply
CURRENT – nA
–0.05
1
CURRENT – nA
0
IS, ID (ON), VD = VS
0
2
–40C
1
5
0.10
VDD = +2.5V
VSS = –2.5V
7
6
4
3
TPC 3. On Resistance as a Function
of VD(VS) for Different Temperatures,
Single Supply
8
VDD = 3V
VSS = 0V
1
VD, VS, DRAIN OR SOURCE VOLTAGE – V
TPC 2. On Resistance as a Function
of VD(VS) for Dual Supply
TPC 1. On Resistance as a Function
of VD(VS) for Single Supply
7
0
VD, VS, DRAIN OR SOURCE VOLTAGE – V
–2
–1
0
1
2
VS, (VD = VDD –VS) – V
TPC 8. Leakage Currents as a
Function of VD(VS)
–7–
3
–0.10
5
20
35
50
65
TEMPERATURE – C
TPC 9. Leakage Currents as a
Function of Temperature
80
ADG786/ADG788
0.20
30
0.05
IS, ID (ON)
0
–0.05
IS (OFF)
5
20
35
50
65
–2
tON, VDD = 3V
0.10
–0.10
VSS = GND
35
TIME – ns
CURRENT – nA
0.15
0
40
VDD = 3V
VSS = GND
VD = 2.7V/1V
VS = 1V/2.7V
25
tON, VDD = 5V
20
15
10
tOFF, VDD = 3V
5
tOFF, VDD = 5V
0
80
–20
TPC 10. Leakage Currents as a
Function of Temperature
20
40
60
100k
0
1
VSS = 3V
VDD = GND
10
100
1000
FREQUENCY – kHz
10000
TPC 13. Input Current, IDD vs.
Switching Frequency
100M
–20
–30
–40
–50
–60
–70
–30
–40
–50
–60
–80
–70
–90
–80
–100
30k
1M
10M
FREQUENCY – HZ
VDD = 5V
TA = 25C
–10
ATTENUATION – dB
ATTENUATION – dB
VDD = +2.5V
VSS = –2.5V
1
–10
TPC 12. On Response vs. Frequency
–20
VDD = 5V
VSS = GND
10n
0.1
–8
–16
10k
80
VDD = 5V
TA = 25C
–10
1m
100n
–6
–14
0
TA = 25C
100
VDD = 5V
TA = 25C
–12
TPC 11. tON / tOFF Times vs.
Temperature
10m
CURRENT – A
0
–4
TEMPERATURE – C
TEMPERATURE – C
10
ON RESPONSE – dB
0.25
100k
1M
10M
FREQUENCY – Hz
100M
TPC 14. Off Isolation vs. Frequency
–90
30k
100k
1M
10M
FREQUENCY – Hz
100M
TPC 15. Crosstalk vs. Frequency
30
VDD = +2.5V
VSS = –2.5V
TA = 25C
QINJ – pC
20
VDD = 3V
VSS = GND
10
0
VDD = 5V
VSS = GND
–10
–3
–2
–1
0
1
2
VOLTAGE – V
3
4
5
TPC 16. Charge Injection vs. Source
Voltage
–8–
REV. 0
ADG786/ADG788
Test Circuits
IDS
V1
IS (OFF)
S
D
S
A
VS
D
S
NC
D
ID (ON)
A
VD
VD
VS
RON = V1/IDS
NC = NO CONNECT
Test Circuit 3. ID (ON)
Test Circuit 2. IS (OFF)
Test Circuit 1. On Resistance
VDD
0.1F
VDD
ADDRESS
DRIVE
S1B
VS1B
D1
S1A
VS1A
50%
50%
VOUT
VS1A
CL
35pF
RL
300
IN/EN
90%
90%
VOUT
VS1B
GND
tOFF
tON
VSS
0.1F
VSS
Test Circuit 4. Switching Times, tON, tOFF
VDD
VSS
0.1F
3V
VSS
VDD
A2
S1A
A1
ENABLE
DRIVE (VIN)
VS
tOFF(EN)
ADG786
EN
VIN
VO
D1
50
50%
0V
S1B
A0
50%
RL
300
GND
CL
35pF
0.9V0
0.9V0
VO
OUTPUT
0V
tON(EN)
Test Circuit 5. Enable Delay, tON (EN), tOFF (EN)
VDD
0.1F
3V
VDD
ADDRESS
VIN
VS
SA
ADDRESS*
0V
SB
50
ADG786/
ADG788
VS
D1
GND
VSS
RL
300
CL
35pF
VOUT
VOUT
80%
80%
0.1F
tOPEN
VSS
*A0, A1, A2 for ADG786, IN1-4 for ADG788
Test Circuit 6. Break-Before-Make Delay, tOPEN
REV. 0
–9–
ADG786/ADG788
VDD
VSS
VDD
VSS
3V
LOGIC
INPUT (VIN)
ADG786/
ADG788
0V
RS
D
S
CL
1nF
EN*
VS
VOUT
VOUT
QINJ = CL VOUT
VOUT
GND
VIN
* IN1–4 for ADG734
Test Circuit 7. Charge Injection
VDD
VDD
VSS
0.1F
0.1F
NETWORK
ANALYZER
VSS
VDD
S
VSS
S
NETWORK
ANALYZER
50
IN
VS
VS
D
D
VIN
RL
50
GND
VOUT
VIN
GND
OFF ISOLATION = 20 LOG
VOUT
INSERTION LOSS = 20 LOG
VS
VDD
NETWORK
ANALYZER
0.1F
VSS
VDD
SA
RL
50
D
SB
50
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Power Supply Sequencing
VSS
0.1F
RL
50
Test Circuit 10. Bandwidth
Test Circuit 8. OFF Isolation
VOUT
0.1F
VDD
50
50
IN
VSS
0.1F
R
50
IN
VS
GND
CHANNEL-TO-CHANNEL
VOUT
CROSSTALK = 20 LOG
VS
When using CMOS devices, care must be taken to ensure correct power supply sequencing. Incorrect sequencing can result
in the device being subjected to stresses beyond those maximum
ratings listed in the data sheet. Digital and analog inputs should
be applied to the device after supplies and ground. In dual supply applications, if digital and analog inputs may be applied
prior to VDD and VSS supplies, the addition of a Schottky diode
connected between VSS and GND will ensure that the device
powers on correctly. For single supply applications, VSS should
be tied to GND as close to the device as possible.
Test Circuit 9. Channel-to-Channel Crosstalk
–10–
REV. 0
ADG786/ADG788
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Chip Select Package
(CP-20)
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
0.024 (0.60)
0.017 (0.42)
16
0.009 (0.24)
15
0.157 (4.0)
BSC SQ
PIN 1
INDICATOR
TOP
VIEW
0.148 (3.75)
BSC SQ
0.028 (0.70) MAX
0.026 (0.65) NOM
12 MAX
0.035 (0.90) MAX
0.033 (0.85) NOM
SEATING
PLANE
0.020 (0.50)
BSC
0.008 (0.20)
REF
0.012 (0.30)
0.009 (0.23)
0.007 (0.18)
0.030 (0.75)
0.024 (0.60)
0.020 (0.50)
11
10
1
0.089 (2.25)
0.083 (2.10) SQ
0.077 (1.95)
6
0.080 (2.00)
REF
0.002 (0.05)
0.0004 (0.01)
0.0 (0.0)
–11–
20
BOTTOM
VIEW
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
REV. 0
0.010 (0.25)
MIN
5
–12–
PRINTED IN U.S.A.
C02381–1–7/01(0)