HD151TS407SS Mother Board Clock Generator for SiS 645/645DX/648/648FX/650/651/655/660 P4 Chipset ADE-205-703A (Z) Preliminary Rev.1 Nov. 2002 Description The HD151TS407 is a high-performance, low-skew, low-jitter, PC motherboard Clock generator. It is specifically designed for SiS 645/645DX/648/648FX/650/651/655/660 Pentium®4 chip set. Features • • • • • • • • • • • • • • • • • • 1 memory clock up to 200 MHz (DDR200/266/333/400 Support). 2 differential pairs of current mode control CPU clock. 6 PCI clocks and 2 PCI_F clocks @3.3 V, 33.3 MHz typ. 2 copies of AGP clock @3.3V, 66.6 MHz typ. 2 Zclock @3.3 V, up to 133.3 MHz. 1 copy of 48 MHz for USB @3.3 V 12 MHz / 48 MHz, 24 MHz / 48 MHz selectable clock @3.3 V 3 copies of 14.318 MHz reference clock @3.3 V Power save and clock stop function. Programmable clock output skew control function. I2CTM serial port programming. Spread Spectrum modulation (–0.5/–1.0/–1.5/–2.0% or ±0.25/±0.50/±0.75/±1.0%). Watchdog timer and reset output. VCO Direct Frequency Setting function. 48pin SSOP (300 mils). Supports 3 × DDR DIMM application with clock buffer HD74CDCV851 (SSOP48pin) Supports 2 × DDR DIMM Micro-ATX application with clock buffer HD74CDCV852 (SSOP28pin) Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD151TS407SSEL SSOP-48 pin SS EL (1,000 pcs / Reel) Note: Please consult the sales office for the above package availability. Note: I2C is a trademark of Philips Corporation. Pentium is registered trademark of Intel Corporation HD151TS407SS Key Specifications • • • • • • • Supply Voltages: VDD = 3.3 V ±5% Clock cycle to cycle jitter = |100| ps typ CPU clock group Skew = 150 ps max AGP clock group Skew = 175 ps max ZCLK clock group Skew = 175 ps max PCI clock group Skew = 500 ps max CPU(early) to PCI, AGP & ZCLK offset = 1 to 4 ns (typ. 2ns) Rev.1, Nov. 2002, page 2 of 35 HD151TS407SS Pin Arrangement VDDREF 1 48 VDDSD *FS0/REF0 2 47 SDCLK *FS1/REF1 3 46 GNDSD *FS2/REF2 4 45 CPU_STP# GNDREF 5 44 CPU1T X1 6 43 CPU1C X2 7 42 VDDCPU GNDZ 8 41 GNDCPU ZCLK0 9 40 CPU0T ZCLK1 10 39 CPU0C 38 IREF VDDZ 11 PCI_STP#/WDRESET# 12 37 GNDA VDDPCI 13 36 VDDA FS3*/PCI_F0 14 35 SCLK FS4*/PCI_F1 15 34 SDATA PCI0 16 33 PD#/VTT_PWRGD PCI1 17 32 GNDAGP GNDPCI 18 31 AGPCLK0 VDDPCI 19 30 AGPCLK1 PCI2 20 29 VDDAGP PCI3 21 28 VDD48 PCI4 22 27 48MHz/12MHz PCI5 23 26 24MHz/48MHz/MULTISEL* GNDPCI 24 25 GND48 (Top view) * Latch input / multi function pin. Note: FS0, 1, 2, 3, 4 = 120 kΩ Internal Pull-down. PCI_STP#, MULTISEL, PD#, CPU_STP# = 120 kΩ Internal Pull-up. 27 Pin = 48 MHz when power on. 26 Pin = 24 MHz when power on. Rev.1, Nov. 2002, page 3 of 35 HD151TS407SS Block Diagram 3.3 V VDD48 GND48 3.3 V VDDA GNDA 7× 3.3V VDD 7×GND IREF 3× REF 3.3 (14.318 MHz) XTAL 14.318 MHz 1/m1 OSC Synthesizer (CPU PLL) Clock Divider 1/n1 Clock Divider Mode Control Logic 1/m2 Synthesizer (48 MHz PLL) 1/n2 Note: Latched Input / Multi Function pin. Rev.1, Nov. 2002, page 4 of 35 1× SDCLK 3.3 2× AGP 3.3 SSC Modulator CPU_STP# PD# *MULTISEL *FS0, 1, 2, 3, 4 SDATA SCLK PCI_STP# 2× CPUCLK (HCSL) 2× ZCLK 3.3 6× PCICLK 3.3 2× PCICLK_F 3.3 Clock Divider 48/12 MHz 3.3 24/48 MHz 3.3 Watchdog Timer WDRESET# HD151TS407SS Table1 Clock Frequency Function Table & I2C Byte4 (bit2, 4, 5, 6 & 7) Bit2 Bit7 Bit6 Bit5 Bit4 FS4 FS3 FS2 FS1 FS0 CPU SDCLK ZCLK AGP PCICLK 0 0 0 0 0 100 100 133.33 66.67 33.33 0 400 200 400 0 0 0 0 1 100 133.33 133.33 66.67 33.33 1 400 266 400 0 0 0 1 0 100 166.67 125 62.5 33.33 2 400 333 500 0 0 0 1 1 100 200 133.33 66.67 33.33 3 400 400 400 0 0 1 0 0 133.33 100 133.33 66.67 33.33 4 533 200 400 0 0 1 0 1 133.33 133.33 133.33 66.67 33.33 5 533 266 400 0 0 1 1 0 133.33 166.67 133.33 66.67 33.33 6 533 333 667 0 0 1 1 1 133.33 200 133.33 66.67 33.33 7 533 400 400 0 1 0 0 0 133.33 166.67 133.33 50 33.33 8 533 333 667 0 1 0 0 1 200 133.33 133.33 66.67 33.33 9 800 266 400 0 1 0 1 0 222.22 166.67 133.33 66.67 33.33 10 0 1 0 1 1 200 200 133.33 66.67 33.33 11 800 400 400 0 1 1 0 0 166.67 166.67 133.33 50 33.33 12 667 333 667 0 1 1 0 1 166.67 133.33 133.33 66.67 33.33 13 667 266 667 0 1 1 1 0 166.67 166.67 133.33 66.67 33.33 14 667 333 667 0 1 1 1 1 166.67 222.22 133.33 66.67 33.33 15 667 444 667 1 0 0 0 0 100 100 66.67 66.67 33.33 16 400 200 400 1 0 0 0 1 100 133.33 66.67 66.67 33.33 17 400 266 400 1 0 0 1 0 100 166.67 62.5 62.5 33.33 18 400 333 500 1 0 0 1 1 100 200 66.67 66.67 33.33 19 400 400 400 1 0 1 0 0 133.33 100 66.67 66.67 33.33 20 533 200 400 1 0 1 0 1 133.33 133.33 66.67 66.67 33.33 21 533 266 400 1 0 1 1 0 133.33 166.67 66.67 66.67 33.33 22 533 333 667 1 0 1 1 1 133.33 200 66.67 66.67 33.33 23 533 400 400 1 1 0 0 0 140 175 116.67 63.6 33.3 24 700 1 1 0 0 1 145 193.3 116 64.4 32.2 25 580 1 1 0 1 0 150 150 120 66.67 33.33 26 600 1 1 0 1 1 155 155 124 62 32.6 27 620 1 1 1 0 0 160 160 128 64 32 28 1 1 1 0 1 133.33 133.33 100 66.67 33.33 29 533 266 400 1 1 1 1 0 133.33 166.67 95.24 66.67 33.33 30 533 333 667 1 1 1 1 1 133.33 200 100 66.67 33.33 31 533 400 400 FSB DDR VCO 667 640 Rev.1, Nov. 2002, page 5 of 35 HD151TS407SS Table2 Outputs State at Power Down INPUT OUTPUTS PD# CPUT CPUC SDCLK PCICLK ZCLK AGP 24/48 MHz 48 MHz 0 2 × IREF Hi-Z L L L L L L 1 Run Run Run Run Run Run Run Run Table3 CPUCLK Outputs Specification MULTISEL (pin26) Board Target Trace / Term Z Reference R, Iref = VDD / (3Rr) Output Current Ioh Voh @Z 1 60 Ω Rr = 475 1% I_REF = 2.32 mA 6 × Iref 0.85 V @60 Ω 1 50 Ω Rr = 475 1% I_REF = 2.32 mA 6 × Iref 0.71 V @50 Ω 0 60 Ω Rr = 475 1% I_REF = 2.32 mA 4 × Iref 0.56 V @60 Ω 0 50 Ω Rr = 475 1% I_REF = 2.32 mA 4 × Iref 0.47 V @50 Ω Rev.1, Nov. 2002, page 6 of 35 HD151TS407SS I2C Controlled Register Bit Map Byte0, 1, 2, 3 are reserved. All bits are default “1” at POWER ON. Byte4 CLK Frequency & SSC Control Register Bit Description Contents Default 7 Clock frequency control bit (See Table1) 0 6 Clock frequency control bit (See Table1) 0 5 Clock frequency control bit (See Table1) 0 4 Clock frequency control bit (See Table1) 0 3 Clock frequency select mode bit 0 = Freq. is selected by latched input FS0:4 2 1 = Freq. is selected by I C Byte4 bit2, 4–7 0 2 Clock frequency control bit (See Table1) 0 1 SSC enable bit 0 = SSC ON, 1 = SSC OFF 0 0 Outputs (all outputs) enable bit 0 = Running 1 = Tristate all outputs 0 Byte5 48MHz Clock & SSC Control Register Bit Description Contents 7 (Reserved) 0 6 (Reserved) 0 5 24MHz or 48MHz select When this bit = “0”, pin26 outputs 48MHz When this bit = “1”, pin26 outputs 24MHz 1 4 48MHz or 12MHz select When this bit = “0”, pin27 outputs 48MHz When this bit = “1”, pin27 outputs 12MHz 0 3 Spread Spectrum Control bit3 2 Spread Spectrum Control bit2 1 Spread Spectrum Control bit1 0 Spread Spectrum Control bit0 0000 = –0.5% (Default) 0001 = –0.75% 0010 = –1.0% 0011 = –1.5% 0100 = –2.0% Default 1000 = ±0.25% 1001 = ±0.375% 1010 = ±0.5% 1011 = ±0.75% 1100 = ±1.0% 0 0 0 0 Rev.1, Nov. 2002, page 7 of 35 HD151TS407SS I2C Controlled Register Bit Map (cont.) Byte6 Multi Input-pin Read Back Register Bit Description Contents Default 7 (Reserved bit) 0 6 (Reserved bit) 0 5 MULTISEL (pin26) read back Read only X 4 FS4 (pin15) read back Read only X 3 FS3 (pin14) read back Read only X 2 FS2 (pin4) read back Read only X 1 FS1 (pin3) read back Read only X 0 FS0 (pin2) read back Read only X Byte7 Byte Count Read Back Register Bit Description Contents Default 7 Byte count setting bit7 0 6 Byte count setting bit6 Writing to this register will configure byte count and how many bytes will be read back. Default is 1Ehex = 30 bytes. 0 5 Byte count setting bit5 4 Byte count setting bit4 1 3 Byte count setting bit3 1 2 Byte count setting bit2 1 1 Byte count setting bit1 1 0 Byte count setting bit0 0 Rev.1, Nov. 2002, page 8 of 35 0 HD151TS407SS I2C Controlled Register Bit Map (cont.) Byte8 Byte Vendor/Device ID Read Back Register Bit Description Contents Default 7 Vendor ID bit3 1 6 Vendor ID bit2 Hitachi = “1111” Read Only 5 Vendor ID bit1 1 4 Vendor ID bit0 1 3 Device ID bit3 2 Device ID bit2 0 1 Device ID bit1 0 0 Device ID bit0 1 Read Only 1 0 Note: Don’t write to this byte. Byte9 Clock Stop Control Register Bit Description Contents Default 7 (Reserved bit) 0 6 (Reserved bit) 0 5 (Reserved bit) 0 4 CPU1T/C state control at power down mode. 0 = CPU1T outputs 2 × Iref current and CPU1C is 0 tristate when PD# asserted. 1 = Both CPU1T and CPU1C are tristate when PD# asserted. 3 CPU0T/C state control at power down mode. 0 = CPU0T outputs 2 × Iref current and CPU0C is 0 tristate when PD# asserted. 1 = Both CPU0T and CPU0C are tristate when PD# asserted. 2 PCI_STP# (pin12) function enable 0 = Enable, 1 = Disable 0 1 CPU_STP# (pin45) function enable 0 = Enable, 1 = Disable 0 0 PD# (pin33) function enable 0 = Enable, 1 = Disable 0 Rev.1, Nov. 2002, page 9 of 35 HD151TS407SS I2C Controlled Register Bit Map (cont.) Byte10 CPU_STP# Control Register Bit Description Contents Default 7 AGPCLK1 (pin30) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 6 AGPCLK0 (pin31) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 5 CPU_STP# (pin45) function (AGPCLK1 control) 1 = AGPCLK1 will be stopped by CPU_STP# 0 = AGPCLK1 will not be stopped by CPU_STP# (AGPCLK1 = free running) 0 4 CPU_STP# (pin45) function (AGPCLK0 control) 1 = AGPCLK0 will be stopped by CPU_STP# 0 = AGPCLK0 will not be stopped by CPU_STP# (AGPCLK0 = free running) 0 3 CPU1T/C output enable 1 = Enable, 0 = Disable (Tristate) 1 2 CPU0T/C output enable 1 = Enable, 0 = Disable (Tristate) 1 1 CPU_STP# (pin45) function (CPU1T/C control) 1 = CPU1T/C will be stopped by CPU_STP# 0 = CPU1T/C will not be stopped by CPU_STP# (CPU1T/C = free running) 1 0 CPU_STP# (pin45) function (CPU0T/C control) 1 = CPU0T/C will be stopped by CPU_STP# 0 = CPU0T/C will not be stopped by CPU_STP# (CPU0T/C = free running) 1 Byte11 PCI_STP# Control Register Bit Description Contents Default 7 PCI_STP# (pin12) function (PCI_F1 Control) 1 = PCI_F[1:0] & PCI[5:0] will be stopped by PCI_STP# pin. 0 6 PCI_STP# (pin12) function (PCI_F0 Control) 0 = PCI_F[1:0] & PCI[5:0] will not be controlled by 0 PCI_STP# pin. (free running) 5 PCI_STP# (pin12) function (PCI5 Control) 1 4 PCI_STP# (pin12) function (PCI4 Control) 1 3 PCI_STP# (pin12) function (PCI3 Control) 1 2 PCI_STP# (pin12) function (PCI2 Control) 1 1 PCI_STP# (pin12) function (PCI1 Control) 1 0 PCI_STP# (pin12) function (PCI0 Control) 1 Rev.1, Nov. 2002, page 10 of 35 HD151TS407SS I2C Controlled Register Bit Map (cont.) Byte12 PCI Clock Outputs Control Register Bit Description Contents Default 7 PCI_F1 (pin15) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 6 PCI_F0 (pin14) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 5 PCI5 (pin23) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 4 PCI4 (pin22) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 3 PCI3 (pin21) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 2 PCI2 (pin20) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 1 PCI1 (pin17) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 0 PCI0 (pin16) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 Byte13 Peripheral clocks Control Register Bit Description Contents Default 7 REF2 (pin4) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 6 REF1 (pin3) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 5 REF0 (pin2) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 4 24_48MHz (pin26) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 3 48MHz (pin27) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 2 ZCLK1 (pin10) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 1 ZCLK0 (pin9) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 0 SDCLK (pin47) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 Rev.1, Nov. 2002, page 11 of 35 HD151TS407SS I2C Controlled Register Bit Map (cont.) Byte14 CPU Clock Skew Control Register Bit Description Contents Default 7 CPUT/C skew control bit3 CPUT/C skew control bit2 5 CPUT/C skew control bit1 4 CPUT/C skew control bit0 1000 = Delay 0 ps 1001 = Delay 250 ps 1010 = Delay 500 ps 1011 = Delay 750 ps 1100 = Delay 1000 ps 1101 = Delay 1250 ps 1110 = Delay 1500 ps 1111 = Delay 1750 ps 0111 = Ahead 250 ps 0110 = Ahead 500 ps 0101 = Ahead 750 ps 0100 = Ahead 1000 ps 0011 = Ahead 1250 ps 0010 = Ahead 1500 ps 0001 = Ahead 1750 ps 0000 = Ahead 2000 ps 1 6 3 CPUT/C skew control bit3 CPUT/C skew control bit2 1 CPUT/C skew control bit1 0 CPUT/C skew control bit0 0111 = Ahead 100 ps 0110 = Ahead 200 ps 0101 = Ahead 300 ps 0100 = Ahead 400 ps 0011 = Ahead 500 ps 0010 = Ahead 600 ps 0001 = Ahead 700 ps 0000 = Ahead 800 ps 1 2 1000 = Delay 0 ps 1001 = Delay 100 ps 1010 = Delay 200 ps 1011 = Delay 300 ps 1100 = Delay 400 ps 1101 = Delay 500 ps 1110 = Delay 600 ps 1111 = Delay 700 ps 0 0 0 0 0 0 Byte15 SDCLK & ZCLK Clock Skew Control Register Bit Description Contents 7 ZCLK skew control bit3 6 ZCLK skew control bit2 5 ZCLK skew control bit1 4 ZCLK skew control bit0 1000 = Delay 0 ps 1001 = Delay 250 ps 1010 = Delay 500 ps 1011 = Delay 750 ps 1100 = Delay 1000 ps 1101 = Delay 1250 ps 1110 = Delay 1500 ps 1111 = Delay 1750 ps 0111 = Ahead 250 ps 0110 = Ahead 500 ps 0101 = Ahead 750 ps 0100 = Ahead 1000 ps 0011 = Ahead 1250 ps 0010 = Ahead 1500 ps 0001 = Ahead 1750 ps 0000 = Ahead 2000 ps 3 SDCLK skew control bit3 2 SDCLK skew control bit2 1 SDCLK skew control bit1 0 SDCLK skew control bit0 1000 = Delay 0 ps 1001 = Delay 250 ps 1010 = Delay 500 ps 1011 = Delay 750 ps 1100 = Delay 1000 ps 1101 = Delay 1250 ps 1110 = Delay 1500 ps 1111 = Delay 1750 ps 0111 = Ahead 250 ps 0110 = Ahead 500 ps 0101 = Ahead 750 ps 0100 = Ahead 1000 ps 0011 = Ahead 1250 ps 0010 = Ahead 1500 ps 0001 = Ahead 1750 ps 0000 = Ahead 2000 ps Rev.1, Nov. 2002, page 12 of 35 Default 1 0 0 0 1 0 0 0 HD151TS407SS I2C Controlled Register Bit Map (cont.) Byte16 AGP Clock Skew Control Register Bit Description Contents 7 AGPCLK skew2 control bit3 6 AGPCLK skew2 control bit2 5 AGPCLK skew2 control bit1 4 AGPCLK skew2 control bit0 1000 = Delay 4000 ps 1001 = Delay 4500 ps 1010 = Delay 5000 ps 1011 = Delay 5500 ps 1100 = Delay 6000 ps 1101 = Delay 6500 ps 1110 = Delay 7000 ps 1111 = Delay 7500 ps 0111 = Delay 3500 ps 0110 = Delay 3000 ps 0101 = Delay 2500 ps 0100 = Delay 2000 ps 0011 = Delay 1500 ps 0010 = Delay 1000 ps 0001 = Delay 500 ps 0000 = Delay 0 ps 3 AGPCLK skew1 control bit3 Set Early Skew 1000 = Delay 0 ps 1001 = Delay 500 ps 1010 = Delay 1000 ps 1011 = Delay 1500 ps 1100 = Delay 2000 ps 1101 = Delay 2500 ps 1110 = Delay 3000 ps 1111 = Delay 3500 ps 0111 = Ahead 500 ps 0110 = Ahead 1000 ps 0101 = Ahead 1500 ps 0100 = Ahead 2000 ps 0011 = Ahead 2500 ps 0010 = Ahead 3000 ps 0001 = Ahead 3500 ps 0000 = Ahead 4000 ps 2 AGPCLK skew1 control bit2 1 AGPCLK skew1 control bit1 0 AGPCLK skew1 control bit0 Default 0 0 0 0 1 0 0 0 Byte17 PCI_F & PCI Clock Skew Control Register Bit Description Contents 7 PCI_F & PCI skew2 control bit3 6 PCI_F & PCI skew2 control bit2 5 PCI_F & PCI skew2 control bit1 4 PCI_F & PCI skew2 control bit0 1000 = Delay 4000 ps 1001 = Delay 4500 ps 1010 = Delay 5000 ps 1011 = Delay 5500 ps 1100 = Delay 6000 ps 1101 = Delay 6500 ps 1110 = Delay 7000 ps 1111 = Delay 7500 ps 0111 = Delay 3500 ps 0110 = Delay 3000 ps 0101 = Delay 2500 ps 0100 = Delay 2000 ps 0011 = Delay 1500 ps 0010 = Delay 1000 ps 0001 = Delay 500 ps 0000 = Delay 0 ps 3 PCI_F & PCI skew1 control bit3 Set Early Skew 1000 = Delay 0 ps 1001 = Delay 500 ps 1010 = Delay 1000 ps 1011 = Delay 1500 ps 1100 = Delay 2000 ps 1101 = Delay 2500 ps 1110 = Delay 3000 ps 1111 = Delay 3500 ps 0111 = Ahead 500 ps 0110 = Ahead 1000 ps 0101 = Ahead 1500 ps 0100 = Ahead 2000 ps 0011 = Ahead 2500 ps 0010 = Ahead 3000 ps 0001 = Ahead 3500 ps 0000 = Ahead 4000 ps 2 PCI_F & PCI skew1 control bit2 1 PCI_F & PCI skew1 control bit1 0 PCI_F & PCI skew1 control bit0 Default 0 0 0 0 1 0 0 0 Rev.1, Nov. 2002, page 13 of 35 HD151TS407SS I2C Controlled Register Bit Map (cont.) Byte18 AGP & PCI Skew Independent Control Register Bit Description Contents Default 7 AGPCLK1 skew2 control bit 0 = Disable, 1 = Enable 0 6 AGPCLK0 skew2 control bit 0 = Disable, 1 = Enable 0 5 PCI5 skew2 control bit 0 = Disable, 1 = Enable 0 4 PCI4 skew2 control bit 0 = Disable, 1 = Enable 0 3 PCI3 skew2 control bit 0 = Disable, 1 = Enable 0 2 PCI2 skew2 control bit 0 = Disable, 1 = Enable 0 1 PCI1 skew2 control bit 0 = Disable, 1 = Enable 0 0 PCI0 skew2 control bit 0 = Disable, 1 = Enable 0 Contents Default Byte19 Clock Slew Rate Control Register Bit Description 7 PCI slew rate control bit1 6 PCI slew rate control bit0 5 PCI_F slew rate control bit1 4 PCI_F slew rate control bit0 3 AGPCLK slew rate control bit1 2 AGPCLK slew rate control bit0 1 ZCLK slew rate control bit1 0 ZCLK slew rate control bit0 Rev.1, Nov. 2002, page 14 of 35 10 = Normal, 11 = –, 01 = + +, 00 = + 10 = Normal, 11 = –, 01 = + +, 00 = + 10 = Normal, 11 = –, 01 = + +, 00 = + 10 = Normal, 11 = –, 01 = + +, 00 = + 1 0 1 0 1 0 1 0 HD151TS407SS I2C Controlled Register Bit Map (cont.) Byte20 Clock Slew Rate Register Bit Description Contents Default 7 (Reserved) 0 6 (Reserved) 0 5 REF slew rate control bit1 4 REF slew rate control bit0 3 24_48M slew rate control bit1 2 24_48M slew rate control bit0 1 48MHz slew rate control bit1 0 48MHz slew rate control bit0 10 = Normal, 11 = –, 01 = + +, 00 = + 1 0 10 = Normal, 11 = –, 01 = + +, 00 = + 1 0 10 = Normal, 11 = –, 01 = + +, 00 = + 1 0 Byte21 Clock Invert Control Register Bit Description Contents Default 7 (Reserved) 6 24_48MHz invert control bit 0 = Normal, 1 = Inverted 0 5 48MHz invert control bit 0 = Normal, 1 = Inverted 0 4 PCI_F/PCI invert control bit 0 = Normal, 1 = Inverted 0 3 AGPCLK invert control bit 0 = Normal, 1 = Inverted 0 2 ZCLK invert control bit 0 = Normal, 1 = Inverted 0 1 SDCLK invert control bit 0 = Normal, 1 = Inverted 0 0 CPUT/C invert control bit 0 = Normal, 1 = Inverted 0 0 Byte22 Watchdog Timer Control Register Bit Description Contents Default 7 Watchdog enable 0 = Disable, 1 = Enable 0 6 Watchdog status 0 = Normal, 1 = Alarm 0 5 PLL divide control register select 0 = Byte 4 (Bit 2, 7, 6, 5, 4) 1 = Byte 22 (Bit 4, 3, 2, 1, 0) 0 4 Watchdog safe freq. setting Bit4 Correspond to Byte4/bit2 (FS4) Read Only 0 3 Watchdog safe freq. setting Bit3 Correspond to Byte4/bit7 (FS3) Read Only 0 2 Watchdog safe freq. setting Bit2 Correspond to Byte4/bit6 (FS2) Read Only 0 1 Watchdog safe freq. setting Bit1 Correspond to Byte4/bit5 (FS1) Read Only 0 0 Watchdog safe freq. setting Bit0 Correspond to Byte4/bit4 (FS0) Read Only 0 Rev.1, Nov. 2002, page 15 of 35 HD151TS407SS I2C Controlled Register Bit Map (cont.) Byt23 Watchdog Timer Control Register Bit Description 7 PLL unlock detector sensitivity control 00 = ±50% bit1 01 = ±40% PLL unlock detector sensitivity control 10 = ±30% 11 = ±20% bit0 6 Contents Default 0 0 5 Watchdog Timer count bit5 4 Watchdog Timer count bit4 3 Watchdog Timer count bit3 2 Watchdog Timer count bit2 1 Watchdog Timer count bit1 0 0 Watchdog Timer count bit0 0 The decimal representation of these 6 bits corresponds to how many 293 ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the setting. Default at power up is 16 × 293 ms = 4.69s 0 1 0 0 Byte24 Reserved Register Bit Description 7 (Reserved) 0 6 (Reserved) 0 5 (Reserved) 0 4 (Reserved) 0 3 (Reserved) 0 2 (Reserved) 0 1 (Reserved) 0 0 (Reserved) 0 Rev.1, Nov. 2002, page 16 of 35 Contents Default HD151TS407SS I2C Controlled Register Bit Map (cont.) Byte25 Clock Frequency Control Register Bit Description 7 6 (Reserved) AGP/PCI/ZCLK PLL select bit1 5 AGP/PCI/ZCLK PLL select bit0 0 = AGP/PCI/ZCLK = 66/33/66 MHz 1 = AGP/PCI/ZCLK = 66/33/132 MHz When Byte25 bit6 = 1. 0 4 CPU_PLL output frequency (VCO frequency) control bit VCO frequency control bit11 VCO frequency control bit10 VCO frequency control bit9 VCO frequency control bit8 0 = Determined by FS[4:0] or Byte4[7:2] 1 = Determined by Byte25[3:0] & Byte26[7:0] The 100 MHz digit of VCO frequency. 0010 = 2…. 0111 = 7 0 3 2 1 0 Contents Default 0 = CPU_PLL (Normal) 1 = USP_PLL (AGP/PCI/ZCLK frequency fixed) 0 0 0 1 0 0 Byte26 Clock Frequency Control Register Bit Description Contents Default 7 6 5 4 3 2 1 0 VCO frequency control bit7 VCO frequency control bit6 VCO frequency control bit5 VCO frequency control bit4 VCO frequency control bit3 VCO frequency control bit2 VCO frequency control bit1 VCO frequency control bit0 The 10 MHz digit of VCO frequency. 0000 = 0, 0001 = 1 …. 1001 = 9 0 0 0 0 0 0 0 0 The 1 MHz digit of VCO frequency. 0000 = 0, 0001 = 1 …. 1001 = 9 Notes: 1. Byte25[4:0] & 26 must be written together in every case. 2. How to set and confirm clock frequency. (1) How to set VCO frequency to 666 MHz. Write Byte25 0 Byte26 0 0 1 0 1 ON (2) 1 0 0 1 0 0 1 6 6 1 0 ⇒ 6 max 720 min 200 How to read actual frequency of VCO, CPU, SDCLK, ZCLK, AGP and PCI clock (See Byte28 – 33) Byte25[4] = 1 actual VCO freg. read back. Byte28 0 1 1 6 Note: 1 0 0 Byte29 1 1 6 0 0 1 1 6 0 1 0 0 0 8 Case of VCO = 666.8 MHz. Other clock frequency are able to read using the same way as shown at upper. Byte30,31 = Read back of CPU actual frequency. Byte32,33 = Read back of SDCLK actual frequency. Rev.1, Nov. 2002, page 17 of 35 HD151TS407SS I2C Controlled Register Bit Map (cont.) Byte27 Clock Output Divider Control Register Bit Description Contents Default 7 (Reserved) 6 Clock output divider enable bit 0 = Output divider (CPU & SDCLK) value will be determined by FS[4:0] or Byte4[7:2]. 1 = Output divider (CPU & SDCLK) value will be determined by Byte27[5:0]. 0 5 SDCLK output divider control bit2 SDCLK output divider control bit1 3 SDCLK output divider control bit0 000 = 1/2, 001 = 1/3, 010 = 1/4, 011 = 1/5, 100 = 1/6 101 = 1/7 110 = 1/8 111 = 1/9 0 4 2 CPU output divider control bit0 1 CPU output divider control bit0 0 CPU output divider control bit0 000 = 1/2, 001 = 1/3, 010 = 1/4, 011 = 1/5, 100 = 1/6 101 = 1/7 110 = 1/8 111 = 1/9 0 0 0 0 0 0 Byte28 Clock Frequency Read Back Register Bit Description Contents Default 7 VCO Frequency read back bit15 X 6 VCO Frequency read back bit14 5 VCO Frequency read back bit13 The 100 MHz digit of VCO frequency 0000 = 0, 0001 = 1 …. 1001 = 9 Enable at Byte25[4] = 1 Read only 4 VCO Frequency read back bit12 3 VCO Frequency read back bit11 2 VCO Frequency read back bit10 1 VCO Frequency read back bit9 0 VCO Frequency read back bit8 Rev.1, Nov. 2002, page 18 of 35 X X X The 10 MHz digit of VCO frequency. 0000 = 0, 0001 = 1 …. 1001 = 9 Enable at Byte25[4] = 1 Read only X X X X HD151TS407SS I2C Controlled Register Bit Map (cont.) Byte29 Clock Frequency Read Back Register Bit Description Contents Default 7 VCO Frequency read back bit7 X 6 VCO Frequency read back bit6 5 VCO Frequency read back bit5 The 1 MHz digit of VCO frequency. 0000 = 0, 0001 = 1 …. 1001 = 9 Enable at Byte25[4] = 1 Read only 4 VCO Frequency read back bit4 3 VCO Frequency read back bit3 2 VCO Frequency read back bit2 1 VCO Frequency read back bit1 0 VCO Frequency read back bit0 X X X The 0.1 MHz digit of VCO frequency. 0000 = 0, 0001 = 1 …. 1001 = 9 Enable at Byte25[4] = 1 Read only X X X X Byte30 Clock Frequency Read Back Register Bit Description Contents Default 7 CPU Frequency read back bit15 X 6 CPU Frequency read back bit14 5 CPU Frequency read back bit13 The 100 MHz digit of CPU frequency. 0000 = 0, 0001 = 1 …. 1001 = 9 Enable at Byte25[4] = 1 Read only 4 CPU Frequency read back bit12 3 CPU Frequency read back bit11 2 CPU Frequency read back bit10 1 CPU Frequency read back bit9 0 CPU Frequency read back bit8 X X X The 10 MHz digit of VCO frequency. 0000 = 0, 0001 = 1 …. 1001 = 9 Enable at Byte25[4] = 1 Read only X X X X Byte31 Clock Frequency Read Back Register Bit Description Contents Default 7 CPU Frequency read back bit7 X 6 CPU Frequency read back bit6 5 CPU Frequency read back bit5 The 1 MHz digit of CPU frequency. 0000 = 0, 0001 = 1 …. 1001 = 9 Enable at Byte25[4] = 1 Read only 4 CPU Frequency read back bit4 3 CPU Frequency read back bit3 2 CPU Frequency read back bit2 1 CPU Frequency read back bit1 0 CPU Frequency read back bit0 X X X The 0.1 MHz digit of CPU frequency. 0000 = 0, 0001 = 1 …. 1001 = 9 Enable at Byte25[4] = 1 Read only X X X X Rev.1, Nov. 2002, page 19 of 35 HD151TS407SS I2C Controlled Register Bit Map (cont.) Byte32 Clock Frequency Read Back Register Bit Description Contents Default 7 SDCLK Frequency read back bit7 X 6 SDCLK Frequency read back bit6 5 SDCLK Frequency read back bit5 The 100 MHz digit of SDCLK frequency. 0000 = 0, 0001 = 1 …. 1001 = 9 Enable at Byte25[4] = 1 Read only 4 SDCLK Frequency read back bit4 3 SDCLK Frequency read back bit3 2 SDCLK Frequency read back bit2 1 SDCLK Frequency read back bit1 0 SDCLK Frequency read back bit0 X X X The 10 MHz digit of SDCLK frequency. 0000 = 0, 0001 = 1 …. 1001 = 9 Enable at Byte25[4] = 1 Read only X X X X Byte33 Clock Frequency Read Back Register Bit Description Contents Default 7 SDCLK Frequency read back bit7 X 6 SDCLK Frequency read back bit6 5 SDCLK Frequency read back bit5 The 1 MHz digit of SDCLK frequency. 0000 = 0, 0001 = 1 …. 1001 = 9 Enable at Byte25[4] = 1 Read only 4 SDCLK Frequency read back bit4 3 SDCLK Frequency read back bit3 2 SDCLK Frequency read back bit2 1 SDCLK Frequency read back bit1 0 SDCLK Frequency read back bit0 Rev.1, Nov. 2002, page 20 of 35 X X X The 0.1 MHz digit of SDCLK frequency. 0000 = 0, 0001 = 1 …. 1001 = 9 Enable at Byte25[4] = 1 Read only X X X X HD151TS407SS CPU_STP# Assertion/De-assersion CPU_STP# CPUT High Hi–Z CPUC# CPU internal CPU_STP# Assertion/Deassertion Waveforms PCI_STP# Assertion/De-assersion PCI_STP# PCI_F Low PCI PCI_STP# Assertion/Deassertion Waveforms PD# Assertion/De-assersion < 1.8 ms PD# CPUT 2*Iref (Note) High Hi–Z (Note) High CPUC# CPUT CPUC# PD# Assertion/Deassertion Waveforms Byte9[4:3] CPU1T CPU1C 00 2*Iref Hi-Z 01 Hi-Z Hi-Z CPU2T 2*Iref CPU2C Hi-Z 10 2*Iref Hi-Z 11 Hi-Z Hi-Z 2*Iref Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Rev.1, Nov. 2002, page 21 of 35 HD151TS407SS Hitachi clock generator I2C Serial Interface Operation 1. Write mode 1.1 Controller (host) sends a start bit. 1.2 Controller (host) sends the write address D2 (h). 1.3 Hitachi clock generator will acknowledge (Hitachi clock gen. sends “Low”). 1.4 Controller (host) sends a begin byte M. 1.5 Hitachi clock generator will acknowledge (Hitachi clock gen. sends “Low”). 1.6 Controller (host) sends a byte count N. 1.7 Hitachi clock generator will acknowledge (Hitachi clock gen. sends “Low”). 1.8 Controller (host) sends data from byte M to byte M+N–1. 1.9 Hitachi clock generator will acknowledge each byte one at a time. 1.10 Controller (host) sends a stop bit. 1 bit 7 bits Start bit 1 bit 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits Slave R/W Ack Begin Byte = M Ack Byte Count = N Ack Byte M address D2(h) 1 bit 8 bits 1 bit 8 bits Ack Byte M+1 Ack Byte M+N–1 Rev.1, Nov. 2002, page 22 of 35 1 bit 1 bit Ack Stop bit HD151TS407SS Hitachi clock generator I2C Serial Interface Operation (cont.) 2. Read mode 2.1 Controller (host) sends a start bit. 2.2 Controller (host) sends the write address D2 (h). 2.3 Hitachi clock generator will acknowledge (Hitachi clock gen. sends “Low”). 2.4 Controller (host) sends a begin byte M. 2.5 Hitachi clock generator will acknowledge (Hitachi clock gen. sends “Low”). 2.6 Controller (host) sends a restart bit. 2.7 Controller (host) sends the read address D3 (h). 2.8 Hitachi clock generator will acknowledge (Hitachi clock gen. sends “Low”). 2.9 Hitachi clock generator will send the byte count N. 2.10 Controller (host) will acknowledge. 2.11 Hitachi clock generator will send data from byte M to byte M+N–1. 2.12 When Hitachi clock generator sends the last byte, controller (host) will not acknowledge. 2.13 Controller (host) sends a stop bit. 1 bit 7 bits Start bit 1 bit 8 bits 1 bit 1 bit 8 bits 1 bit 1 bit 7 bits 1 bit Slave R/W Ack Begin Byte = M Ack Restart bit Slave R/W address D2(h) address D3(h) 1 bit 8 bits Ack Begin Count = N Ack Byte M 1 bit 8 bits 1 bit Ack Byte M+1 Ack 8 bits 1 bit 1 bit Byte M+N–1 Not Ack Stop bit Notes: 1. Hitachi clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for the verification. 2. The data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode). 3. The input is operating at 3.3 V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I2C interface, the protocol is set to use only block-write from the controller. 6. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The data is loaded until a stop sequence is issued. 7. At power-on, all registers are set to a default condition, as shown. Rev.1, Nov. 2002, page 23 of 35 HD151TS407SS Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VDD –0.5 to 4.6 V Input voltage VI –0.5 to 5.5 V –0.5 to 4.6 V 1 Conditions SDATA, SCLK Output voltage * VO –0.5 to VDD +0.5 V Input clamp current IIK –50 mA VI < 0 Output clamp current IOK –50 mA VO < 0 Continuous output current IO ±50 mA VO = 0 to VDD 0.7 W –65 to +150 °C Maximum power dissipation at Ta = 55°C (in still air) Storage temperature Notes: Tstg Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Recommended Operating Conditions Item Symbol Min Typ Max Unit Conditions Supply voltage VDD 3.135 3.3 3.465 V –0.3 — VDD+0.3 V DC input signal voltage High level input voltage VIH 2.0 — VDD+0.3 V Low level input voltage VIL –0.3 — 0.8 V Operating temperature Ta 0 — 70 °C Rev.1, Nov. 2002, page 24 of 35 HD151TS407SS Pin Descriptions Pin name No. Type Description GND 5,8,18,24,25 Ground 32,41,46 GND pins VDD 1,11,13,19,28 Power 29,42,48 Power supplies pins. Nominal 3.3 V. VDDA 36 Power Power supply for PLL core. GNDA 37 Power Power supply for PLL core. CPUT [1:0] 44,40 OUTPUT “True” clocks of differential pair CPUCLK. These pins are HCSL outputs. CPUC [1:0] 43,39 OUTPUT “Complementary” clocks of differential pair CPUCLK. These pins are HCSL outputs. SDCLK 47 OUTPUT 3.3 V Memory clock outputs. CPU_STP# 45 INPUT CPUCLK STOP pin. This asynchronous input halts CPU, SDRAM and AGP clocks at logic “0” level when driven low, the stop selection can be programmed through I2C. 120 kΩ internal pulled-up. PCI_F0 14 OUTPUT Free running PCI clock 3.3 V output. INPUT Latch input multi function pin for frequency select. This pin is internal pull-down to GND. OUTPUT Free running PCI clock 3.3 V output. INPUT Latch input multi function pin for frequency select. This pin is internal pull-down to GND. (*FS3) PCI_F1 15 (*FS4) PCICLK [5:0] 16,17,20,21 OUTPUT 22,23 3.3 V PCI clock outputs. PCI_STP# 12 INPUT PCICLK stop pin. Stops PCICLKs at logic “0” level when input low, the stop selection can be programmed through I2C. 120 kΩ internal pulled-up. OUTPUT When Byte22 bit7 = 1, this pin becomes WDRESET# open drain output. OUTPUT Hyper Zip clock outputs. ZCLK [1:0] 9,10 Rev.1, Nov. 2002, page 25 of 35 HD151TS407SS Pin Descriptions (cont.) Pin name No. Type Description REF0 2 OUTPUT 14.318 MHz reference clock. INPUT Latch input multi function pin for frequency select. This pin is internal pull-down to GND. OUTPUT 14.318 MHz reference clock INPUT Latch input multi function pin for frequency select. This pin is internal pull-down to GND. OUTPUT 14.318 MHz reference clock. INPUT Latch input multi function pin for frequency select. This pin is internal pull-down to GND. OUTPUT SIO clock output. Default is 24 MHz. This pin’s output frequency is able to change for 48 MHz by I2C register. INPUT Latch input multi function pin for CPUCLK ’s output current setting. This pin is internal pull-up. (*FS0) REF1 3 (*FS1) REF2 4 (*FS2) 24MHz/48MHz 26 (*MULTISEL) 48MHz/12MHz 27 OUTPUT 3.3 V, 48 MHz USB clock output. 2 This pin’s output frequency is able to change for 12 MHz by I C register (Byte5 bit4). AGPCLK0 31 OUTPUT AGP clock output. AGPCLK1 30 OUTPUT AGP clock output. VTT_PWRGD/ PD# 33 INPUT Power down pin. All circuits will be powered down. (Output state of each outputs are shown in page6 Table2.) Asynchronous active low input pin used to power down the device into low power state. The internal clocks are disabled and VCO and the crystal are stopped. The latency of power down will not be greater than 3ms. X1 6 INPUT XTAL input. X2 7 OUTPUT XTAL output. SDATA 34 INPUT Data input for I2C logic. This pin is internal pull-up to VDD by 120 kΩ resistor. SCLK 35 INPUT Clock input for I2C logic. This pin is internal pull-up to VDD by 120 kΩ resistor. IREF 38 IN A fixed resistor provides a reference current for the differential HCSL clock outputs. Note: FS [4:0] & MULTISEL Input logic levels are latched an internal power-on reset. Use 10 kΩ resistor to program logic High to VDD or GND for logic low. Rev.1, Nov. 2002, page 26 of 35 HD151TS407SS DC Electrical Characteristics / Serial Input Port Ta = 0°C to 70°C, VDD = 3.3 V Typ *1 Max Unit 0.8 V VIH 2.0 V Input Current II –50 +50 µA VI = 0 V or 3.465 V, VDD = 3.465 V Input capacitance CI 10 pF SDATA & SCLK *2 Item Symbol Min Input Low Voltage VIL Input High Voltage Note: Test Conditions 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. 2. Target of design, not 100% tested in production. AC Electrical Characteristics / Serial Input port Item Symbol Min Typ Max Unit Test Conditions Notes SCLK Frequency FSCLK 100 kHz Start Hold Time tSTHD 4.0 µs SCLK Low Time tLOW 4.7 µs SCLK High Time tHIGH 4.0 µs Data Setup Time tDSU 250 ns Data Hold Time tDHD 300 ns Rise Time tr 1000 ns SDATA & SCLK 0.8 V to 2.0 V Fall Time tf 300 ns SDATA & SCLK 2.0 V to 0.8 V Stop Setup Time tSTSU 4.0 µs BUS Free Time between Stop & Start Condition tSPF 4.7 µs Normal Mode Note: Target of design, not 100% tested in production. Rev.1, Nov. 2002, page 27 of 35 HD151TS407SS DC Electrical Characteristics / SDCLK Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF Item Symbol Min Typ *1 Max Unit Test Conditions Output voltage VOH 3.1 V IOH = –1 mA, VDD = 3.3 V VOL 50 mV IOL = 1 mA, VDD = 3.3 V IOH –22 mA VOH = 2.0 V IOL 25 mA VOL = 0.8 V Output Current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. AC Electrical Characteristics / SDCLK Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF Item Symbol Min Typ Max Unit Test Conditions Notes Cycle to cycle jitter tCCS |100| ps Slew rate tSL 1.0 V/ns Clock Duty Cycle 45 50 55 % SDCLK to CPU Clock Skew –2.0 0 2.0 ns Output Impedance 30 Ω Notes: Target of design, not 100% tested in production. 1. Difference of cycle time between two adjoining cycles. Rev.1, Nov. 2002, page 28 of 35 133 MHz, Fig1 *1 0.4 V to 2.4 V HD151TS407SS DC Electrical Characteristics / CPUCT/C HCSL Clock Ta = 0°C to 70°C, VDD = 3.3 V Typ *1 Max Unit Test Conditions V I(nom) mA VDD = 3.3 V *2 3000 Ω VO = 1.2 V Item Symbol Min Output voltage VO Output Current IO Output resistance 1.2 Notes: Target of design, not 100% tested in production. 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions 2. I(nom) is output current(Ioh) shown in Page6 Table3. AC Electrical Characteristics / CPUT/C HCSL Clock Ta = 0°C to 70°C, VDD = 3.3 V, CL = 2 pF, Rref = 475 Ω, 6 × Iref Item Symbol Min Typ Max Unit Test Conditions Notes Cycle to cycle jitter tCCS |100| ps CPU Group Skew (CPU clock out to CPU clock out) tskS 150 ps Rise time tr 175 700 ps VO = 0.14 V to 0.56 V Fall time tf 175 700 ps VO = 0.14 V to 0.56 V Clock Duty Cycle 47 50 53 % CPU (early) to AGP Skew 1.0 2.0 4.0 ns CPU (early) to PCI Skew 1.0 2.0 4.0 ns CPU (early) to ZCLK Skew 1.0 2.0 4.0 ns 0.45 × Voh 0.55 × Voh V Cross point voltage Vcross 133 MHz *1 100/133 MHz Notes: Target of design, not 100% tested in production. 1. Difference of cycle time between two adjoining cycles. Rev.1, Nov. 2002, page 29 of 35 HD151TS407SS DC Electrical Characteristics / PCI Clock Ta = 0°C to 70°C, VDD = 3.3 V, CL = 30 pF Item Symbol Min Typ *1 Max Unit Test Conditions Output voltage VOH 3.1 V IOH = –1 mA, VDD = 3.3 V VOL 50 mV IOL = 1 mA, VDD = 3.3 V IOH –22 mA VOH = 2.0 V IOL 25 mA VOL = 0.8 V Output current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. AC Electrical Characteristics / PCI Clock Ta = 0°C to 70°C, VDD = 3.3 V, CL = 30 pF Item Symbol Min Typ Max Unit Test Conditions Notes Cycle to cycle jitter tCCS |100| ps 33.3 MHz, Fig1 PCI Group Skew tskS (PCI clock out to PCI clock out) 500 ps Rising edge @1.5 V to 1.5 V Fig.2 Slew rate 1.0 V/ns Clock Duty Cycle 45 50 55 % Output Impedance 30 Ω tSL Notes: Target of design, not 100% tested in production. 1. Difference of cycle time between two adjoining cycles. Rev.1, Nov. 2002, page 30 of 35 *1 0.4 V to 2.4 V HD151TS407SS DC Electrical Characteristics / AGP Clock & ZCLK Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF Item Symbol Min Typ *1 Max Unit Test Conditions Output voltage VOH 3.1 V IOH = –1 mA, VDD = 3.3 V VOL 50 mV IOL = 1 mA, VDD = 3.3 V IOH –22 mA VOH = 2.0 V IOL 25 mA VOL = 0.8 V Output current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. AC Electrical Characteristics / AGP Clock & ZCLK Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF Item Symbol Min Typ Max Unit Test Conditions Notes Cycle to cycle jitter tCCS |200| ps 66.6 MHz, Fig1 AGP Group Skew & ZCLK Group Skew tskS 175 ps Rising edge @1.5 V to 1.5 V Fig.2 Slew rate tSL 1.0 V/ns Clock Duty Cycle 45 50 55 % Output Impedance 30 Ω *1 0.4 V to 2.4 V Notes: Target of design, not 100% tested in production. 1. Difference of cycle time between two adjoining cycles. Rev.1, Nov. 2002, page 31 of 35 HD151TS407SS DC Electrical Characteristics / 48/12 MHz, 24/48 MHz & REF Clock Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF Item Symbol Min Typ *1 Max Unit Test Conditions Output voltage VOH 3.1 V IOH = –1 mA, VDD = 3.3 V VOL 50 mV IOL = 1 mA, VDD = 3.3 V IOH –22 mA VOH = 2.0 V IOL 16 mA VOL = 0.8 V Output Current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. AC Electrical Characteristics / 48/12 MHz, 24/48 MHz & REF Clock Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF Item Symbol Min Typ Max Unit Test Conditions Notes Cycle to cycle jitter tCCS |200| ps Slew rate tSL 0.5 V/ns Clock Duty Cycle 45 50 55 % Output Impedance 40 Ω Notes: Target of design, not 100% tested in production. 1. Difference of cycle time between two adjoining cycles. Rev.1, Nov. 2002, page 32 of 35 48 MHz, Fig1 *1 0.4 V to 2.4 V HD151TS407SS Clock Out tcycle n+1 tcycle n t CCS = (tcycle n) - (tcycle n+1) Figure1 Cycle to Cycle Jitter (3.3 V Single Ended Clock Output) Clock Outx 1.5 V Clock Outy 1.5 V tskS Figure2 Output Clock Skew (3.3 V Single Ended Clock Output) RS = 33.2 Ω ZLT = ZLC = 50 Ω CPUCLKT LT TS407 RS = 33.2 Ω CPUCLKC RI(ref) = 475 Ω LC RP = 49.9 Ω RP = 49.9 Ω CL = 2 pF CL = 2 pF Figure3 Load Circuit for CPUCLKT/C Rev.1, Nov. 2002, page 33 of 35 HD151TS407SS Package Dimensions Unit: mm 15.85 ± 0.3 25 1 24 0.635 0.25 ± 0.1 Rev.1, Nov. 2002, page 34 of 35 0.15 0.13 M 0.10 Min 0.78 Max 0.15 ± 0.05 2.65 Max 7.50 ± 0.3 48 10.40 ± 0.4 1.45 0˚ - 10˚ 0.60 ± 0.2 HD151TS407SS Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Sales offices Hitachi, Ltd. Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109 URL http://www.hitachisemiconductor.com/ For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-6538-6533/6538-8577 Fax : <65>-6538-6933/6538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Europe GmbH Electronic Components Group Dornacher Str 3 D-85622 Feldkirchen Postfach 201, D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://semiconductor.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan. Colophon 7.0 Rev.1, Nov. 2002, page 35 of 35