HD151TS404SS Mother Board Clock Generator for SiS746 AMD Athlon/Duron Chipset ADE-205-711A (Z) Rev.1 Nov. 2002 Description The HD151TS404 is a high-performance, low-skew, low-jitter, PC motherboard Clock generator. It is specifically designed for SiS746 chip set. Features • • • • • • • • • • • • • • • • 1 Differential pair of open drain CPU clock. 1 open drain CPU clock for chipset. 6 PCI clocks and 2 PCI_F clocks @3.3 V, 33.3 MHz typ. 2 copies of AGP clock @3.3V, 66.6 MHz typ. 2 Zclock @3.3 V, up to 133.3 MHz. 1 copy of 48 MHz for USB @3.3 V 24 MHz / 48 MHz selectable clock @3.3 V 2 copies of 14.318 MHz reference clock @3.3 V Power save and clock stop function. Programmable clock output skew control function. I2CTM serial port programming. Spread Spectrum modulation (–0.5% or ±0.25%). 48pin SSOP (300 mils). Supports 3 × DDR DIMM application with clock buffer HD74CDCV851 (SSOP48pin) Supports 2 × DDR DIMM Micro-ATX application with clock buffer HD74CDCV852 (SSOP28pin) Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD151TS404SSEL SSOP-48 pin SS EL (1,000 pcs / Reel) Note: Please consult the sales office for the above package availability. Note: I2C is a trademark of Philips Corporation. Pentium is registered trademark of Intel Corporation HD151TS404SS Key Specifications • • • • • • Supply Voltages: VDD = 3.3 V ±5% Clock cycle to cycle jitter = |125| ps Typ CPU clock group Skew = 150 ps max AGP clock group Skew = 175 ps max PCI clock group Skew = 500 ps max CPU(early) to PCI, AGP & ZCLK offset = 1 to 4 ns (typ. 2ns) Rev.1, Nov. 2002, page 2 of 27 HD151TS404SS Pin Arrangement 48 VDDAPIC VDDREF 1 *FS0/REF0 2 47 IOAPIC1 *FS1/REF1 3 46 IOAPIC0 45 GNDAPIC NC 4 GNDREF 5 44 CPU_STP# X1 6 43 CPU1T(OD) X2 7 42 VDDCPU GNDZ 8 41 GNDCPU ZCLK0 9 40 CPU0T(OD) ZCLK1 10 39 CPU0C(OD) 38 VDDCPU VDDZ 11 PCI_STP# 12 37 GNDA VDDPCI 13 36 VDDA FS2*/PCI_F0 14 35 SCLK FS3*/PCI_F1 15 34 SDATA PCI0 16 33 PD# PCI1 17 32 GNDAGP GNDPCI 18 31 AGPCLK0 VDDPCI 19 30 AGPCLK1 PCI2 20 29 VDDAGP PCI3 21 28 VDD48 PCI4 22 27 48MHz PCI5 23 26 24_48MHz GNDPCI 24 25 GND48 (Top view) * Latch input / multi function pin. Note: FS0, 1, 2, 3 = 120 kΩ Internal Pull-down. PCI_STP#, PD#, CPU_STP# = 120 kΩ Internal Pull-up. Rev.1, Nov. 2002, page 3 of 27 HD151TS404SS Block Diagram 2.5V 3.3V VDD48 GND48 3.3V VDDA GNDA 2.5V 5× 3.3V VDD 7×GND 2×VDDCPU VDDAPIC 2× REF 3.3 (14.318 MHz) XTAL 1/m1 14.318 MHz Synthesizer 2× IOAPIC 2.5 (14.318 MHz) (CPU PLL) OSC CPUOT/C (OD) 1/n1 SSC Modulator CPU1T (OD) Clock Divider CPU_STP# PD# *FS0, 1, 2, 3 SDATA SCLK PCI_STP# 2× AGP 3.3 2× ZCLK 3.3 Mode Control Logic 1/m2 Synthesizer (48 MHz PLL) 1/n2 Note: Latched Input / Multi Function pin. Rev.1, Nov. 2002, page 4 of 27 6× PCICLK 3.3 2× PCICLK_F 3.3 48 MHz 3.3 24/48 MHz 3.3 HD151TS404SS Table1 Clock Frequency Function Table & I2C Byte4 (bit2, 4, 5, 6 & 7) Bit2 Bit7 Bit6 Bit5 Bit4 FS3 FS2 FS1 FS0 CPU ZCLK AGP PCICLK 33.33 0 0 0 0 0 0 133.33 66.67 66.67 1 0 0 0 0 1 133.33 66.67 50 33.33 2 0 0 0 1 0 133.33 100 66.67 33.33 3 0 0 0 1 1 133.33 100 50 33.33 4 0 0 1 0 0 133.33 133.33 66.67 33.33 5 0 0 1 0 1 133.33 133.33 50 33.33 6 0 0 1 1 0 133.33 166.67 66.67 33.33 7 0 0 1 1 1 133.33 166.67 55.58 33.33 8 0 1 0 0 0 100 66.67 66.67 33.33 9 0 1 0 0 1 100 66.67 50 33.33 10 0 1 0 1 0 100 100 66.67 33.33 11 0 1 0 1 1 100 100 50 33.33 12 0 1 1 0 0 100 133.33 66.67 33.33 13 0 1 1 0 1 100 133.33 50 33.33 14 0 1 1 1 0 111.1 166.67 66.67 33.33 15 0 1 1 1 1 111.1 166.67 55.56 33.33 16 1 0 0 0 0 115.5 115.5 64.17 32.08 17 1 0 0 0 1 120 100 66.67 33.33 18 1 0 0 1 0 133.33 83.33 66.67 33.33 19 1 0 0 1 1 133.33 111.1 74.1 33.33 20 1 0 1 0 0 133.33 133.33 83.33 33.33 21 1 0 1 0 1 144.4 115.5 64.17 32.08 22 1 0 1 1 0 150 100 66.67 33.33 23 1 0 1 1 1 166.67 111.1 66.67 33.33 24 1 1 0 0 0 111.1 133.33 66.67 33.33 25 1 1 0 0 1 138.4 138.4 69.2 34.6 26 1 1 0 1 0 144.4 144.4 64.17 32.08 27 1 1 0 1 1 150 150 64.28 32.14 28 1 1 1 0 0 155.1 124.1 68.9 34.5 29 1 1 1 0 1 166.67 133.33 66.67 33.33 30 1 1 1 1 0 179.8 134.8 67.4 33.7 31 1 1 1 1 1 200 133.33 66.67 33.33 Rev.1, Nov. 2002, page 5 of 27 HD151TS404SS Table2 Outputs State at Power Down INPUT OUTPUTS PD# CPUT CPUC 1 1 PCICLK ZCLK AGP 24/48 MHz 48 MHz 0 H* H* L L L L L 1 Run Run Run Run Run Run Run Note: 1. CPUCLK will be floating. Pull up by external resistor. Rev.1, Nov. 2002, page 6 of 27 HD151TS404SS I2C Controlled Register Bit Map Byte0, 1, 2, 3 are reserved. All bits are default “1” at POWER ON. Byte4 CLK Frequency & SSC Control Register Bit Description Contents Default 7 CLK Freq. Control bit (See Table1) 0 6 CLK Freq. Control bit (See Table1) 0 5 CLK Freq. Control bit (See Table1) 0 4 CLK Freq. Control bit (See Table1) 0 3 Freq. Select Mode bit 0 = Freq. is selected by latched input FS0:4 2 1 = Freq. is selected by I C Byte0 bit2, 4–7 0 2 CLK Freq. Control bit (See Table1) 0 1 SSC Enable bit “1” = SSC OFF, “0” = SSC ON 0 0 Outputs (All outputs) enable bit 0 = Running 1 = Tristate all outputs 0 Contents Default Byte5 Multi Input-pin Read Back Register Bit Description 7 (Reserved bit) 0 6 (Reserved bit) 0 5 (Reserved bit) 0 4 (Reserved bit) 0 3 FS3 (pin14) Read back X 2 FS2 (pin4) Read back X 1 FS1 (pin3) Read back X 0 FS0 (pin2) Read back X Rev.1, Nov. 2002, page 7 of 27 HD151TS404SS I2C Controlled Register Bit Map (cont.) Byte6 PCI_STP# & CPU_STP# Control Register Bit Description 7 (Reserved) 0 6 (Reserved) 0 5 PCI_STP# (pin12) Function (PCI_F0 Control) When this bit is “1”, PCI_F0 will be stopped by PCI_STP# pin. When this bit is “0”, PCI_F0 will not be controlled by PCI_STP# pin. (PCI_F0 = free running) 0 4 PCI_STP# (pin12) Function (PCI_F1 Control) When this bit is “1”, PCI_F1 will be stopped by PCI_STP# pin. When this bit is “0”, PCI_F1 will not be controlled by PCI_STP# pin. (PCI_F1 = free running) 0 3 CPU_STP# (pin45) Function When this bit is “1”, CPU0T/0C will be stopped by 1 CPU_STP# pin. CPU0T/0C will be “floating” at CPU_STP# = Low. Default is “1” Clock Stop Mode. When this bit is “0”, CPU0T/0C will not be controlled by CPU_STP# pin. (CPU0T/0C = free running) (CPU0T/0C Control) Contents Default 2 CPU_STP# (pin45) Function (CPU1T Control) When this bit is “1”, CPU1T will be stopped by CPU_STP# pin. CPU1T will be “floating” at CPU_STP# = Low. When this bit is “0”, CPU1T will not be controlled by CPU_STP# pin. (CPU1T = free running) Default is “0” Clock Free Running Mode. 0 1 CPU0T/0C output Enable 1 = Enable, 0 = Disable (Tristate) 1 0 CPU1T output Enable 1 = Enable, 0 = Disable (Tristate) 1 Rev.1, Nov. 2002, page 8 of 27 HD151TS404SS I2C Controlled Register Bit Map (cont.) Byte7 PCI Clock Outputs Control Register Bit Description Contents Default 7 PCI_F1 (pin15) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 6 PCI_F0 (pin14) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 5 PCI5 (pin23) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 4 PCI4 (pin22) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 3 PCI3 (pin21) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 2 PCI2 (pin20) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 1 PCI1 (pin17) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 0 PCI0 (pin16) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 Byte8 Byte Vendor/Device ID Read Back Register Bit Description Contents Default 7 Vendor ID bit3 Hitachi = “1111” 1 6 Vendor ID bit2 1 5 Vendor ID bit1 1 4 Vendor ID bit0 1 3 Device ID bit3 0 2 Device ID bit2 0 1 Device ID bit1 0 0 Device ID bit0 1 Note: Don’t write to this byte. Rev.1, Nov. 2002, page 9 of 27 HD151TS404SS I2C Controlled Register Bit Map (cont.) Byte9 Peripheral clocks Control Register Bit Description Contents Default 7 PD# (pin33) pin function enable 1 = Enable, 0 = PD# Disable 1 6 (Reserved) 5 48 MHz (pin27) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 4 24_48 MHz (pin26) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 3 24 MHz or 48 MHz Select When this bit = “0”, pin26 outputs 24 MHz When this bit = “1”, pin26 outputs 48 MHz 0 2 (Reserved) 0 1 (Reserved) 0 0 Spread spectrum control register 0 0: ±0.25% central spread. The modulation rate is 33 kHz. 1: 0 to –0.5% down spread. The modulation rate is 33 kHz. 0 Contents Default Byte10 Clock Output Enable Register Bit Description 7 Reserved 6 IOAPIC0 & 1 (pin46,47) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 5 REF1 (pin3) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 4 REF0 (pin2) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 3 ZCLK1 (pin10) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 2 ZCLK0 (pin9) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 1 AGPCLK1 (pin30) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 0 AGPCLK0 (pin31) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 Rev.1, Nov. 2002, page 10 of 27 0 HD151TS404SS I2C Controlled Register Bit Map (cont.) Byte11 Reserved Register Bit Description Contents Default 7 (Reserved) 0 6 (Reserved) 0 5 (Reserved) 1 4 (Reserved) 1 3 (Reserved) 1 2 (Reserved) 1 1 (Reserved) 1 0 (Reserved) 1 Byte12 Reserved Register Bit Description Contents Default 7 (Reserved) 0 6 (Reserved) 0 5 (Reserved) 0 4 (Reserved) 0 3 (Reserved) 0 2 (Reserved) 0 1 (Reserved) 0 0 (Reserved) 0 Byte13 PLL N Divide Ratio Control Register Bit Description Contents Default 7 (Reserved) 0 6 (Reserved) 0 5 (Reserved) 0 4 (Reserved) 0 3 (Reserved) 0 2 PLL divide control register 0: Byte0 (bit2,4,5,6,7) 1: Byte9,10,11 (PLL N & M divider) 0 1 PLL N Divider Control bit9 PLL N Divider Control bit9 0 0 PLL N Divider Control bit8 PLL N Divider Control bit8 0 Rev.1, Nov. 2002, page 11 of 27 HD151TS404SS I2C Controlled Register Bit Map (cont.) Byte14 PLL N Divide Ratio Control Register Bit Description Contents Default 7 PLL N Divider Control bit7 PLL N Divider Control bit7 0 6 PLL N Divider Control bit6 PLL N Divider Control bit6 0 5 PLL N Divider Control bit5 PLL N Divider Control bit5 0 4 PLL N Divider Control bit4 PLL N Divider Control bit4 0 3 PLL N Divider Control bit3 PLL N Divider Control bit3 0 2 PLL N Divider Control bit2 PLL N Divider Control bit2 0 1 PLL N Divider Control bit1 PLL N Divider Control bit1 0 0 PLL N Divider Control bit0 PLL N Divider Control bit0 0 Byte15 PLL M Divide Ratio Control Register Bit Description Contents Default 7 (Reserved) 6 PLL M Divider Control bit6 PLL M Divider Control bit6 0 5 PLL M Divider Control bit5 PLL M Divider Control bit5 0 4 PLL M Divider Control bit4 PLL M Divider Control bit4 0 3 PLL M Divider Control bit3 PLL M Divider Control bit3 0 2 PLL M Divider Control bit2 PLL M Divider Control bit2 0 1 PLL M Divider Control bit1 PLL M Divider Control bit1 0 0 PLL M Divider Control bit0 PLL M Divider Control bit0 0 Contents Default 0 Byte16 Reserved Register Bit Description 7 (Reserved) 0 6 (Reserved) 0 5 (Reserved) 0 4 (Reserved) 0 3 (Reserved) 0 2 (Reserved) 0 1 (Reserved) 0 0 (Reserved) 0 Rev.1, Nov. 2002, page 12 of 27 HD151TS404SS I2C Controlled Register Bit Map (cont.) Byte17 Reserved Register Bit Description Contents Default 7 (Reserved) 0 6 (Reserved) 0 5 (Reserved) 0 4 (Reserved) 0 3 (Reserved) 0 2 (Reserved) 0 1 (Reserved) 0 0 (Reserved) 0 Byte18 CPU Clock Skew Control Register Bit Description Contents Default 7 CPUT/C0 Skew Control bit3 0 6 CPUT/C0 Skew Control bit2 5 CPUT/C0 Skew Control bit1 4 CPUT/C0 Skew Control bit0 0000: Ahead 2000 ps 0001: Ahead 1500 ps 0010: Ahead 1000 ps 0011: Ahead 500 ps 0100: Ahead 0 ps (Default) 0101: Delay 500 ps 0110: Delay 1000 ps 0111: Delay 1500 ps 1000: Delay 2000 ps 3 CPU1T Skew Control bit3 2 CPU1T Skew Control bit2 1 CPU1T Skew Control bit1 0 CPU1T Skew Control bit0 0000: Ahead 2000 ps 0001: Ahead 1500 ps 0010: Ahead 1000 ps 0011: Ahead 500 ps 0100: Ahead 0 ps (Default) 0101: Delay 500 ps 0110: Delay 1000 ps 0111: Delay 1500 ps 1000: Delay 2000 ps 1 0 0 0 1 0 0 Rev.1, Nov. 2002, page 13 of 27 HD151TS404SS I2C Controlled Register Bit Map (cont.) Byte19 SDCLK (Mem. Clock) skew Control Register Bit Description Contents Default 7 (Reserved) 0 6 (Reserved) 1 5 (Reserved) 0 4 (Reserved) 0 3 (Reserved) 0 2 (Reserved) 0 1 (Reserved) 0 0 (Reserved) 0 Byte20 Reserved Register Bit Description 7 (Reserved) 0 6 (Reserved) 0 5 (Reserved) 0 4 (Reserved) 0 3 (Reserved) 0 2 (Reserved) 0 1 (Reserved) 0 0 (Reserved) 0 Rev.1, Nov. 2002, page 14 of 27 Contents Default HD151TS404SS I2C Controlled Register Bit Map (cont.) Byte21 Reserved Register Bit Description Contents Default 7 (Reserved) 0 6 (Reserved) 0 5 (Reserved) 0 4 (Reserved) 0 3 (Reserved) 0 2 (Reserved) 0 1 (Reserved) 0 0 (Reserved) 0 Byte22 Reserved Register Bit Description Contents Default 7 (Reserved bit) 0 6 (Reserved bit) 0 5 (Reserved bit) 0 4 (Reserved bit) 0 3 (Reserved bit) 0 2 (Reserved bit) 0 1 (Reserved bit) 0 0 (Reserved bit) 0 Rev.1, Nov. 2002, page 15 of 27 HD151TS404SS Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VDD –0.5 to 4.6 V Input voltage VI –0.5 to 5.5 V –0.5 to 4.6 V 1 Conditions SCLK, SDATA Output voltage * VO –0.5 to VDD +0.5 V Input clamp current IIK –50 mA VI < 0 Output clamp current IOK –50 mA VO < 0 Continuous output current IO ±50 mA VO = 0 to VDD 0.7 W –65 to +150 °C Maximum power dissipation at Ta = 55°C (in still air) Storage temperature Notes: Tstg Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Recommended Operating Conditions Item Symbol Min Typ Max Unit Conditions Supply voltage VDD3.3 3.135 3.3 3.465 V REF, ZCLK,PCI, 24/48MHz, AGP VDD2.5 2.375 2.5 2.625 V IOAPIC, CPU –0.3 — VDD+0.3 V High level input voltage VIH 2.0 — VDD+0.3 V Low level input voltage VIL –0.3 — 0.8 V Operating temperature Ta 0 — 70 °C DC input signal voltage Rev.1, Nov. 2002, page 16 of 27 HD151TS404SS Pin Descriptions Pin name No. Type Description GND 5,8,18,24,25 Ground 32,41 GND pins VDD3.3 1,11,13,19,28 Power 29 Power supplies pins. Nominal 3.3 V. VDD(2.5) 38,42,48 Power Power supplies pins. Nominal 2.5 V. VDDA 36 Power Power supply for PLL core. GNDA 37 Power Power supply for PLL core. CPUT [1:0] 43,40 OUTPUT “True” clocks of differential pair CPUCLK. These pins are open drain outputs. CPUC0 39 OUTPUT “Complementary” clocks of differential pair CPUCLK. These pins are open drain outputs. IOAPIC[1:0] 47,46 OUTPUT 2.5 V IOAPIC clock output. CPU_STP# 44 INPUT CPUCLK STOP pin. This asynchronous input halts CPU and AGP clocks at logic “0” level when driven low, the stop selection can be programmed 2 through I C. 120 kΩ internal pulled-up. PCI_F0 14 OUTPUT Free running PCI clock 3.3 V output. INPUT Latch input multi function pin for frequency select. This pin is internal pull-down to GND. OUTPUT Free running PCI clock 3.3 V output. INPUT Latch input multi function pin for frequency select. This pin is internal pull-down to GND. (*FS2) PCI_F1 15 (*FS3) PCICLK [5:0] 16,17,20,21 OUTPUT 22,23 3.3 V PCI clock outputs. PCI_STP# 12 INPUT PCICLK stop pin. Stops PCICLKs at logic “0” level when input 2 low, the stop selection can be programmed through I C. 120 kΩ internal pulled-up. ZCLK [1:0] 9,10 OUTPUT Hyper Zip clock outputs. Rev.1, Nov. 2002, page 17 of 27 HD151TS404SS Pin Descriptions (cont.) Pin name No. Type Description REF0 2 OUTPUT 14.318 MHz reference clock. INPUT Latch input multi function pin for frequency select. This pin is internal pull-down to GND. OUTPUT 14.318 MHz reference clock INPUT Latch input multi function pin for frequency select. This pin is internal pull-down to GND. (*FS0) REF1 3 (*FS1) NC 4 NC 24_48MHz 26 OUTPUT SIO clock output. Default is 24 MHz. 2 This pin’s output frequency is able to change for 48 MHz by I C register. AGPCLK0 31 OUTPUT AGP clock output. AGPCLK1 30 OUTPUT AGP clock output. PD# 33 INPUT Power down pin. All circuits will be powered down. (Output state of each outputs are shown in page6 Table2.) Asynchronous active low input pin used to power down the device into low power state. The internal clocks are disabled and VCO and the crystal are stopped. The latency of power down will not be greater than 3ms. 48 MHz 27 OUTPUT 3.3 V, 48 MHz USB clock output. X1 6 INPUT XTAL input. X2 7 OUTPUT XTAL output. SDATA 34 INPUT Data input for I2C logic. This pin is internal pull-up to VDD by 120 kΩ resistor. SCLK 35 INPUT Clock input for I2C logic. This pin is internal pull-up to VDD by 120 kΩ resistor. Note: FS [3:0] & MODE Input logic levels are latched an internal power-on reset. Use 10 kΩ resistor to program logic High to VDD or GND for logic low. Rev.1, Nov. 2002, page 18 of 27 HD151TS404SS DC Electrical Characteristics / Serial Input Port Ta = 0°C to 70°C, VDD = 3.3 V Typ *1 Max Unit 0.8 V VIH 2.0 V Input Current II –50 +50 µA VI = 0 V or 3.465 V, VDD = 3.465 V Input capacitance CI 10 pF SDATA & SCLK Item Symbol Min Input Low Voltage VIL Input High Voltage Note: Test Conditions 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. AC Electrical Characteristics / Serial Input port Item Symbol Min Typ Max Unit Test Conditions Notes SCLK Frequency FSCLK 100 kHz Start Hold Time tSTHD 4.0 µs SCLK Low Time tLOW 4.7 µs SCLK High Time tHIGH 4.0 µs Data Setup Time tDSU 250 ns Data Hold Time tDHD 300 ns Stop Setup Time tSTSU 4.0 µs BUS Free Time between Stop & Start Condition tSPF 4.7 µs Normal Mode Rev.1, Nov. 2002, page 19 of 27 HD151TS404SS DC Electrical Characteristics CPUCT/C Clock (Open Drain) Ta = 0°C to 70°C, VDD = 3.3 V, VDDCPU = 2.5 V, Test Circuits = Figure3 Item Symbol Min Typ *1 Max Unit Test Conditions Output Voltage VOL 0 50 mV IOL = 1 mA Differential Cross Over Voltage VX 0.75 V Vpull-up = 1.5 V Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. AC Electrical Characteristics CPUT/C Clock (Open Drain) Ta = 0°C to 70°C, VDD = 3.3 V, VDDCPU = 2.5 V, Test Circuits = Figure3 Item Symbol Min Typ Max Unit Test Conditions Notes AC Output Impedance ZO 50 Ω VO = VX Cycle to cycle jitter tCCS ±100 ps 133 MHz CPU Group Skew (CPU clock out to CPU clock out) tskS 50 ps Slew rate tSL 1.0 V/ns 0.3 V to 1.2 V Clock Duty Cycle 50 % CPU (early) to AGP Skew 1.0 2.0 4.0 ns CPU (early) to PCI Skew 1.0 2.0 4.0 ns CPU (early) to ZCLK Skew 1.0 2.0 4.0 ns Note: 1. Difference of cycle time between two adjoining cycles. Rev.1, Nov. 2002, page 20 of 27 *1 HD151TS404SS DC Electrical Characteristics / PCI Clock Ta = 0°C to 70°C, VDD = 3.3 V, CL = 30 pF Item Symbol Min Typ *1 Max Unit Test Conditions Output voltage VOH 3.1 V IOH = –1 mA, VDD = 3.3 V VOL 50 mV IOL = 1 mA, VDD = 3.3 V IOH –22 mA VOH = 2.0 V IOL 25 mA VOL = 0.8 V Output Current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions AC Electrical Characteristics / PCI Clock Ta = 0°C to 70°C, VDD = 3.3 V, CL = 30 pF Item Symbol Min Typ Max Unit Test Conditions Notes Cycle to cycle jitter tCCS |125| ps 133 MHz, Fig.1 *1,2 PCI Group Skew (PCI clock out to PCI clock out) tskS 500 ps Rising edge @1.5 V to 1.5 V Fig.2 *2 Slew rate tSL 1.0 V/ns Clock Duty Cycle 45 50 55 % Output Impedance 30 Ω 0.4 V to 2.4 V *2 Notes: 1. Difference of cycle time between two adjoining cycles. 2. Target of design, not 100% tested in production. Rev.1, Nov. 2002, page 21 of 27 HD151TS404SS DC Electrical Characteristics / AGP Clock & ZCLK Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF Item Symbol Min Typ *1 Max Unit Test Conditions Output voltage VOH 3.1 V IOH = –1 mA, VDD = 3.3 V VOL 50 mV IOL = 1 mA, VDD = 3.3 V IOH –22 mA VOH = 2.0 V IOL 25 mA VOL = 0.8 V Output current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. AC Electrical Characteristics / AGP Clock & ZCLK Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF Item Symbol Min Typ Max Unit Test Conditions Notes Cycle to cycle jitter tCCS |250| ps 66.6 MHz, Fig1 AGP Group Skew & ZCLK Group Skew tskS 175 ps Rising edge @1.5 V to 1.5 V Fig.2 Slew rate tSL 1.0 V/ns Clock Duty Cycle 45 50 55 % Output Impedance 30 Ω Note: 1. Difference of cycle time between two adjoining cycles. Rev.1, Nov. 2002, page 22 of 27 *1 0.4 V to 2.4 V HD151TS404SS DC Electrical Characteristics / 48MHz, 24_48MHz & REF Clock Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF Item Symbol Min Typ *1 Max Unit Test Conditions Output voltage VOH 3.1 V IOH = –1 mA, VDD = 3.3 V VOL 50 mV IOL = 1 mA, VDD = 3.3 V IOH –22 mA VOH = 2.0 V IOL 16 mA VOL = 0.8 V Output current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. AC Electrical Characteristics / 48MHz, 24_48MHz & REF Clock Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF Item Symbol Min Typ Max Unit Test Conditions Notes Cycle to cycle jitter tCCS ±250 ps Slew rate tSL 0.5 V/ns Clock Duty Cycle 45 50 55 % Output Impedance 40 Ω 48 MHz, Fig1 *1, 0.4 V to 2.4 V Notes: 1. Difference of cycle time between two adjoining cycles. Rev.1, Nov. 2002, page 23 of 27 HD151TS404SS DC Electrical Characteristics / IOAPIC Ta = 0°C to 70°C, VDDAPIC = 2.5 V, VDD = 3.3 V, CL = 20 pF Item Symbol Min Typ *1 Max Unit Test Conditions Output voltage VOH 2.0 V IOH = –1 mA, VDDAPIC = 2.5 V VOL 50 mV IOL = 1 mA, VDDAPIC = 2.5 V IOH –12 mA VOH = 1.6 V IOL 12 mA VOL = 0.88 V Output Current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. AC Electrical Characteristics / IOAPIC Ta = 0°C to 70°C, VDDAPIC = 2.5 V, VDD = 3.3 V, CL = 20 pF Item Symbol Min Typ Max Unit Test Conditions Notes Cycle to cycle jitter tCCS |250| ps *1 Slew rate tSL 0.5 V/ns 0.88 V to 1.6 V Clock Duty Cycle 45 55 % Output Impedance 40 Ω Note: 1. Difference of cycle time between two adjoining cycles. Rev.1, Nov. 2002, page 24 of 27 HD151TS404SS Clock Out tcycle n+1 tcycle n t CCS = (tcycle n) - (tcycle n+1) Figure1 Cycle to Cycle Jitter (3.3 V Single Ended Clock Output) Clock Outx 1.5 V Clock Outy 1.5 V tskS Figure2 Output Clock Skew (3.3 V Single Ended Clock Output) 47 Ω 1.5 V 1.5 V 68 Ω 500 Ω CPUCLKT 680 pF 500 Ω 1.5 V TS404 47 Ω 500 Ω 680 pF CPUCLKC 68 Ω 500 Ω 1.5 V Figure3 Load Circuit for Open Drain CPUCLKT/C Rev.1, Nov. 2002, page 25 of 27 HD151TS404SS Package Dimensions Unit: mm 15.85 ± 0.3 25 1 24 0.635 0.25 ± 0.1 Rev.1, Nov. 2002, page 26 of 27 0.15 0.13 M 0.10 Min 0.78 Max 0.15 ± 0.05 2.65 Max 7.50 ± 0.3 48 10.40 ± 0.4 1.45 0˚ - 10˚ 0.60 ± 0.2 HD151TS404SS Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Sales offices Hitachi, Ltd. Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109 URL http://www.hitachisemiconductor.com/ For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-6538-6533/6538-8577 Fax : <65>-6538-6933/6538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Europe GmbH Electronic Components Group Dornacher Str 3 D-85622 Feldkirchen Postfach 201, D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://semiconductor.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan. Colophon 7.0 Rev.1, Nov. 2002, page 27 of 27