HM511664C Series 1M FP DRAM (64-kword × 16-bit) 256 refresh ADE-203-627A (Z) Rev. 1.0 Dec. 20, 1997 Description The Hitachi HM511664C Series is a CMOS dynamic RAM organized 65,536-word × 16-bit. HM511664C Series has realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM511664C Series offers Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM511664C to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII. Features • Single 5 V supply: 5 V ± 10% • Access time: 60 ns/70 ns/80 ns (max) • Power dissipation Active mode: 660 mW/ 633 mW/495 mW (max) Standby mode: 11 mW (max) • Fast page mode capability • Refresh cycles 256 refresh cycles: 4 ms • 2 variations of refresh RAS-only refresh CAS-before-RAS refresh • 2WE-byte control Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series Ordering Information Type No. Access time Package HM511664CJ-6 HM511664CJ-7 HM511664CJ-8 60 ns 70 ns 80 ns 400-mil 40-pin plastic SOJ (CP-40D) HM511664CTT-6 HM511664CTT-7 HM511664CTT-8 60 ns 70 ns 80 ns 400-mil 44-pin plastic TSOPII (TTP-44/40DA) Pin Arrangement HM511664CJ Series VCC I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 NC VCC UWE LWE RAS A0 A1 A2 A3 A4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 (Top view) 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 VSS I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 NC VSS CAS OE NC NC NC A7 A6 A5 VSS HM511664CTT Series VCC I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 NC 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 NC VCC UWE LWE RAS A0 A1 A2 A3 A4 VCC 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 VSS CAS OE NC NC NC A7 A6 A5 VSS (Top view) HM511664C Series Pin Description Pin name Function A0 to A7 Address input • Row address A0 to A7 • Refresh address A0 to A7 • Column address A0 to A7 I/O1 to I/O16 Data-in/data-out RAS Row address strobe CAS Column address strobe UWE, LWE Read/write enable OE Output enable VCC Power supply VSS Ground NC No connection Block Diagram RAS CAS UWE LWE OE Timing and control Column decoder A0 Column A1 to • • • address buffers • • • Row address buffers Row decoder A7 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array I/O buffers I/O1 to I/O16 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series Operation Table The HM511664C series has the following 10 operation modes. 1. Read cycle 2. Early write cycle 3. Delayed write cycle 4. Read-modify-write cycle 5. RAS-only refresh cycle 6. CAS-before-RAS refresh cycle 7. Fast page mode read cycle 8. Fast page mode early write cycle 9. Fast page mode delayed write cycle 10. Fast page mode read-modify-write cycle Inputs RAS CAS UWE LWE Output Operation H H D D Open Standby H L H H Valid Standby L L H H L L L *2 *2 Valid Read cycle *2 Open Early write cycle L *2 Undefined Delayed write cycle L L L L L L H to L H to L Valid Read-modify-write cycle L H D D Open RAS-only refresh cycle H to L L D D Open CAS-before-RAS refresh cycle L H to L H H L H to L L *2 *2 L H to L L L H to L H to L Valid Fast page mode read cycle *2 Open Fast page mode early write cycle L *2 Undefined Fast page mode delayed write cycle H to L Valid Fast page mode read modify-write cycle L Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS ≥ 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UWE and LWE. (Mode is set by the earliest of UWE and LWE active edge and reset by the latest of UWE and LWE inactive edge.) However write OPERATION and output High-Z control are done independently by each UWE, LWE. 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –1.0 to +7.0 V Supply voltage relative to VSS VCC –1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Notes Supply voltage VSS 0 0 0 V 2 VCC 4.5 5.0 5.5 V 1, 2 VIH 2.4 — 6.5 V 1 (I/O pin) VIL –0.5 — 0.8 V 1 (Others) VIL –1.0 — 0.8 V 1 Input high voltage Input low voltage Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V) *4 HM511664C -6 Parameter Operating current* *2 1, Standby current -7 -8 Symbol Min Max Min Max Min Max Unit Test conditions I CC1 — 120 — 115 — 90 mA RAS cycling CAS cycling, t RC = min I CC2 — 2 — 2 — 2 mA TTL interface RAS, CAS = VIH Dout = High-Z — 1 — 1 — 1 mA CMOS interface RAS, CAS, UWE, LWE, OE ≥ V CC – 0.2 V Dout = High-Z RAS-only refresh current* 2 I CC3 — 120 — 115 — 90 mA t RC = min Standby current*1 I CC5 — 5 — 5 — 5 mA RAS = VIH, CAS = VIL, Dout = enable CAS-before-RAS refresh current*2 I CC6 — 120 — 115 — 90 mA t RC = min Fast page mode current* 1, * 3 I CC7 — 120 — 115 — 90 mA t PC = min Input leakage current I LI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 6.5 V Output leakage current I LO –10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 6.5 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –2.5 mA Output low voltage 0 0.4 0 0.4 0 0.4 V Low Iout = 2.1 mA VOL Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS = VIL. 3. Address can be changed twice or less while CAS = VIH. 4. All the V CC pins should be supplied with the same voltage. And all the VSS pins should be supplied with the same voltage. 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series Capacitance (Ta = +25°C, VCC = 5 V ±10%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-in, Data-out) CI/O — 10 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)*1, *14, *15, *17, *18 Test Conditions • • • • Input rise and fall time : 5 ns Input levels: VIL = 0 V, V IH = 3.0 V Input timing reference levels : 0.8 V, 2.4 V Output load : 1 TTL gate + CL (50 pF) (Including scope and jig) 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM511664C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Random read or write cycle time t RC 105 — 125 — 145 — ns RAS precharge time t RP 40 — 50 — 60 — ns RAS pulse width t RAS 60 10000 70 10000 80 10000 ns 23 CAS pulse width t CAS 15 10000 20 10000 20 10000 ns 22, 24 Row address setup time t ASR 0 — 0 — 0 — ns Row address hold time t RAH 10 — 10 — 10 — ns Column address setup time t ASC 0 — 0 — 0 — ns Column address hold time t CAH 15 — 15 — 15 — ns RAS to CAS delay time t RCD 20 45 20 50 20 60 ns 8 RAS to column address delay time t RAD 15 30 15 35 15 40 ns 9 RAS hold time t RSH 15 — 20 — 20 — ns CAS hold time t CSH 60 — 70 — 80 — ns CAS to RAS precharge time t CRP 10 — 10 — 10 — ns OE to Din delay time t ODD 15 — 15 — 15 — ns OE delay time from Din t DZO 0 — 0 — 0 — ns CAS setup time from Din t DZC 0 — 0 — 0 — ns Transition time (rise and fall) tT 3 50 3 50 3 50 ns Refresh period t REF — 4 — 4 — 4 ms 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Notes 25 7 HM511664C Series Read Cycle HM511664C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC — 60 — 70 — 80 ns 2, 3 Access time from CAS t CAC — 15 — 20 — 20 ns 3, 4, 13 Access time from address t AA — 30 — 35 — 40 ns 3, 5, 13 Access time from OE t OAC — 15 — 20 — 20 ns 22 Read command setup time t RCS 0 — 0 — 0 — ns 20 Read command hold time to CAS t RCH 0 — 0 — 0 — ns 16, 19 Read command hold time to RAS t RRH 0 — 0 — 0 — ns 16, 19 Column address to RAS lead time t RAL 30 — 35 — 40 — ns Output buffer turn-off time t OFF1 0 15 0 15 0 15 ns 6 Output buffer turn-off time to OE t OFF2 0 15 0 15 0 15 ns 6 CAS to Din delay time t CDD 15 — 15 — 15 — ns Write Cycle HM511664C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — 0 — ns 10, 19 Write command hold time t WCH 10 — 13 — 15 — ns 20 Write command pulse width t WP 10 — 13 — 15 — ns 21 Write command to RAS lead time t RWL 20 — 20 — 20 — ns 21 Write command to CAS lead time t CWL 10 — 13 — 15 — ns 21 Data-in setup time t DS 0 — 0 — 0 — ns 11, 21 Data-in hold time t DH 10 — 13 — 15 — ns 11, 21 CAS to OE delay time t COD — 0 — 0 — 0 ns 22 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series Read-Modify-Write Cycle HM511664C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 135 — 165 — 185 — ns RAS to WE delay time t RWD 77 — 90 — 102 — ns 10, 19 CAS to WE delay time t CWD 32 — 38 — 42 — ns 10, 19 Column address to WE delay time t AWD 47 — 55 — 62 — ns 10, 19 OE hold time from WE t OEH 15 — 18 — 20 — ns 21 Refresh Cycle HM511664C -6 Parameter Symbol Min -7 -8 Max Min Max Min Max Unit Notes CAS setup time (CBR refresh cycle) t CSR 10 — 10 — 10 — ns CAS hold time (CBR refresh cycle) t CHR 10 — 10 — 10 — ns RAS precharge to CAS hold time t RPC 10 — 10 — 10 — ns CAS precharge time in normal mode t CPN 10 — 10 — 10 — ns Fast Page Mode Cycle HM511664C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode cycle time t PC 40 — 45 — 50 — ns Fast page mode CAS precharge time t CP 10 — 10 — 10 — ns Fast page mode RAS pulse width t RASC 60 100000 70 100000 80 100000 ns 12 Access time from CAS precharge t ACP — 35 — 40 — 45 ns 3, 13 RAS hold time from CAS precharge t RHCP 35 — 40 — 45 — ns 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series Fast Page Mode Read-Modify-Write Cycle HM511664C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode read-modify-write cycle time t PCM 80 — 95 — 100 — ns Fast page mode read-modify-write cycle CAS precharge to WE delay time t CPW 52 — 60 — 67 — ns 10, 21 Notes: 1. AC measurements assume t T = 5 ns. 2. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 1 TTL loads and 50 pF. 4. Assumes that t RCD ≥ tRCD (max) and tRAD ≤ tRAD (max). 5. Assumes that t RCD ≤ tRCD (max) and tRAD ≥ tRAD (max). 6. t OFF1 (max), tOFF2 (max) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ tRWD (min), tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. t RASC defines RAS pulse width in Fast page mode cycles. 13. Access time is determined by the longest among t AA , t CAC and t ACP. 14. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either t RCH or tRRH must be satisfied for a read cycle. 17.When both UWE and LWE go low at the same time, all 16-bits data are written into the device. UWE and LWE cannot be staggered within the same write/read cycles. 18. All the V CC and VSS pins shall be supplied with the same voltages. 19. t RCH, t RRH, t WCS , t RWD, t CWD and t AWD are determined by the earlier falling edge of UWE and LWE. 20. t WCH and t RCS are determined by the later rising edge of UWE or LWE. 21. t WP, t RWL, t CWL, t OEH, t DS, t DH and tCPW should be satisfied by both UWE and LWE. 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series 22. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH min/VIL max level. 23. t RAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle. 24. t CAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle. 25. t CSH (min) can be achieved when t RCD ≤ tCSH (min) – tCAS(min) 26. XXX: H or L (H: VIH (min) ≤ V IN ≤ V IH (max), L: VIL (min) ≤ V IN ≤ V IL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. Notes concerning 2WE control Please do not separate the UWE/LWE operation timing intentionally. However skew between UWE/LWE are allowed under the following conditions. (1) Each of the UWE/LWE should satisfy the timing specifications individually. (2) Different operation mode for upper/lower byte is not allowed; such as following. RAS CAS Delayed write LWE Early write UWE 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series Timing Waveforms*26 Read Cycle t RC t RAS RAS tT t RP t RSH t CRP t CAS t RCD t CSH CAS t ASR t RAD t RAL t CAH t RAH t ASC Address Column Row t RCH t RCS UWE t RRH LWE t CAC t OFF1 t AA High-Z Dout Dout t RAC t OAC t DZC Din t OFF2 t CDD High-Z t ODD t DZO OE 13 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series Early Write Cycle t RC t RAS RAS t RP tT t RSH t RCD t CAS t CSH CAS t ASR t RAH Address t ASC Row t CAH Column t WCH t WCS UWE LWE t DS Din Dout 14 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t DH Din High-Z t CRP HM511664C Series Delayed Write Cycle t RC t RAS t RP RAS t CSH t CRP tT t RCD t RSH t CAS CAS t RAH Address t CWL t RWL t ASC t ASR t CAH Column Row t RCS t WP UWE LWE t DH t DS Din Din t OEH t DZC t ODD t DZO Dout High-Z *Invalid Dout t COD t OFF2 OE * Do not enable Dout during delayed write cycle. 15 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series Read-Modify-Write Cycle t RWC t RP t RAS RAS t CRP tT t RCD t CAS CAS t RAD t ASR t ASC t RAH Address t CAH Column Row t CWL t RCS t CWD t RWL t AWD t WP UWE t AA LWE t RWD t CAC t RAC t DS t DZC High-Z Din Dout t DH High-Z Din Dout t OEH t OAC t OFF2 t DZO OE 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t ODD HM511664C Series RAS-Only Refresh Cycle t RC t RP t RAS RAS tT t CRP t CRP t RPC CAS t RAH t ASR Address Row Dout High-Z 17 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series CAS-Before-RAS Refresh Cycle t RC t RP t RC t RAS t RP t RAS t RP RAS tT t RPC t CPN t RPC t CSR t CHR t CPN t CRP t CSR CAS t CHR Address t OFF1 Dout 18 Powered by ICminer.com Electronic-Library Service CopyRight 2003 High-Z HM511664C Series Fast Page Mode Read Cycle t RASC t RP t RHCP RAS tT t CAS t RCD t CRP t RSH t PC t CSH t CP t CAS t CAS t CP CAS t RAD t ASR Address t CAH t RAH t ASC Row t ASC t ASC t CAH Column Column Column t RRH t RCS t RCS t RCH t RCH t RCS t RAL t CAH t RCH UWE LWE t CDD t DZC t DZC Din High-Z High-Z t ODD t CAC t CAC t AA t ODD t ACP t ACP High-Z t OFF1 Dout t DZO t CAC t AA t OFF1 Dout High-Z t AA t RAC t CDD t CDD t DZC t OFF1 t DZO Dout t OAC Dout t ODD t DZO t OFF2 t OFF2 t OAC t OFF2 OE t OAC 19 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series Fast Page Mode Early Write Cycle t RASC t RP RAS t CSH tT t CAS t RCD t RSH t PC t CP t CAS t CP t CAS CAS t ASR Address t RAH t ASC Row t CAH Column t WCS t WCH t ASC t CAH t ASC Column Column t WCS t CAH t WCH t WCS t WCH UWE LWE t DS Din Din Dout 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t DS t DS t DH t DH t DH Din High-Z Din t CRP HM511664C Series Fast Page Mode Delayed Write Cycle t RASC t RP RAS t CSH t RSH t PC tT t CAS t RCD t CP t CP t CAS t CAS t CRP CAS t ASC t ASR t CAH t CAH t RAH Address Row t CWL t ASC Column t ASC Column t CAH Column t CWL t CWL t RCS t WP t RWL t WP t WP UWE LWE t DH t DS Din t DH t RCS t DS Din Din t RCS t DH t DS Din t OEH High-Z Dout t ODD OE 21 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series Fast Page Mode Read-Modify-Write Cycle t RP t RASC RAS t PCM tT t RCD CAS t CP t RAD t RAH t CRP t CP t CAS t CAS t ACP t CAH t ASR Address t CAS Row t CAH t CAH tASC t ASC t ASC Column Column t RCS t AWD t CWD t CWL t RWD t WP Column t AWD t CWL t CWD t RCS t WP t CPW t RCS t CPW t CWL t AWD t RWL t CWD t WP UWE LWE t CAC t DZC t DH High-Z Din t DZC t CAC t DS t DH tDZC High-Z Din t CAC t DZO t OAC t OEH Dout t DZO Din t AA t RAC High-Z t DH High-Z Din t AA Dout t ACP t DS t DS t OAC t OEH t OFF2 t OEH Dout Dout t OFF2 t OAC t DZO t OFF2 OE t ODD 22 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t ODD t ODD HM511664C Series Package Dimension HM511664CJ Series (CP-40D) Unit: mm 25.80 26.16 Max 0.43 ± 0.10 0.41 ± 0.08 1.27 0.10 Dimension including the plating thickness Base material dimension 0.31 2.30 +– 0.14 1.30 Max 20 0.25 0.80 +– 0.17 10.16 ± 0.13 0.74 3.50 ± 0.26 1 11.18 ± 0.13 21 40 9.40 ± 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-40D — Conforms 1.73 g 23 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series Package Dimension (cont.) HM511664CTT Series (TTP-44/40DA) Unit: mm 23 10.16 44 18.41 18.81 Max 35 32 1 10 13 0.80 22 0.80 0.30 ± 0.10 0.25 ± 0.05 0.13 M 11.76 ± 0.20 1.005 Max 0.10 Dimension including the plating thickness Base material dimension 24 Powered by ICminer.com Electronic-Library Service CopyRight 2003 0.13 ± 0.05 2.40 0.17 ± 0.05 0.125 ± 0.04 1.20 Max 0° – 5° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-44/40DA Conforms — 0.43 g HM511664C Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA. 94005-1897 USA Tel: 800-285-1601 Fax:303-297-0447 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 25 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511664C Series Revision Record Rev. Date Contents of Modification 0.0 Sep. 10, 1996 Initial issue I. Ogiwara S. Suzuki Correct errors of AC Characteristics T. Oono S. Suzuki 0.1 Dec. 20, 1996 t T (min): 2/2/2 ns to 3/3/3 ns Deletion of note 23 1.0 Dec. 20, 1997 Change of Subtitle 26 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Drawn by Approved by