HM511667C Series 1M EDO DRAM (64-kword × 16-bit) 256 refresh ADE-203-625A (Z) Rev. 1.0 Dec. 20, 1997 Description The Hitachi HM511667C Series is a CMOS dynamic RAM organized 65,536-word × 16-bit. HM511667C Series has realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM511667C Series offers Extended Data Out (EDO) Page Mode as a high speed access mode. Multiplexed address input permits the HM511667C to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII. Features • Single 5 V supply: 5 V ± 10% • Access time: 60/70/80 ns (max) • Power dissipation Active mode: 660/633/495 mW (max) Standby mode: 11 mW (max) • EDO page mode capability • Refresh cycles 256 refresh cycles : 4 ms • 2 variations of refresh RAS-only refresh CAS-before-RAS refresh • 2WE-byte control Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series Ordering Information Type No. Access time Package HM511667CJ-6 HM511667CJ-7 HM511667CJ-8 60 ns 70 ns 80 ns 400-mil 40-pin plastic SOJ (CP-40D) HM511667CTT-6 HM511667CTT-7 HM511667CTT-8 60 ns 70 ns 80 ns 400-mil 44-pin plastic TSOPII (TTP-44/40DA) Pin Arrangement HM511667CJ Series VCC I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 NC VCC UWE LWE RAS A0 A1 A2 A3 A4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 (Top view) 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 VSS I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 NC VSS CAS OE NC NC NC A7 A6 A5 VSS HM511667CTT Series VCC I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 NC 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 NC VCC UWE LWE RAS A0 A1 A2 A3 A4 VCC 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 VSS CAS OE NC NC NC A7 A6 A5 VSS (Top view) HM511667C Series Pin Description Pin name Function A0 to A7 Address input • Row address A0 to A7 • Refresh address A0 to A7 • Column address A0 to A7 I/O1 to I/O16 Data-in/data-out RAS Row address strobe CAS Column address strobe UWE, LWE Read/write enable OE Output enable VCC Power supply V SS Ground NC No connection Block Diagram RAS CAS UWE LWE OE Timing and control Column decoder A0 Column A1 to • • • address buffers • • • Row address buffers Row decoder A7 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array I/O buffers I/O1 to I/O16 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series Operation Table The HM511667C series has the following 10 operation modes. 1. Read cycle 2. Early write cycle 3. Delayed write cycle 4. Read-modify-write cycle 5. RAS-only refresh cycle 6. CAS-before-RAS refresh cycle 7. EDO page mode read cycle 8. EDO page mode early write cycle 9. EDO page mode delayed write cycle 10. EDO page mode read-modify-write cycle Inputs RAS CAS UWE LWE Output Operation H H D D Open Standby H L H H Valid Standby L L H H L L L *2 *2 Valid Read cycle *2 Open Early write cycle L *2 Undefined Delayed write cycle L L L L L L H to L H to L Valid Read-modify-write cycle L H D D Open RAS-only refresh cycle H to L L D D Open CAS-before-RAS refresh cycle L H to L H H L H to L L *2 *2 L H to L L L H to L H to L Valid EDO page mode read cycle *2 Open EDO page mode early write cycle L *2 Undefined EDO page mode delayed write cycle H to L Valid EDO page mode read modify-write cycle L Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS ≥ 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UWE and LWE. (Mode is set by the earliest of UWE and LWE active edge and reset by the latest of UWE and LWE inactive edge.) However write OPERATION and output High-Z control are done independently by each UWE, LWE. 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –1.0 to +7.0 V Supply voltage relative to VSS VCC –1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Notes Supply voltage VSS 0 0 0 V 2 VCC 4.5 5.0 5.5 V 1, 2 VIH 2.4 — 6.5 V 1 (I/O pin) VIL –0.5 — 0.8 V 1 (Others) VIL –1.0 — 0.8 V 1 Input high voltage Input low voltage Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V) *4 HM511667C -6 Parameter Operating current* *2 1, Standby current -7 -8 Symbol Min Max Min Max Min Max Unit Test conditions I CC1 — 120 — 115 — 90 mA RAS cycling CAS cycling, t RC = min I CC2 — 2 — 2 — 2 mA TTL interface RAS, CAS = VIH Dout = High-Z — 1 — 1 — 1 mA CMOS interface RAS, CAS, UWE, LWE, OE ≥ V CC – 0.2 V Dout = High-Z RAS-only refresh current* 2 I CC3 — 120 — 115 — 90 mA t RC = min Standby current*1 I CC5 — 5 — 5 — 5 mA RAS = VIH, CAS = VIL, Dout = enable CAS-before-RAS refresh current*2 I CC6 — 120 — 115 — 90 mA t RC = min EDO page mode current* 1, * 3 I CC4 — 150 — 120 — 115 mA t HPC = min Input leakage current I LI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 6.5 V Output leakage current I LO –10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 6.5 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage 0 0.4 0 0.4 0 0.4 V Low Iout = 2 mA VOL Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS = VIL. 3. Address can be changed once or less within one EDO page cycle. 4. All the V CC pins should be supplied with the same voltage. And all the VSS pins should be supplied with the same voltage. 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series Capacitance (Ta = +25°C, VCC = 5 V ±10%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-in, Data-out) CI/O — 10 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS, CAS = VIH to disable Dout. AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)*1, *14, *15, *17, *18 Test Conditions • • • • • Input rise and fall time : 2 ns Input levels: VIL = 0 V, V IH = 3.0 V Input timing reference levels : 0.8 V, 2.4 V Output timing reference levels : 0.8 V, 2.0 V· Output load : 1 TTL gate + CL (50 pF) (Including scope and jig) 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM511667C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Random read or write cycle time t RC 105 — 125 — 145 — ns RAS precharge time t RP 40 — 50 — 60 — ns RAS pulse width t RAS 60 10000 70 10000 80 10000 ns 26 CAS pulse width t CAS 10 10000 13 10000 15 10000 ns 27 Row address setup time t ASR 0 — 0 — 0 — ns Row address hold time t RAH 10 — 10 — 10 — ns Column address setup time t ASC 0 — 0 — 0 — ns Column address hold time t CAH 10 — 13 — 15 — ns RAS to CAS delay time t RCD 20 45 20 50 20 60 ns 8 RAS to column address delay time t RAD 15 30 15 35 15 40 ns 9 RAS hold time t RSH 20 — 20 — 20 — ns CAS hold time t CSH 48 — 58 — 68 — ns CAS to RAS precharge time t CRP 10 — 10 — 10 — ns OE to Din delay time t ODD 15 — 15 — 15 — ns OE delay time from Din t DZO 0 — 0 — 0 — ns CAS setup time from Din t DZC 0 — 0 — 0 — ns Transition time (rise and fall) tT 2 50 2 50 2 50 ns Refresh period t REF — 4 — 4 — 4 ms 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Notes 28 7 HM511667C Series Read Cycle HM511667C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC — 60 — 70 — 80 ns 2, 3 Access time from CAS t CAC — 15 — 20 — 20 ns 3, 4, 13 Access time from address t AA — 30 — 35 — 40 ns 3, 5, 13 Access time from OE t OAC — 15 — 20 — 20 ns 22 Read command setup time t RCS 0 — 0 — 0 — ns 20 Read command hold time to CAS t RCH 0 — 0 — 0 — ns 16, 19 Read command hold time to RAS t RRH 0 — 0 — 0 — ns 16, 19 Column address to RAS lead time t RAL 30 — 35 — 40 — ns Column address to CAS lead time t CAL 18 — 23 — 28 — ns Output buffer turn-off time t OFF1 0 15 0 15 0 15 ns 6, 24 Output buffer turn-off time to OE t OFF2 0 15 0 15 0 15 ns 6 CAS to Din delay time t CDD 15 — 18 — 20 — ns RAS to Din delay time t RDD 15 — 18 — 20 — ns WE to Din delay time t WDD 15 — 18 — 20 — ns OE pulse width t OEP 15 — 20 — 20 — ns 22 Turn-off to RAS t OFR 0 15 0 15 0 15 ns 6, 24 Turn-off to WE t WEZ 0 15 0 15 0 15 ns 6 Output data hold time t OH 5 — 5 — 5 — ns 24 Output data hold time from RAS t OHR 5 — 5 — 5 — ns 24 Read command hold time from RAS t RCHR 60 — 70 — 80 — ns Read command hold time from CAS t RCHC 15 — 18 — 20 — ns Read command hold time from column address 30 — 35 — 40 — ns t RCHA 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series Write Cycle HM511667C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — 0 — ns 10, 19 Write command hold time t WCH 10 — 13 — 15 — ns 20 Write command pulse width t WP 10 — 13 — 15 — ns 21 Write command to RAS lead time t RWL 10 — 13 — 15 — ns 21 Write command to CAS lead time t CWL 10 — 13 — 15 — ns 21 Data-in setup time t DS 0 — 0 — 0 — ns 11, 21 Data-in hold time t DH 10 — 13 — 15 — ns 11, 21 Read-Modify-Write Cycle HM511667C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 135 — 165 — 185 — ns RAS to WE delay time t RWD 77 — 90 — 102 — ns 10, 19 CAS to WE delay time t CWD 32 — 38 — 42 — ns 10, 19 Column address to WE delay time t AWD 47 — 55 — 62 — ns 10, 19 OE hold time from WE t OEH 15 — 18 — 20 — ns 21 Refresh Cycle HM511667C -6 Parameter Symbol Min -7 -8 Max Min Max Min Max Unit Notes CAS setup time (CBR refresh cycle) t CSR 10 — 10 — 10 — ns CAS hold time (CBR refresh cycle) t CHR 10 — 10 — 10 — ns RAS precharge to CAS hold time t RPC 10 — 10 — 10 — ns CAS precharge time in normal mode t CPN 10 — 10 — 10 — ns 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series EDO Page Mode Cycle HM511667C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes EDO page mode cycle time t HPC 25 — 30 — 35 — ns EDO page mode CAS precharge time t CP 10 — 13 — 15 — ns EDO page mode RAS pulse width t RASC 60 100000 70 100000 80 100000 ns 12 Access time from CAS precharge t ACP — 35 — 40 — 45 ns 3, 13 RAS hold time from CAS precharge t RHCP 35 — 40 — 45 — ns Output data hold time from CAS low t DOH 5 — 5 — 5 — ns CAS hold time referred OE t COL 10 — 13 — 20 — ns CAS to OE setup time t COP 5 — 5 — 5 — ns Read command hold time from CAS precharge t RCHP 35 — 40 — 45 — ns 23 25 EDO Page Mode Read-Modify-Write Cycle HM511667C -6 Parameter Symbol Min -7 -8 Max Min Max Min Max Unit Notes EDO page mode read-modify-write t HPCM cycle time 66 — 77 — 86 — ns EDO page mode read-modify-write t CPW cycle CAS precharge to WE delay time 52 — 60 — 67 — ns 10, 21 Notes: 1. AC measurements assume t T = 2 ns. 2. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 1 TTL loads and 50 pF. 4. Assumes that t RCD ≥ tRCD (max) and tRAD ≤ tRAD (max). 5. Assumes that t RCD ≤ tRCD (max) and tRAD ≥ tRAD (max). 6. t OFF1 (max), tOFF2 (max), tOFR (max) and tWEZ (max) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ tRWD (min), tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. t RASC defines RAS pulse width in EDO page mode cycles. 13. Access time is determined by the longest among t AA , t CAC and t ACP. 14. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either t RCH or tRRH must be satisfied for a read cycle. 17. When both UWE and LWE go low at the same time, all 16-bits data are written into the device. UWE and LWE cannot be staggered within the same write/read cycles. 18. All the V CC and VSS pins shall be supplied with the same voltages. 19. t RCH, t RRH, t WCS , t RWD, t CWD and t AWD are determined by the earlier falling edge of UWE and LWE. 20. t WCH and t RCS are determined by the later rising edge of UWE or LWE. 21. t WP, t RWL, t CWL, t OEH, t DS, t DH and tCPW should be satisfied by both UWE and LWE. 22. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH min/VIL max level. 23. t HPC (min) can be achieved during a series of EDO page mode early write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle tHPC (tCAS + tCP + 2tT) becomes greater than the specified t HPC (min) value. 24. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH , and between t OFR and t OFF. 25. t DOH defines the time at which the output level satisfied the output timing reference levels. Measured with the test conditions. 26. t RAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle. 27. t CAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle. 28. t CSH (min) can be achieved when tRCD ≤ tCSH (min) – tCAS (min). 29. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series Notes concerning 2WE control Please do not separate the UWE/LWE operation timing intentionally. However skew between UWE/LWE are allowed under the following conditions. (1) Each of the UWE/LWE should satisfy the timing specifications individually. (2) Different operation mode for upper/lower byte is not allowed; such as following. RAS CAS Delayed write LWE Early write UWE 13 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series Timing Waveforms*29 Read Cycle t RC t RAS RAS tT t RP t CRP t RSH t CAS t CSH t RCD CAS t RAD t ASR Address t RAL t CAH t RAH t ASC Row Column t RCS t RCHA t CAL t OHR t RCHR t RCHC UWE LWE t RDD t OH t RCH t RRH t OFR t CAC t AA t OFF1 Dout Dout t RAC t OFF2 t DZC t OAC t WDD t ODD t DZO 14 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t WEZ High-Z Din OE t CDD t OEP HM511667C Series Early Write Cycle t RC t RAS t RP RAS tT t RSH t RCD t CAS t CRP t CSH CAS t ASR t RAH Address t ASC Row t CAH Column t WCH t WCS UWE LWE t DS Din Dout t DH Din High-Z 15 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series Delayed Write Cycle t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT CAS t ASR Address t ASC t RAH t CWL t RWL t CAH Row Column t RCS t WP UWE LWE t DS t DH High-Z Din Din t DZC t ODD t DZO t OEH Dout Invalid Dout* t OFF2 OE * * Do not enable Dout during delayed write cycle. 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series Read-Modify-Write Cycle t RWC t RP t RAS RAS tT t CRP t CAS t RCD CAS t RAD t ASR t ASC t RAH Address t CAH Column Row t CWL t RCS t CWD t RWL t AWD t WP UWE LWE t AA t RWD t CAC t RAC t DS t DZC High-Z Din Dout t DH High-Z Din Dout t OEH t OAC t OFF2 t DZO OE t ODD t OEP 17 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP tRPC CAS t RAH t ASR Address Row Dout 18 Powered by ICminer.com Electronic-Library Service CopyRight 2003 High-Z tCRP HM511667C Series CAS-Before-RAS Refresh Cycle t RC t RP t RC t RAS t RP t RAS t RP RAS tT t RPC t CPN t RPC t CSR t CHR t CPN t CRP t CSR t CHR CAS Address t OFF1 Dout High-Z 19 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series EDO Page Mode Read Cycle (tHPC minimum cycle operation) t RASC t RHCP t RP RAS tT t CSH t RCD t HPC t CAS t CP t CAS t RSH t CP t CRP t CAS CAS t ASR t CAL t RAD t RAH Address t CAH tASC Row Column 1 t CAL t CAL t ASC t CAH Column 2 t RAL t CAH t ASC Column 3 t RCHA t RRH t RCHP t RCS t RCH t RCHC UWE LWE t WEZ t DZC t CDD High-Z Din t CAC t CAC t RAC t AA t AA t ACP t DOH Dout 1 Dout t CAC t AA t ACP t DOH Dout 2 t OFR t OH t ODD t OHR t OFF1 Dout 3 t OAC t DZO OE 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t OFF2 HM511667C Series EDO Page Mode Read Cycle (High-Z control by WE and OE) t RP RAS tT t CSH t CP t HPC t CAS CAS t RCS t CP t HPC t CAS tCAS tCAS t RCHP t RCHC t RCHA tASR tRAH t ASC tCAH Row tASC t ASC t CAH Column 2 tCAL tDZC t RRH t RCH t t RAL RCHC t ASC t CAH Column 1 t CRP t RHCP t CP t RCH t RCS t RCHR UWE LWE Address t HPC t RASC Column 3 t CAL t WDD t CAH Column 4 t CAL tRDD tCDD t CAL High-Z Din tCOL tDZO tCOP tODD OE tAA tCAC tCAC tAA Dout tOFF2 Dout 1 tACP tAA tCAC tWEZ tRAC tOFR tOHR tOFF2 tACP tACP tOAC tOAC Dout 2 tAA tOFF2 tDOH Dout 2 tCAC tOFF1 tOH tOAC Dout 3 Dout 4 21 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series EDO Page Mode Early Write Cycle (tHPC minimum cycle operation) t RASC t RP RAS tT t CSH t RCD t RSH t HPC t CAS t CP t CAS t CAS t CP CAS t ASR Address t RAH Row t ASC t CAH Column t WCS t WCH t ASC t CAH Column t WCS t ASC t CAH Column t WCH t WCH t WCS UWE LWE t DS Din Din Dout 22 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t DH t DS Din High-Z t DH t DS t DH Din t CRP HM511667C Series EDO Page Mode Delayed Write Cycle t RP t RASC RAS tT t CSH tRCD t HPC t CAS t CP t CAS t RSH t CAS t CP t CRP CAS t ASR t RAH Address t ASC t CAH t ASC t CAH Row t CAH t ASC Column Column Column t CWL t CWL t RCS t CWL t WP t WP t WP t RWL UWE LWE t DH t DS Din t RCS t DH t DS t DH t DS Din Din t RCS Din t OEH High-Z Dout t ODD OE 23 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series EDO Page Mode Read-Modify-Write Cycle t RP t RASC RAS t RCD t HPCM tT t CAS CAS t CRP t CP t CP t CAS t CAS t RAD t RAH t ASR Address t ACP t CAH t ASC t ASC Row t ASC Column Column t CWL t AWD t CWD t RCS t CAH t CAH t AWD t CWL t CWD t RCS t WP t RWD Column t CPW t WP t RCS t CPW t CWL t AWD t RWL t CWD t WP UWE LWE t CAC t DZC t DZC t DH High-Z Din Din t AA tOAC t OEH Dout t OAC t OEH Dout t OFF2 t DS t DH t DZC High-Z Din t CAC t DZO t RAC t DZO t DH t CAC High-Z Din tAA Dout t ACP t DS t DS t AA t OAC t OEH Dout t OFF2 t DZO t OFF2 OE t ODD t ODD t OEP 24 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t OEP t ODD tOEP HM511667C Series EDO Page Mode Mix Cycle (1)*23 t RP t RASC RAS t CSH tT CAS t CAS t WCS t CAS tCAS Address t RCS tCPW tAWD t ASC tRAH Row tCAH Column 1 tCAL t DS Din tCAS t WCH WE tASR t ASC t CAH tASC t CAH Column 2 Column 3 tWP tASC t RCHP t RCHC t RRH t RCH t RCHA t RAL t CAH Column 4 t CAL t DH Din 1 t CRP t CP t CP t CP t DH t DS High-Z tRDD tCDD t CAL Din 3 tODD tWDD OE t ACP tAA tOAC tCAC tDZO t ACP tOFF2 tAA tCAC Dout 2 tAA tOFF2 tCAC tOAC t DOH Dout tOFR tWEZ tACP Dout 3 tOFF1 tOH Dout 4 25 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series EDO Page Mode Mix Cycle (2)*23 t RP t RASC RAS tT t CSH t CAS CAS t RCS t RCHR t CAS Address tCAS t RCH t WCS t WCH tCAS Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 tCAL t DS High-Z Din t DH Column 4 Din 2 tODD t RRH t RCH t RCHA t RAL t CAH tASC t CAL t DS t CAL t RCHC tWP tCPW t ASC tRAH t RCHP tCWL UWE LWE tASR t CRP t CP t CP t CP tRDD tCDD t CAL t DH Din 3 tDZO tODD tWDD tDZO OE tAA tOAC tCAC tOFF2 Dout 1 26 Powered by ICminer.com Electronic-Library Service CopyRight 2003 tOFR tWEZ tOFF2 tACP tCAC tRAC Dout t OAC tACP tAA tOFF2 tAA tCAC tOAC Dout 3 tOFF1 tOH Dout 4 HM511667C Series Package Dimension HM511667CJ Series (CP-40D) Unit: mm 25.80 26.16 Max 0.43 ± 0.10 0.41 ± 0.08 1.27 0.10 Dimension including the plating thickness Base material dimension 0.31 2.30 +– 0.14 1.30 Max 20 0.25 0.80 +– 0.17 10.16 ± 0.13 0.74 3.50 ± 0.26 1 11.18 ± 0.13 21 40 9.40 ± 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-40D — Conforms 1.73 g 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series Package Dimension (cont.) HM511667CTT Series (TTP-44/40DA) Unit: mm 23 10.16 44 18.41 18.81 Max 35 32 1 10 13 0.80 22 0.80 0.30 ± 0.10 0.25 ± 0.05 0.13 M 11.76 ± 0.20 1.005 Max 0.10 Dimension including the plating thickness Base material dimension 28 Powered by ICminer.com Electronic-Library Service CopyRight 2003 0.13 ± 0.05 2.40 0.17 ± 0.05 0.125 ± 0.04 1.20 Max 0° – 5° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-44/40DA Conforms — 0.43 g HM511667C Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA. 94005-1897 USA Tel: 800-285-1601 Fax:303-297-0447 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 29 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM511667C Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.0 Aug. 30, 1996 Initial issue I. Ogiwara S. Suzuki 1.0 Dec. 20, 1997 Change of Subtitle 30 Powered by ICminer.com Electronic-Library Service CopyRight 2003