HM5164805A Series HM5165805A Series 64M EDO DRAM (8-Mword × 8-bit) 8k refresh/4k refresh ADE-203-458B (Z) Rev. 2.0 Oct. 30, 1997 Description The Hitachi HM5164805A Series, HM5165805A Series are CMOS dynamic RAMs organized 8,388,608word × 8-bit. They employ the most advanced CMOS technology for high performance and low power. The HM5164805A Series, HM5165805A Series offer Extended Data Out (EDO) Page Mode as a high speed access mode. They have the package variation of standard 400-mil 32-pin plastic SOJ and standard 400-mil 32-pin plastic TSOPII. Features • Single 3.3 V supply: 3.3 V +0.3 V/–0.15 V (HM5165805A-5R) 3.3 V ± 0.3 V (HM5164805A Series, HM5165805A/AL-6/7) • Access time: 50 ns/60 ns/70 ns (max) • Power dissipation Active mode : TBD/414 mW/360 mW (max) (HM5164805A Series) : 702 mW/594 mW/522 mW (max) (HM5165805A Series) Standby mode : 7.2 mW (max) : 1.08 mW (L-version) • EDO page mode capability • Refresh cycle RAS-only refresh 8192 cycles/64 ms (HM5164805A) /128 ms (HM5164805AL) (L-version) 4096 cycles/64 ms (HM5165805A) /128 ms (HM5165805AL) (L-version) CBR/Hidden refresh 4096 cycles/64 ms (HM5164805A, HM5165805A) /128 ms (HM5164805AL, HM5165805AL) (L-version) • 4 variations of refresh RAS-only refresh Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title CAS-before-RAS refresh Hidden refresh Self refresh (L-version) • Battery backup operation (L-version) Ordering Information Type No. Access time Package HM5164805AJ-6 HM5164805AJ-7 60 ns 70 ns 400-mil 32-pin plastic SOJ (CP-32DC) HM5164805ALJ-6 HM5164805ALJ-7 60 ns 70 ns HM5165805AJ-6 HM5165805AJ-7 60 ns 70 ns HM5165805ALJ-6 HM5165805ALJ-7 60 ns 70 ns HM5164805ATT-6 HM5164805ATT-7 60 ns 70 ns HM5164805ALTT-6 HM5164805ALTT-7 60 ns 70 ns HM5165805ATT-5R HM5165805ATT-6 HM5165805ATT-7 50 ns 60 ns 70 ns HM5165805ALTT-6 HM5165805ALTT-7 60 ns 70 ns 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 400-mil 32-pin plastic TSOP II (TTP-32DC) Datasheet Title Pin Arrangement HM5164805AJ/ALJ Series VCC 1 I/O0 2 HM5164805ATT/ALTT Series 32 VSS 31 I/O7 I/O0 32 VSS 2 31 I/O7 I/O1 3 30 I/O6 VCC 1 I/O1 3 30 I/O6 I/O2 4 29 I/O5 I/O2 4 29 I/O5 I/O3 5 28 I/O4 I/O3 5 28 I/O4 NC 6 27 VSS NC 6 27 VSS VCC 7 26 CAS VCC 7 26 CAS WE 8 25 OE WE 8 25 OE RAS 9 24 A12 RAS 9 24 A12 A0 10 23 A11 A0 10 23 A11 A1 11 22 A10 A1 11 22 A10 A2 12 21 A9 A2 12 21 A9 A3 13 20 A8 A3 13 20 A8 A4 14 19 A7 A4 14 19 A7 A5 15 18 A6 A5 15 18 A6 VCC 16 17 VSS VCC 16 17 VSS (Top view) (Top view) Pin Description Pin name Function A0 to A12 Address input — Row/Refresh address A0 to A12 — Column address A0 to A9 I/O0 to I/O7 Data input/Data output RAS Row address strobe CAS Column address strobe WE Read/Write enable OE Output enable VCC Power supply VSS Ground NC No connection 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title Pin Arrangement HM5165805AJ/ALJ Series VCC 1 I/O0 2 HM5165805ATT/ALTT Series 32 VSS 31 I/O7 I/O0 32 VSS 2 31 I/O7 I/O1 3 30 I/O6 VCC 1 I/O1 3 30 I/O6 I/O2 4 29 I/O5 I/O2 4 29 I/O5 I/O3 5 28 I/O4 I/O3 5 28 I/O4 NC 6 27 VSS NC 6 27 VSS VCC 7 26 CAS VCC 7 26 CAS WE 8 25 OE WE 8 25 OE RAS 9 24 NC RAS 9 24 NC A0 10 23 A11 A0 10 23 A11 A1 11 22 A10 A1 11 22 A10 A2 12 21 A9 A2 12 21 A9 A3 13 20 A8 A3 13 20 A8 A4 14 19 A7 A4 14 19 A7 A5 15 18 A6 A5 15 18 A6 VCC 16 17 VSS VCC 16 17 VSS (Top view) Pin Description Pin name Function A0 to A11 Address input — Row/Refresh address A0 to A11 — Column address A0 to A10 I/O0 to I/O7 Data input/Data output RAS Row address strobe CAS Column address strobe WE Read/Write enable OE Output enable VCC Power supply VSS Ground NC No connection 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 (Top view) Datasheet Title Block Diagram (HM5164805A Series) RAS CAS WE OE Timing and control Column decoder A0 Column A1 to • • • 8M array address 8M array buffers A9 • • • Row address buffers A10 to A12 Row decoder 8M array 8M array 8M array I/O buffers I/O0 to I/O7 8M array 8M array 8M array 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title Block Diagram (HM5165805A Series) RAS CAS WE OE Timing and control Column decoder A0 Column A1 to • • • 8M array address 8M array buffers A10 • • • Row Row decoder 8M array address 8M array 8M array I/O0 to I/O7 I/O buffers 8M array 8M array buffers 8M array A11 Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –0.5 to VCC + 0.5 (≤ 4.6 V (max)) V Supply voltage relative to VSS VCC –0.5 to +4.6 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title Recommended DC Operating Conditions (Ta = 0 to +70˚C) Parameter Symbol Min Typ Max Unit Notes Supply voltage VSS 0 0 0 V 2 VCC (HM5165805A-5R) 3.15 3.3 3.6 V 1, 2 VCC (HM5164/65805A/AL-6/7) 3.0 3.3 3.6 V 1, 2 Input high voltage VIH 2.0 — VCC + 0.3 V 1 Input low voltage VIL –0.3 — 0.8 V 1 Note: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title DC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM5164805A Series) HM5164805A -5R Parameter -6 -7 Symbol Min Max Min Max Min Max Unit Test conditions Operating current* , * 2 I CC1 — TBD — 115 — 100 mA t RC = min Standby current I CC2 — TBD — 2 — 2 mA TTL interface RAS, CAS = VIH Dout = High-Z — TBD — 1 — 1 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC2 — TBD — 300 — 300 µA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC3 — TBD — 115 — 100 mA t RC = min Standby current* I CC5 — TBD — 5 5 RAS = VIH, CAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 — TBD — 140 — 120 mA t RC = min EDO page mode current*1, * 3 I CC7 — TBD — 110 — 95 t HPC = min Battery backup current* (Standby with CBR refresh) (L-version) I CC10 — TBD — 650 — 650 µA CMOS interface Dout = High-Z, CBR refresh: tRC = 31.3 µs t RAS ≤ 0.3 µs Self refresh mode current (L-version) I CC11 — TBD — 500 — 500 µA CMOS interface RAS, CAS ≤ 0.2 V Dout = High-Z Input leakage current I LI TBD TBD –10 10 –10 10 µA 0 V ≤ Vin ≤ VCC + 0.3 V Output leakage current I LO TBD TBD –10 10 –10 10 µA 0 V ≤ Vout ≤ VCC Dout = disable Output high voltage VOH TBD TBD 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL TBD TBD 0 0.4 0.4 Low Iout = 2 mA 1 Standby current (L-version) RAS-only refresh current* 2 1 4 — 0 mA mA V Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle tHPC . 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V +0.3 V/–0.15 V, VSS = 0 V) (HM5165805A-5R) (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM5165805A/AL-6/7) HM5165805A -5R Parameter -6 -7 Symbol Min Max Min Max Min Max Unit Test conditions Operating current* , * 2 I CC1 — 195 — 165 — 145 mA t RC = min Standby current I CC2 — 2 — 2 — 2 mA TTL interface RAS, CAS = VIH Dout = High-Z — 1 — 1 — 1 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC2 — TBD — 300 — 300 µA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC3 — 195 — 165 — 145 mA t RC = min Standby current* I CC5 — 5 5 5 RAS = VIH, CAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 — 170 — 140 — 120 mA t RC = min EDO page mode current*1, * 3 I CC7 — 150 — 125 — 110 mA t HPC = min Battery backup current* (Standby with CBR refresh) (L-version) I CC10 — TBD — 650 — 650 µA CMOS interface Dout = High-Z, CBR refresh: tRC = 31.3 µs t RAS ≤ 0.3 µs Self refresh mode current (L-version) I CC11 — TBD — 500 — 500 µA CMOS interface RAS, CAS ≤ 0.2 V Dout = High-Z Input leakage current I LI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ VCC + 0.3 V Output leakage current I LO –10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ VCC Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 2 mA 1 Standby current (L-version) RAS-only refresh current*2 1 4 — — mA Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle tHPC . 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title Capacitance (Ta = 25°C, VCC = 3.3 V +0.3 V/–0.15 V) (HM5165805A-5R) (Ta = 25°C, VCC = 3.3 V ± 0.3 V) (HM5164805A Series, HM5165805A/AL-6/7) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-in, Data-out) CI/O — 7 pF 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS and CAS = VIH to disable Dout. AC Characteristics*1, *2 , *17 (Ta = 0 to +70°C, VCC = 3.3 V +0.3 V/–0.15 V, VSS = 0 V) (HM5165805A-5R) (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM5164805A Series, HM5165805A/AL-6/7) Test Conditions • • • • • Input rise and fall time: 2 ns Input levels: 0 V, 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load:1 TTL gate + C L (50 pF) (Including scope and jig) (HM5165805A-5R) 1 TTL gate + CL (100 pF) (Including scope and jig) (HM5164805A Series, HM5165805A/AL-6/7) 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5164805A/HM5165805A -5R -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Random read or write cycle time t RC 84 — 104 — 124 — ns RAS precharge time t RP 30 — 40 — 50 — ns CAS precharge time t CP 8 — 10 — 13 — ns RAS pulse width t RAS 50 10000 60 10000 70 10000 ns CAS pulse width t CAS 8 10000 10 10000 13 10000 ns Row address setup time t ASR 0 — 0 — 0 — ns Row address hold time t RAH 8 — 10 — 10 — ns Column address setup time t ASC 0 — 0 — 0 — ns Column address hold time t CAH 8 — 10 — 13 — ns RAS to CAS delay time t RCD 12 37 20 45 20 52 ns 3 RAS to column address delay time t RAD 10 25 14 30 14 35 ns 4 RAS hold time t RSH 13 — 15 — 18 — ns CAS hold time t CSH 40 — 48 — 58 — ns CAS to RAS precharge time t CRP 5 — 5 — 5 — ns OE to Din delay time t OED 13 — 15 — 18 — ns 5 OE delay time from Din t DZO 0 — 0 — 0 — ns 6 CAS delay time from Din t DZC 0 — 0 — 0 — ns 6 Transition time (rise and fall) tT 2 50 2 50 2 50 ns 7 21 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title Read Cycle HM5164805A/HM5165805A -5R -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC — 50 — 60 — 70 ns 8, 9 Access time from CAS t CAC — 13 — 15 — 18 ns 9, 10, 16 Access time from address t AA — 25 — 30 — 35 ns 9, 11, 16 Access time from OE t OEA — 13 — 15 — 18 ns 9 Read command setup time t RCS 0 — 0 — 0 — ns Read command hold time to CAS t RCH 0 — 0 — 0 — ns Read command hold time from RAS t RCHR 50 — 60 — 70 — ns Read command hold time to RAS t RRH 5 — 0 — 0 — ns Column address to RAS lead time t RAL 25 — 30 — 35 — ns Column address to CAS lead time t CAL 15 — 18 — 23 — ns CAS to output in low-Z t CLZ 0 — 0 — 0 — ns Output data hold time t OH 3 — 3 — 3 — ns Output data hold time from OE t OHO 3 — 3 — 3 — ns Output buffer turn-off time t OFF — 15 — 15 — 15 ns 13, 20 Output buffer turn-off to OE t OEZ — 13 — 15 — 15 ns 13 CAS to Din delay time t CDD 13 — 15 — 18 — ns 5 Output data hold time from RAS t OHR 3 — 3 — 3 — ns 20 Output buffer turn-off to RAS t OFR — 13 — 15 — 15 ns 13, 20 Output buffer turn-off to WE t WEZ — 13 — 15 — 15 ns 13 WE to Din delay time t WED 13 — 15 — 18 — ns RAS to Din delay time t RDD 13 — 15 — 18 — ns 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 12 20 Datasheet Title Write Cycle HM5164805A/HM5165805A -5R -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — 0 — ns Write command hold time t WCH 8 — 10 — 13 — ns Write command pulse width t WP 8 — 10 — 10 — ns Write command to RAS lead time t RWL 13 — 15 — 18 — ns Write command to CAS lead time t CWL 10 — 10 — 13 — ns Data-in setup time t DS 0 — 0 — 0 — ns Data-in hold time t DH 8 — 10 — 13 — ns 14 Read-Modify-Write Cycle HM5164805A/HM5165805A -5R -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 111 — 149 — 175 — ns RAS to WE delay time t RWD 67 — 78 — 91 — ns 14 CAS to WE delay time t CWD 30 — 33 — 39 — ns 14 Column address to WE delay time t AWD 42 — 48 — 56 — ns 14 OE hold time from WE t OEH 13 — 15 — 18 — ns Refresh Cycle HM5164805A/HM5165805A -5R -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes CAS setup time (CBR refresh cycle) t CSR 5 — 5 — 5 — ns CAS hold time (CBR refresh cycle) t CHR 8 — 10 — 10 — ns WE setup time (CBR refresh cycle) t WRP 0 — 0 — 0 — ns WE hold time (CBR refresh cycle) t WRH 10 — 10 — 10 — ns RAS precharge to CAS hold time t RPC 5 — 0 — 0 — ns 13 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title EDO Page Mode Cycle HM5164805A/HM5165805A -5R -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes EDO page mode cycle time t HPC 20 — 25 30 ns 19 EDO page mode RAS pulse width t RASP — 100000 — 100000 — 100000 ns 15 Access time from CAS precharge t CPA — 28 — 35 — 40 ns 9, 16 RAS hold time from CAS precharge t CPRH 28 — 35 — 40 — ns Output data hold time from CAS low t DOH 3 — 3 — 3 — ns CAS hold time referred OE t COL 8 — 10 — 13 — ns CAS to OE setup time t COP 8 — 10 — 10 — ns Read command hold time from CAS precharge t RCHC 28 — 35 — 40 — ns Write pulse width during CAS precharge t WPE 8 — 10 — 10 — ns OE precharge time 8 — 10 — 10 — ns t OEP — — 9 EDO Page Mode Read-Modify-Write Cycle HM5164805A/HM5165805A -5R -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes EDO page mode read- modify-write cycle time t HPRWC 57 — 68 — 79 — ns WE delay time from CAS precharge t CPW 45 — 54 — 62 — ns 14 Refresh (HM5164805A Series) Parameter Symbol Max Unit Notes Refresh period t REF 64 ms 8192 cycles Refresh period (L-version) t REF 128 ms 8192 cycles Parameter Symbol Max Unit Notes Refresh period t REF 64 ms 4096 cycles Refresh period (L-version) t REF 128 ms 4096 cycles Refresh (HM5165805A Series) 14 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title Self Refresh Mode (L-version) HM5164805AL/HM5165805AL -5R -6 -7 Parameter Symbol Min Max Min Max Min Max Unit RAS pulse width (self refresh) t RASS TBD — 100 — 100 — µs RAS precharge time (self refresh) t RPS TBD — 110 — 130 — ns CAS hold time (self refresh) t CHS TBD — –50 — –50 — ns Notes Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 50 pF (HM5165805A-5R) and 1 TTL loads and 100 pF (HM5164805A Series, HM5165805A/AL-6/7). 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t RASP defines RAS pulse width in EDO page mode cycles. 16. Access time is determined by the longest among t AA , t CAC and t CPA. 17. All the V CC and VSS pins shall be supplied with the same voltages. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 15 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title 20. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH and between tOFR and t OFF. 21. t CSH (min) can be achieved when tRCD ≤ tCSH (min) – tCAS (min). 22. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS > 100 µs, then RAS precharge time should use tRPS instead of tRP. 23. CBR burst refresh or 4096 cycles of distributed CBR refresh with 15.6 µs interval should be executed within 64 ms immediately after exiting from and before entering into the self refresh mode. 24. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 25. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title Timing Waveforms*25 Read Cycle tRC tRAS tRP RAS tCSH tCRP tRCD tT tRSH tCAS CAS tRAD tASR Address tRAH tRAL tCAL tASC tCAH Column Row tRRH tRCHR tRCS tRCH WE tDZC tCDD tWED tRDD High-Z Din tDZO tOEA tOED OE tOEZ tOHO tOFF tOH tOFR tOHR tCAC tAA tRAC tCLZ tWEZ Dout Dout 17 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title Early Write Cycle tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT CAS tASR Address tRAH Row tASC tCAH Column tWCS tWCH WE tDS Din Dout tDH Din High-Z* * t WCS 18 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t WCS (min) Datasheet Title Delayed Write Cycle*18 tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT CAS tASR Address tRAH tASC Row tCAH Column tCWL tRWL tWP tRCS WE tDS tDZC High-Z Din Din tOED tDZO tDH tOEH tOEP OE tOEZ tCLZ High-Z Dout Invalid Dout 19 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title Read-Modify-Write Cycle*18 tRWC tRAS tRP RAS tT tRCD tCAS tCRP CAS tRAD tASR Address tASC tRAH Row tCAH Column tCWL tCWD tRCS tRWL tWP tAWD tRWD WE tDZC tDS High-Z Din Din tDH tOED tDZO tOEH tOEA tOEP OE tCAC tAA tOEZ tRAC tOHO Dout Dout tCLZ 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 High-Z Datasheet Title RAS-Only Refresh Cycle tRC tRAS tRP RAS tT tRPC tCRP tCRP CAS tASR tRAH Row Address tOFR tOFF High-Z Dout 21 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP RAS t RPC t CSR t CHR t RPC tT CAS t CP t WRP t WRH t CP WE Address t OFR t OFF Dout 22 Powered by ICminer.com Electronic-Library Service CopyRight 2003 High-Z t CRP Datasheet Title Hidden Refresh Cycle tRC tRC tRAS tRP tRAS tRC tRP tRAS tRP RAS tT tRSH tCHR tCRP tRCD CAS tRAD tASR Address tRAH tRAL tASC Row tCAH Column tRRH tRCS tRCH WE tWED tDZC tCDD tRDD High-Z Din tDZO tOED tOEA OE tCAC tAA tRAC tOFF tCLZ Dout Powered by ICminer.com Electronic-Library Service CopyRight 2003 tOEZ tWEZ tOHO tOH Dout tOFR tOHR 23 Datasheet Title EDO Page Mode Read Cycle (1) t RP t HPC t RASP RAS tT t CSH t CP t HPC t CAS CAS t HPC t CPRH t CP t t CRP RSH t CAS t RCHR t RCS t CP tCAS tCAS t RCHC t RCH t RCS t RRH t RCH WE tASR Address tRAH tASC Row tCAH Column 1 t WPE t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t CAL t RAL t CAH tASC t WED Column 4 t CAL t CAL tRDD tCDD tDZC High-Z Din tCOL tDZO tCOP t OEP tOED tOEP OE tAA tCAC tCAC tAA tWEZ tCPA tAA tCAC tOEZ tOHO tDOH Dout 2 Dout 2 tOHO Dout 3 tCAC tOHO tOFF tOH tOEA Dout 4 Dout 1 tAA tOEZ tOEA tRAC Dout tOFR tOHR tOEZ tCPA tCPA tOEA 24 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title EDO Page Mode Read Cycle (2) t RP t RASP RAS tT t CSH t CP t HPC t CAS CAS tHPC t CP t HPC t CP tRSH t CAS t CAS t CRP tCAS t RCHC t RRH t RCH t RCS WE tASR Address tRAH tASC Row tCAH t ASC t CAH t ASC t CAH Column 1 Column 2 t CAL t RAL t CAH tASC Column 3 t CAL t WED Column 4 t CAL tRDD t CAL tDZC tCDD High-Z Din tCOL tDZO tCOP t OEP tOED tOEP OE tAA tCAC tCAC tAA tOEZ tOHO tDOH tRAC Dout tCPA tAA tCAC tCPA tOEA tOEA tAA tOEZ tDOH tOHO Dout 1 Dout 2 Dout 2 tOFR tOHR tOEZ tCPA Dout 3 tCAC tOHO tOFF tOH tOEA Dout 4 25 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title EDO Page Mode Early Write Cycle tRP tRASP RAS tT tCSH tHPC tCAS tRCD tCP tRSH tCAS tCP tCAS tCRP CAS tASR Address Row tRAH tASC tCAH Column 1 tWCS tWCH tASC tCAH Column 2 tWCS tWCH tASC tCAH Column N tWCS tWCH WE tDS Din tDH Din 1 Dout tDS tDH Din 2 tDS tDH Din N High-Z* * t WCS 26 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t WCS (min) Datasheet Title EDO Page Mode Delayed Write Cycle*18 tRASP tRP RAS tT tCP tCSH tRCD tCRP tCP tHPC tCAS tCAS tRSH tCAS CAS tRAD tASR tASC tCAH tASC tCAH Column 1 Column 2 tRAH Address Row tASC tCAH tCWL Column N tCWL tCWL tRWL tRCS tRCS tRCS WE tWP tDZC tDS tDZC tWP tDS tDZC tDH tDH Din 1 Din tDZO tOED tWP tDS tDH Din 2 tDZO tOED tOEP tOEH tDZO tOED tOEP tOEH tOEP tOEH Din N OE tCLZ tCLZ tOEZ tCLZ tOEZ tOEZ Dout Invalid Dout Invalid Dout High-Z Invalid Dout 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title EDO Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t HPRWC t CP t RCD t RSH t CP t CAS t CAS t CRP t CAS CAS t RAD t ASR Address t ASC t RAH Row t ASC t CAH t CAH Column 1 t ASC t CAH Column 2 t RWD t CWL t AWD t CPW t CWL t CPW t AWD t RCS t CWD Column N t CWL t AWD t RCS t CWD t RWL t CWD WE t RCS t WP t WP t DZC t DS t WP t DZC t DS t DZC t DS t DH t DH Din 1 Din t DZO t OED t OEP t OEH t DH Din 2 t OED t DZO t OEP t OEH Din N t OED t DZO t OEP t OEH OE t OHO t OHO t OHO t OEA t CAC t OEA t CAC t AA t OEA t CAC t AA t CPA t RAC t OEZ t CLZ t AA t CPA t OEZ t CLZ t OEZ t CLZ High-Z Dout Dout 1 28 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Dout 2 Dout N Datasheet Title EDO Page Mode Mix Cycle (1)*19 t RP t RASP RAS tT t CAS CAS t CRP t CP t CP t CP t CAS tCAS tCAS t CSH tRSH t RCD t WCS t WCH tCPW tAWD WE t ASC tRAH tASR Address Row tCAH Column 1 t RRH t RCH t RCS t RCS t ASC t CAH tASC t CAH Column 2 Column 3 tWP tASC t RAL t CAH Column 4 t CAL t DS Din Din 1 tRDD tCDD t CAL t DH t DH t DS High-Z Din 3 tOED tOEP tWED OE tCPA tAA tCAC Dout tOFR tWEZ tCPA tCPA tAA tOEA t DOH Dout 2 t OEZ tCAC t OHO Dout 3 tAA tOEZ tCAC tOHO tOEA tOFF tOH Dout 4 29 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title EDO Page Mode Mix Cycle (2)*19 t RP t RASP RAS tT t CSH t CAS CAS t RCD t CAS tCAS t RCH tWCS t WCH tRAH Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t CAL t RRH t RCH tWP tCPW t ASC tRSH t RCS t RCS WE Address tCAS t RCHR t RCS tASR t CRP t CP t CP t CP t RAL t CAH tASC Column 4 t CAL t CAL t DS t DS High-Z Din t DH tRDD tCDD t DH Din 2 Din 3 t OEP t OEP tOED tOED tCOP tWED tCOL OE t OEA tAA tOEA tCAC tOEZ tCPA tAA tCAC tRAC tOEZ t OHO t OHO Dout Dout 1 30 Powered by ICminer.com Electronic-Library Service CopyRight 2003 tOFR tWEZ tCPA Dout 3 tAA tCAC tOEZ tOEA tOFF tOH tOHO Dout 4 Datasheet Title Self Refresh Cycle (L-version)*22, 23, 24 tRASS tRP tRPS RAS tRPC tCP tT tCRP tCHS tCSR CAS tWRP tWRH WE tOFR tOFF Dout High-Z 31 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title Package Dimensions HM5164805AJ/ ALJ Series HM5165805AJ/ ALJ Series (CP-32DC) Unit: mm 3.50 ± 0.26 1.165 Max 0.43 ± 0.10 0.41 ± 0.08 1.27 0.10 Dimension including the plating thickness Base material dimension 32 2.55 ± 0.46 16 0.74 0.90 ± 0.26 1 11.18 ± 0.13 17 10.16 ± 0.13 32 20.95 21.38 Max 9.40 ± 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-32DC — Conforms 1.2 g Datasheet Title HM5164805ATT/ALTT Series HM5165805ATT/ALTT Series (TTP-32DC) Unit: mm 20.95 21.35 Max 17 10.16 32 1.27 0.42 ± 0.08 0.40 ± 0.06 0.21 16 M 0.80 11.76 ± 0.20 0.13 ± 0.05 0.10 0.145 ± 0.05 0.125 ± 0.04 1.20 Max 1.15 Max Dimension including the plating thickness Base material dimension 0° – 5° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) 0.68 1 TTP-32DC Conforms — 0.51 g When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 33 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 34 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.0 Oct. 13, 1995 Initial issue S. Ikenaga J. Kitano 0.1 Apr. 30, 1996 Change format S. Ikenaga J. Kitano S. Ikenaga J. Kitano J. Kitano J. Kitano Unification of HM5164805A Series and HM5165805A Series Addition of HM5164805A/HM5165805A-5 Series Addition of HM5164805AJ/ALJ Series, HM5165805AJ/ALJ Series (CP-32DC) Pin Descriptions Addition of Row/Refresh address and Column address to address input Addition of Block Diagrams DC Characteristics (HM5164805A) I CC1 max: 105/95 mA to TBD/135/115 mA I CC3 max: 105/95 mA to TBD/135/115 mA I CC6 max: 105/95 mA to TBD/150/130 mA I CC7 max: 105/95 mA to TBD/145/125 mA Addition of note 4 DC Characteristics (HM5165805A) I CC1 max: 145/135 mA to TBD/185/165 mA I CC3 max: 125/110 mA to TBD/185/165 mA I CC6 max: 125/110 mA to TBD/150/130 mA I CC7 max: 125/110 mA to TBD/145/125 mA Addition of note 4 AC Characteristics t RCD max: 38/45 ns to TBD/45/52 ns t COP min: 5/5 ns to TBD/10/10 ns Addition of t WPE and tOEP t HPRWC min: 79/90 ns to TBD/68/79 ns Addition of notes 20 to 24 Change of notes 3 and 13 Timing waveforms Addition of t WPE and tOEP timings Deletion of note: t OEH ≥ tCWL 0.2 Jun. 12, 1996 AC Characteristics Change of notes 18 and 25 Timing waveforms Deletion of notes about undefined pins 0.3 Jan. 22, 1997 Power dissipation TBD/540/468 mW to TBD/414/360 mW (max) (HM5164805A Series) TBD/648/576 mW to TBD/594/522 mW (max) (HM5165805A Series) 35 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Datasheet Title Revision Record (cont) Rev. Date Contents of Modification Drawn by Approved by 0.3 Jan. 22, 1997 DC Characteristics (HM5164805A Series) J. Kitano J. Kitano I CC1(max): TBD/135/115 mA to TBD/115/100 mA I CC3(max): TBD/135/115 mA to TBD/115/100 mA I CC6(max): TBD/150/130 mA to TBD/140/120 mA I CC7(max): TBD/145/125 mA to TBD/110/95 mA I LO test conditions: 0 V ≤ Vout ≤ VCC + 0.3 to 0 V ≤ Vout ≤ VCC DC Characteristics (HM5165805A Series) I CC1(max): TBD/185/165 mA to TBD/165/145 mA I CC3(max): TBD/185/165 mA to TBD/165/145 mA I CC6(max): TBD/150/130 mA to TBD/140/120 mA I CC7(max): TBD/145/125 mA to TBD/125/110 mA I LO test conditions: 0 V ≤ Vout ≤ VCC + 0.3 to 0 V ≤ Vout ≤ VCC AC Characteristics Change of note 20 1.0 Sep.12, 1997 Deletion of preliminary Power dissipation Standby mode (L-version): TBD to 1.08 mW(max) DC Characteristics (HM5165805A Series) I CC2(max)(L-version): TBD/TBD/TBD µA to TBD/300/300 µA I CC10(max): TBD/TBD/TBD µA to TBD/650/650 µA I CC11(max): TBD/TBD/TBD µA to TBD/500/500 µA AC Characteristics t RAD (min): TBD/15/15 ns to TBD/14/15 ns t RWL (min): TBD/10/13 ns to TBD/15/18 ns t REF (L-version) (HM5164805A Series) 128 ms to TBD (for suspension of L-version), Correct errors (HM5164805A Series) t REF (L-version): 4096 cycles to 8192 cycles 2.0 Oct. 30, 1997 Deletion of HM5164805A/HM5165805A-5 Series Addition of HM5165805A-5R Addition of specification for HM5164805AL Power dissipation TBD/594/522 mW to 702/594/522 mW (HM5165805A) Recommended DC Operating Conditions Addition of VCC (HM5165805A-5R): 3.15/3.3/3.6 V DC Characteristics (HM5164805A Series) I CC2 max: TBD/TBD/TBD to TBD/300/300 µA I CC10 max: TBD/TBD/TBD to TBD/650/650 µA I CC11 max: TBD/TBD/TBD to TBD/500/500 µA 36 Powered by ICminer.com Electronic-Library Service CopyRight 2003 M. Tsunozaki M. Saeki Datasheet Title Revision Record (cont) Rev. Date Contents of Modification 2.0 Oct. 30, 1997 AC Characteristics Test conditions Addition of output load condition (-5R): 1 TTL gate + CL (50pF) t RAD min: TBD/14/15 ns to 10/14/14 ns t REF (L-version) (8k refresh): TBD to 128 ms Change of note 9 Drawn by Approved by Timing waveforms Correct error of EDO page mode mix cycle (1) 37 Powered by ICminer.com Electronic-Library Service CopyRight 2003