6BIT 120MSPS ADC AL1212H GENERAL DESCRIPTION FEATURES The AL1212H is a CMOS 6-Bit A/D converter for a digital video disk (DVD) partial-response maximum likelihood (PRML) system. It is a flash type A/D converter which consists of input buffer, comparator array, digital backend encoder, and output buffer. The maximum conversion rate of AL1212H is over 120MSPS and supply voltage is 5V single. - Resolution : 6Bit Differential Linearity Error : ±1.0 LSB Integral Linearity Error : ±1.0 LSB Maximum Conversion Rate : 120MSPS Digital Output : CMOS Level Power Consumption : 300mW Power Supply : 5V Single TYPICAL APPLICATIONS - Multi-media applications - Digital video disk (DVD) system - Digital broadcast satellite (DBS) receiver - Quadrature phase shift keying (QPSK) demodulator - Video applications CML AINT INCOM ITEST CLKIN VSSD VBBA VDDD VDDA VSSA REFBOT REFTOP FUNCTIONAL BLOCK DIAGRAM 4-bit ROM Block CML Level Generator Input Buffer Comparator Array FNAND Array Flip/ Flop Array Bias Current Generator 4-bit ROM Block 4-bit ROM Block 4-bit ROM Block Clock Generator Ver 1.0 (Mar. 1999) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD DSL Block Flip/ Flop Array Output Buffer DO[9:0] AL1212H 6BIT 120MSPS ADC CORE PIN DESCRIPTION NAME I/O TYPE I/O PAD PIN DESCRIPTION REFTOP AI pia_bb Reference Top Bias (3.0V) REFBOT AI pia_bb Reference Bottom Bias (2.0V) CML AB pia_bb Internal Bias Point (open=use internal bias circuit) VDDA AP vdda Analog Power (5.0V) VBBA AG vbba Analog Sub Bias VSSA AG vssa Analog Ground AINT AI piar10_bb INCOM AB pia_bb Internal Bias Point (open=use internal bias circuit) ITEST AB pia_bb Internal Bias Point (open=use internal bias circuit) CLKIN DI piar50_bb DO[5:0] DO poa_bb Digital Output VSSD DG vssd Digital Ground VDDD DP vddd Digital Power (5.0V) Analog Input Input Span : 1.5~3.5 V I/O TYPE ABBR. - AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional - AP DP AG DG : : : : Analog Power Digital Power Analog Ground Digital Ground Clock Input VSSD VDDD VBBA VSSA VDDA CORE CONFIGURATION al1212h AINT DO[5:0] SEC ASIC 2 / 11 ITEST INCOM CML REFBOT REFTOP CLKIN ANALOG AL1212H 6BIT 120MSPS ADC ABSOLUTE MAXIMUM RATINGS Characteristics Value Symbol Unit Supply Voltage VDD 7.0 V Analog Input Voltage AINT VSS to VDD V Digital Input Voltage CLKIN VSS to VDD V Digital Output Voltage VOH, VOL VSS to VDD V 3.0/2.0 V -45 to 125 ºC Reference Voltage REFTOP/REFBOT Storage Temperature Range Tstg NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5KΩ resistor (Human body model). RECOMMENDED OPERATING CONDITIONS Symbol Min Typ Max Unit Supply Voltage VDDA - VSSA VDDD - VSSD 4.5 5.0 5.5 V Supply Voltage Difference VDDA - VDDD -0.1 0.0 0.1 V REFTOP REFBOT - 3.0 2.0 - V AINT 1.5 - 3.5 V VIL VIH 4.5 - 0.5 - V Topr 0 - 70 ºC Characteristics Reference Input Voltage Analog Input Voltage Digital Input 'L' Voltage Digital Input 'H' Voltage Operating Temperature NOTES 1. It is strongly recommended that all the supply pins (VDDA, VDDD, VDDO) be powered from the same source to avoid power latch-up. SEC ASIC 3 / 11 ANALOG AL1212H 6BIT 120MSPS ADC DC ELECTRICAL CHARACTERISTICS Symbol Min Typ Max Unit - - 6 - Bits - Reference Current IREF - 0.8 - mA REFTOP : 3.0V REFBOT : 2.0V Differential Linearity Error DLE - - ±1.0 LSB AINT : 1.5V ~ 3.5V (Ramp Input) Integral Linearity Error ILE - - ±1.0 LSB Bottom Offset Voltage Error EOB - 1 3 LSB EOB = AINT(0,1)-REFBOT Top Offset Voltage Error EOT - 1 3 LSB EOT = REFTOP-AINT(62,63) Characteristics Resolution Conditions Fs : 120MHz NOTES 1. Converter Specifications (unless otherwise specified) VDDA=5.0V VDDD=5.0V SUBST=0.0V VSSA=.0.0V VSSD=0.0V REFTOP=3.0V REFBOT=2.0V Ta=25ºC 2. TBD : To Be Determined AC ELECTRICAL CHARACTERISTICS Characteristics Conversion Rate Dynamic Supply Current Digital Output Data Delay Signal to Noise Ratio SEC ASIC Symbol Min Typ Max Unit Fs - 120 - MSPS Is (IREF) - 60 (0.8) 66 mA Is = I(VDDA) + I(VDDD) Fs : 120MHz td - 1.1 - ns See "DELAY TIMING DIAGRAM" SNDR 32 34 - dB AINT : 20MHz (Sine Input) Fs : 120MHz 4 / 11 Conditions ANALOG AL1212H 6BIT 120MSPS ADC DELAY TIMING DIAGRAM AIN(1) AIN(2) AIN(3) AINT CLKIN td DO DO (-1) DO (0) DO (1) DO (2) Signal Delay SEC ASIC 5 / 11 ANALOG AL1212H 6BIT 120MSPS ADC FUNCTIONAL DESCRIPTION 1. AL1212H is a flash A/D converter, which consists of input buffer, comparator array, digital backend encoder, and clock generator. generator generates approximately 1 MHz low frequency clocks, which are supplied to preamplifiers and input buffer while digital clock generator generates a 120 MHz high frequency clock, which is supplied to latches and digital backend encoder. 2. The input buffer is used to reduce a relatively large input capacitance of the A/D converter and convert single-ended input to differential output, which is provided to comparator array. 3. Comparator array generates a thermometer code from analog input and reference levels. As it has an interpolation factor of 2, this architecture halves the number of preamplifiers but maintains the same number of latches without extra capacitors and resistors. Each preamplifier amplifies the analog input with performing an auto-zero function simultaneously. Each latch converts analog output of the preamplifier into fully digital signal by positive feedback operation. 4. The digital backend part composed of logic gates and ROM blocks converts the comparator outputs into 6-bit binary-coded digital words. The FNAND array, which converts a thermometer code of the comparators into a single HIGH level output, consists of 3-input NAND gates for sparkle code suppression. The digital backend encoding block consists of four 4-bit ROMs to achieve fast encoding, low power consumption, and small digital area. Each FROM block encodes 16-bit input code into 4-bit LSB and generates extra 1-bit, named a group selection bit (GSB), which becomes HIGH when the 4-bit output code is valid. DSL block, which consists of some logic gates, generates 2-bit MSB from the 4-bit GSBs. To prevent timing errors, the digital backend part contains two stage flip/flop arrays which synchronize propagated signals with the external clock. 5 Clock generator consists of analog clock generator and digital clock generator. Analog clock SEC ASIC 6 / 11 ANALOG Analog Input Clock Input AINT VSSA CLKIN 5.0V VSSA VBBA 5.0V VDDD al1212h 3.0V Top Reference 2.0V Bottom Reference CML VSSD DO[5:0] VSSA ITEST VSSA REFBOT VSSD INCOM VDDA REFTOP ANALOG CORE DSP HOST : 1nF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 10uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED NOTES 6-bit Digital Output MUX BIDIRECTIONAL PAD ADC Function Measuring & Digital Input Forcing ANALOG 7 / 11 SEC ASIC AL1212H 6BIT 120MSPS ADC CORE EVALUATION GUIDE 1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. 2. The reference voltages should be biased externally through REFTOP and REFBOT pins. AL1212H 6BIT 120MSPS ADC CORE LAYOUT GUIDE 1. The width of all signal and power lines, which are connected to the ports of AL1212H block, must be same to one of the connected ports. 2. The power lines, which have over 20um width, may be designed by the slit form. 3. Each power line, which has same label, must be tied in front of the I/O pad block. 4. Analog signal lines (AINT, REFTOP, REFBOT, CML, INCOM, and ITEST) must be separated to the digital lines (CLKIN and DO[5:0]). 5. The lines of AINT and CLKIN may be designed as a straight line and maintain an enough space (over 10um) with other lines as it possible. SEC ASIC 8 / 11 ANALOG AL1212H 6BIT 120MSPS ADC PACKAGE CONFIGURATION 0.1u 3.0V 10u 10u 2.0V 1 REFTOP VDDD 48 2 REFTOP VDDD 47 3 REFBOT VSSD 46 4 REFBOT VSSD 45 5 CML NC 44 6 VDDA NC 43 7 VDDA NC 42 8 VBBA NC 41 9 VSSA DO[5] 40 10 VSSA DO[4] 39 11 AINT DO[3] 38 12 NC DO[2] 37 13 INCOM DO[1] 36 14 NC DO[0] 35 15 NC NC 34 16 ITEST NC 33 17 NC NC 32 18 VDDO NC 31 19 VSSO NC 30 20 CLKIN NC 29 21 NC NC 28 22 NC NC 27 23 NC NC 26 24 NC NC 25 1n 1n 0.1u 0.1u 5.0V 10u 1n 0.1u 0.1u Analog input 50 1K 0.1u 0.1u 5.0V 10u 0.1u 1n Clock in 50 al1212h_top 0.1u 1n 5.0V 10u 6-b ADC output : Test Pin No bias forcing, Remain floating NOTES 1. NC denotes "No Connection". SEC ASIC 9 / 11 ANALOG AL1212H 6BIT 120MSPS ADC PACKAGE PIN DESCRIPTION NAME PIN NO. I/O TYPE PIN DESCRIPTION REFTOP 1,2 AI Reference Top (3V) REFBOT 3,4 AI Reference Bottom (2V) CML 5 AB Internal Bias Point (Open=use internal bias circuit) VDDA 6, 7 AP Analog Power (5V) VBBA 8 AG Analog Sub Bias VSSA 9, 10 AG Analog Ground AINT 11 AI Analog Input + INCOM 13 AB Analog Input - (Open=use internal bias circuit) ITEST 16 AB Internal Bias Point (Open=use internal bias circuit) VDDO 18 PP Output Driving Power VSSO 19 PG Output Driving Ground CLKIN 20 DI Clock Input DO[5:0] 35~40 DO Digital Output VSSD 45,46 DG Digital Ground VDDD 47,48 DP Digital Power NOTES 1. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively. 2. INCOM is the other pin of differential input, which is fixed to 2.5 V internally. 3. CML is the bias pin, which is fixed to 2.5 V internally. 4. ITEST is the test pin of bias generator. When initial bias function is working normally the pin is fixed to 0.9 V. 5. VDDO and VSSO are output driving power pads. SEC ASIC 10 / 11 ANALOG AL1212H 6BIT 120MSPS ADC FEEDBACK REQUEST It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much. Characteristic Min Typ Max Unit Analog Power Supply Voltage V Digital Power Supply Voltage V Bit Resolution Bit Reference Input Voltage V Analog Input Voltage Vpp Analog Input Bandwidth (Maximum Input Frequency) MHz Operating Temperature Remarks ºC Integral Non-linearity Error LSB Differential Non-linearity Error LSB Bottom Offset Voltage Error mV Top Offset Voltage Error mV Maximum Conversion Rate MSPS Dynamic Supply Current mA Power Dissipation mW Signal-to-noise Ratio dB Pipeline Delay CLK Output Loading Capacitance pF Digital Output Format (Provide detailed description & timing diagram) 1. Between single input-output and differential input-output configurations, which one is suitable for your system and why? 2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason to prefer some type of configuration. 3. Freely list those functions you want to be implemented in our ADC, if you have any. SEC ASIC 11 / 11 ANALOG