ETC DG202A

DG201A/202
Monolithic Quad SPST CMOS Analog Switches
Features
Benefits
Applications
Wide Input Range
Low Distortion Switching
Can Be Driven from Comparators or Op
Amps Without Limiting Resistors
15-V Input Range
Low Off Leakage—ID(on): 0.1 nA
Low On-Resistance—rDS(on): 115 44-V Maximum Supply Ratings
TTL and CMOS Compatible
Disk Drives
Radar Systems
Communications Systems
Sample-and-Hold
Description
The DG201A and DG202 are quad SPST analog switches
designed to provide accurate switching over a wide range
of input signals. When combining a low on-resistance and
a wide signal range (15 V) with low charge-transfer these
devices are well suited for industrial and military
applications.
conducts equally well in both directions when on. When off
these switches will block up to 30 V peak-to-peak and have
a 44-V absolute maximum power supply rating.
Built on Siliconix’ high voltage metal gate process to
achieve optimum switch performance, each switch
The DG201B/DG202B upgrades are recommended for new
designs.
These two devices are differentiated by the type of switch
actions (See Truth Table).
Functional Block Diagram and Pin Configuration
Dual-In-Line and SOIC
DG201A
LCC
D1 IN1 NC IN2 D2
DG201A
IN1
1
16
IN2
D1
2
15
D2
S1
3
14
S2
V–
4
13
V+
GND
5
12
NC
S4
6
11
S3
D4
7
10
D3
IN4
8
9
IN3
Key
S1
V–
NC
GND
S4
3
2
1 20 19
4
18
5
17
6
16
7
15
8
14
9
S2
V+
NC
NC
S3
10 11 12 13
D4 IN4 NC IN3 D3
Top View
Top View
Truth Table
DG201A
DG202
0
ON
OFF
1
OFF
ON
Logic
Logic “0” 0.8 V
Logic “1” 2.4 V
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70036.
Siliconix
S-52880—Rev. E, 28-Apr-97
1
DG201A/202
Ordering Information
Temp Range
Package
Part Number
0 to 70_C
16-Pin Plastic DIP
–25 to 85_C
16-Pin CerDIP
DG201ABK
–40 to 85_C
16-Pin Narrow
SOIC
DG201ADY
DG201ACJ
DG202CJ
DG201AAK
DG201AAK/883, JM38510/12302BEA
–55 to 125_C
16-Pin CerDIP
7705301EA
DG202AK
DG202AK/883
JM38510/12302BEC
–55 to 125_C
16-Pin Sidebraze
LCC-20
7705301EC
77053012A
Absolute Maximum Ratings
Voltages Referenced to V–
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
Digital Inputsa VS, VD . . . . . . . . . . . . . . . . . . . (V–) –2 V to (V+) +2 V
or 20 mA, whichever occurs first
Current, Any Terminal Except S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% duty cycle max) . . . . . . . . . . . . . . . . . . . . . 70 mA
Storage Temperature
(K, Z Suffix) . . . . . . . . . . . . . –65 to 150_C
(J, Y Suffix) . . . . . . . . . . . . . –65 to 125_C
Power Dissipation (Package)b
16-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin SOICd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin CerDIP and Sidebrazee . . . . . . . . . . . . . . . . . . . . . . . . . .
LCC-20f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
470 mW
640 mW
900 mW
750 mW
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V– will be clamped by
internal diodes. Limit forward diode current to maximum current
ratings.
b. All leads welded or soldered to PC Board.
c. Derate 6.5 mW/_C above 25_C
d. Derate 7.6 mW/_C above 75_C
e. Derate 12 mW/_C above 75_C
f. Derate 10 mW/_C above 75_C
Schematic Diagram (Typical Channel)
V+
S
V–
–
+
V+
GND
INX
D
V–
Figure 1.
2
Siliconix
S-52880—Rev. E, 28-Apr-97
DG201A/202
Specificationsa
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
V = 15 V,
V V–
V = –15V
15V
V+
VIN = 2.4 V, 0.8 Vf
A Suffix
–55 to 125_C
Tempb
Typc
Mind
B, C, D
Suffix
Maxd
Mind
15
–15
Maxd
Unit
15
V
Analog Switch
Analog Signal Rangee
VANALOG
Full
Room
–15
115
175
175
250
250
Drain-Source On-Resistance
rDS(on)
VD = 10 V
V, IS = 1 mA
Source Off
Leakage Current
IS(off)
VS = 14 V, VD = 14 V
Room
Full
0.02
–1
–100
1
100
–5
–100
5
100
Drain Off Leakage Current
ID(off)
VD = 14 V, VS = 14 V
Room
Full
0.02
–1
–100
1
100
–5
–100
5
100
Drain On Leakage Current
ID(on)
VS = VD = 14 V
Room
Full
0.15
–1
–200
1
200
–5
–200
5
200
VIN = 2.4 V
Room
Full
–0.0004
–1
–1
VIN = 15 V
Room
Full
0.003
IINL
VIN = 0 V
Room
Full
–0.0004
Turn-On Time
tON
Room
480
600
600
Turn-Off Time
tOFF
See Switchingg Time
T t Circuit
Test
Ci it
Room
370
450
450
Room
20
Room
5
Room
5
Room
16
Room
70
Room
90
Full
W
nA
Digital Control
p Current with
Input
Input
Voltage
High
I
tV
lt
Hi
h
IINH
Input Current with
Input Voltage Low
–1
–10
1
10
–1
–10
1
10
mA
–1
–10
Dynamic Characteristics
Charge Injection
Q
Source-Off Capacitance
CS(off)
Drain-Off Capacitance
Channel On Capacitance
CD(off)
CD(on) +
CS(on)
Off Isolation
OIRR
Channel-to-Channel
Crosstalk
XTALK
CL = 1000 pF, Vg= 0 V
Rg = 0 W
VS = 0 V
V, VIN = 5 V
V, f = 1 MHz
VD = VS = 0 V, VIN = 0 V
f = 1 MHz
VIN = 5 V
V, RL = 75 W
VS = 2 V, f = 100 kHz
ns
pC
pF
dB
Power Supply
Positive Supply Current
I+
Negative Supply Current
I–
All Channels On or Off
Room
0.9
Room
–0.3
2
–1
2
mA
–1
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
Siliconix
S-52880—Rev. E, 28-Apr-97
3
DG201A/202
Typical Characteristics
Charge Injection vs. Analog Voltage
rDS(on) vs. VD and Power Supply Voltage
70
300
V+ = 15 V, V– = –15 V
TA = 25_C
60
TA = 25_C
250
50
5 V
rDS(on) ( )
Q (pC)
40
30
QD
20
10
200
8 V
QS
0
100
–10
–20
50
–30
–15
–10
–5
0
5
10
VANALOG – Analog Voltage (V)
–25
15
rDS(on) vs. VD and Temperature
180
–15
25
V+ = 15 V, V– = –15 V
VD = 14 V
10 nA
140
–5
5
15
VD – Drain Voltage (V)
Leakage vs. Temperature
100 nA
V+ = 15 V, V– = –15 V
160
1 nA
125_C
120
I S , ID
rDS(on) ( )
10 V
12 V
15 V
150
85_C
100 pA
IS(off), ID(off), ID(on)
25_C
100
10 pA
0_C
80
1 pA
–40_C
–55_C
60
–15
–10
–5
0
5
VD – Drain Voltage (V)
10
0.1 pA
–55 –35
15
Supply Current vs. Switching Frequency
85 105 125
Insertion Loss vs. Frequency
0.0
V+ = 15 V
V– = –15 V
2
I+
LOSS (dB)
I+, I– (mA)
5
25 45
65
Temperature (_C)
2.0
6
4
–15
0
I–
1 M
V+ = 15 V
V– = –15 V
Ref. 0.0 dBm
–2.0
1 k
See Figures 3 and 4
–4.0
–2
RL = 50 –6.0
–4
–6
1k
4
10 k
100 k
f – Frequency (Hz)
1M
1k
10 k
100 k
1M
f – Frequency (Hz)
10 M
Siliconix
S-52880—Rev. E, 28-Apr-97
DG201A/202
Typical Characteristics (Cont’d)
Crosstalk and Off Isolation vs. Frequency
Leakage Current vs. Analog Voltage
0
–20
V+ = 15 V
V– = –15 V
Ref. 0 dBm
RL = 50 8
6
4
–60
I S , I D (pA)
X TALK , ISO (dB)
–40
10
Off Isolation
–80
Crosstalk
–100
2
IS(off), ID(off)
0
ID(on)
–2
V+ = 15 V
V– = –15 V
TA = 25_C
For ID(off), VS = –VD
For IS(off), VD = – VS
–4
–120
See Figures 3 and 4
–6
–140
–8
–160
10 k
100 k
1M
f – Frequency (Hz)
–10
10 M
–20
Switching Time vs. Temperature
1000
V+ = 15 V
V– = –15 V
VS = 2 V
900
800
700
t ON , t OFF (ns)
t ON , t OFF (ns)
800
20
Switching Time vs. Power Supply Voltage
1000
900
–15 –10 –5
0
5
10
15
VD or VS – Drain or Source Voltage (V)
600
tON
500
400
700
600
tON
500
400
tOFF
300
300
200
200
100
–55 –35 –15
5
25 45 65
Temperature (_C)
Siliconix
S-52880—Rev. E, 28-Apr-97
85
105 125
100
tOFF
10
12
14
16
18
20
V+ – Positive Supply (V)
22
5
DG201A/202
Test Circuits
VO is the steady state output with switch on. Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output
waveform.
+15 V
Logic
Input
Switch
Input
3V
V+
tr <20 ns
tf <20 ns
50%
0V
VS = +2 V
tOFF
RL
1 kW
IN
VS
3V
GND
90%
Switch
Output
VO
D
S
CL
35 pF
V–
VO
tON
–15 V
VO = VS
RL
RL + rDS(on)
Figure 2. Switching Time
+15 V
C
+15 V
V+
C
S1
VS
V+
S
VS
VIN
D
50 W
IN1
0V, 2.4 V
Rg = 50 W
0V, 2.4 V
D1
Rg = 50 W
RL
IN
GND
V–
C
S2
NC
VO
D2
RL
IN2
0V, 2.4 V
GND
V–
C
–15 V
C = RF bypass
Off Isolation = 20 log
VS
VO
XTALK Isolation = 20 log
Figure 3. Off Isolation
VS
–15 V
VO
Figure 4. Channel-to-Channel Crosstalk
+15 V
DVO
Rg
VO
V+
S
D
IN
Vg
3V
GND
V–
VO
CL
1000 pF
INX
ON
OFF
ON
DVO = measured voltage error due to charge injection
The charge injection in coulombs is DQ = CL x DVO
–15 V
Figure 5. Charge Injection
6
Siliconix
S-52880—Rev. E, 28-Apr-97
DG201A/202
Application Hintsa
V+
Positive Supply
Voltage
(V)
V–
Negative Supply
Voltage
(V)
VIN
Logic Input Voltage
VINH(min)/VINL(max)
(V)
VS or VD
Analog Voltage Range
(V)
15
–15
2.4/0.8
–15 to 15
10
–12
2.4/0.8
–12 to 12
12
–10
2.2/0.6
–10 to 10
8b
–8
2.0/0.5
–8 to 8
Notes:
a. Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
b. Operation below 8 V is not recommended.
Applications
15 V
V+
Logic Input
Low = Sample
High = Hold
1 kW
+15 V
+15 V
–15 V
–
LM101A
VIN
+
J202
5 MW
50 pF
200 W
2N4400
5.1 MW
V–
30 pF
DG201A
–15 V
VOUT
1000 pF
J500
J507
–15 V
Acquisition Time = 25 ms
Aperature Time = 1 ms
Sample to Hold Offset = 5 mV
Droop Rate = 5 mV/s
Figure 6. Sample-and-Hold
Siliconix
S-52880—Rev. E, 28-Apr-97
7
DG201A/202
Applications (Cont’d)
+15 V
160
V1
C4
150 pF
fC4
Select
Voltage Gain – dB
TTL
Control
120
C3
1500 pF
fC3
Select
C2
0.015 mF
fC2
Select
C1
0.015 mF
fC1
Select
80
fC1
fC2
fC3
fC4
fL1
0
DG201A
fL2
fL3
fL4
GND
V–
–40
1
–15 V
10
100
1k
10 k
R3 = 1 MW
+15 V
–15 V
–
R1 = 10 kW
VOUT
LM101A
+
R2 = 10 kW
100 k
1M
Frequency – Hz
30 pF
AL (Voltage Gain Below Break Frequency) =
1
fC (Break Frequency) = 2pR C
3 X
1
fL (Unity Gain Frequency) = 2pR C
1 X
rDS(on)
–40
dB
Max Attenuation =
10 kW
R3
R1 = 100 (40 dB)
Figure 7. Active Low Pass Filter with Digitally Selected Break Frequency
+15 V
VIN1
DG200A
30 pF
+15 V
V+
+
LM101A
VIN2
–
CH1
+15 V
–15 V
DG202
CH2
V–
RF1
18 kW
RF1
9.9 kW
RF1
100 W
RG1
2 kW
RG2
100 W
RG3
100 W
GND
–15 V
Gain =
RF + RG
RG
Gain 1 (x1)
Gain 2 (x10)
Gain 3 (x100)
Gain 4 (x1000)
V–
GND
Logic High = Switch On
–15 V
Figure 8. A Precision Amplifier with Digitally Programable Input and Gains
8
Siliconix
S-52880—Rev. E, 28-Apr-97