HM514100D Series 4,194,304-word × 1-bit Dynamic RAM ADE-203-680A (Z) Rev. 1.0 Nov. 13, 1997 Description The Hitachi HM514100D is a CMOS dynamic RAM organized 4,194,304 word × 1-bit. HM514100D has realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM514100D offers Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM514100D to be packaged in standard 300-mil 26-pin plastic SOJ. Features • Single 5 V (±10%) • Access time : 60 ns/70 ns/80 ns (max) • Power dissipation Active mode : 605 mW/550 mW/495 mW (max) Standby mode : 11 mW (max) 0.55 mW (max) (L-version) • Fast page mode capability • Refresh cycles 1024 refresh cycles: 16 ms : 128 ms (L-version) • 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh • Test function • Battery backup operation (L-version) Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series Ordering Information Type No. Access time Package HM514100DS-6 HM514100DS-7 HM514100DS-8 60 ns 70 ns 80 ns 300-mil 26-pin plastic SOJ (CP-26/20D) HM514100DLS-6 HM514100DLS-7 HM514100DLS-8 60 ns 70 ns 80 ns 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series Pin Arrangement HM514100DS Series Din 1 26 VSS WE 2 25 Dout RAS 3 24 CAS NC 4 23 NC A10 5 22 A9 A0 9 18 A8 A1 10 17 A7 A2 11 16 A6 A3 12 15 A5 VCC 13 14 A4 (Top view) Pin Description Pin name Function A0 to A10 Address input • Row Address A0 to A10 • Column Address A0 to A10 • Refresh Address A0 to A9 Din Data-in Dout Data-out RAS Row address strobe CAS Column address strobe WE Read/Write enable VCC Power supply VSS Ground NC No connection 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Row Driver Row Driver Row Address Buffer Column Address Buffer Address A0–A10 256 k Memory Array Mat Row Driver 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat Din I/O Bus & Column Decoder Row Driver 256 k Memory Array Mat WE Control Circuit 256 k Memory Array Mat CAS Control Circuit 256 k Memory Array Mat RAS Control Circuit I/O Bus & Column Decoder WE 256 k Memory Array Mat CAS I/O Bus & Column Decoder Row Row Driver Driver 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat RAS 256 k Memory Array Mat Row Row Driver Driver 256 k Memory Array Mat I/O Bus & Column Decoder Row Driver 256 k Memory Array Mat Row Driver 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat HM514100D Series Block Diagram Dout I/O Buffer Row Decoder & Peripheral Circuit Row Row Driver Driver Row Driver Row Row Driver Driver Row Driver HM514100D Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –1.0 to +7.0 V Supply voltage relative to VSS VCC –1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Supply voltage VSS 0 0 0 V VCC 4.5 5.0 5.5 V 1 Input high voltage VIH 2.4 — 6.5 V 1 Input low voltage VIL –1.0 — 0.8 V 1 Note: Note 1. All voltage referred to VSS . 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) HM514100D -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Test conditions Operating current I CC1 — 110 — 100 — 90 mA RAS, CAS cycling t RC = min Standby current I CC2 — 2 — 2 — 2 mA TTL interface RAS, CAS = VIH Dout = High-Z — 1 — 1 — 1 mA CMOS interface RAS, CAS ≥ V CC – 0.2 V Dout = High-Z Notes 1, 2 Standby current (L-version) I CC2 — 100 — 100 — 100 µA CMOS interface RAS, CAS = VIH WE, Address and Din = VIH or VIL Dout = High-Z 4 RAS-only refresh current I CC3 — 110 — 100 — 90 mA t RC = min 2 Standby current I CC5 — 5 5 5 mA RAS = VIH, CAS = VIL Dout = enable 1 CAS-before-RAS refresh current I CC6 — 110 — 100 — 90 mA t RC = min Fast page mode current I CC7 — 110 — 100 — 90 mA t PC = min 1, 3 I CC10 Battery backup current (Standby with CBR refresh) (Lversion) — 200 — 200 — 200 µA t RC = 125 µs t RAS ≤ 1 µs WE = VIH, CAS = VIL OE Address, Din = VIH or VIL Dout = High-Z 4 Input leakage current I LI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 7 V Output leakage current I LO –10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 7 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –5 mA Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 4.2 mA — — Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. VCC – 0.2 V ≤ V IH ≤ 6.5 V and 0 V ≤ V IL ≤ 0.2 V. 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series Capacitance (Ta = 25°C, VCC = 5 V ± 10%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address, Data-in) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-out) CO — 7 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS, CAS = VIH to disable Dout. AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *12, *15 Test Conditions • Input rise and fall time : 5 ns • Input timing reference levels : 0.8 V, 2.4 V • Output load : 2 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM514100D -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Random read or write cycle time t RC 110 — 130 — 150 — ns RAS precharge time t RP 40 — 50 — 60 — ns RAS pulse width t RAS 60 10000 70 10000 80 10000 ns 18 CAS pulse width t CAS 15 10000 20 10000 20 10000 ns 19 Row address setup time t ASR 0 — 0 — 0 — ns Row address hold time t RAH 10 — 10 — 10 — ns Column address setup time t ASC 0 — 0 — 0 — ns Column address hold time t CAH 15 — 15 — 15 — ns RAS to CAS delay time t RCD 20 45 20 50 20 60 ns 8 RAS to column address delay time t RAD 15 30 15 35 15 40 ns 9 RAS hold time t RSH 15 — 20 — 20 — ns CAS hold time t CSH 60 — 70 — 80 — ns CAS to RAS precharge time t CRP 10 — 10 — 10 — ns Transition time (rise and fall) tT 3 50 3 50 3 50 ns Refresh period t REF — 16 — 16 — 16 ms Refresh period (L-version) t REF — 128 — 128 — 128 ms 7 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series Read Cycle HM514100D -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC — 60 — 70 — 80 ns 2, 3, 16 Access time from CAS t CAC — 15 — 20 — 20 ns 3, 4, 14, 16 Access time from address t AA — 30 — 35 — 40 ns 3, 5, 14, 16 Read command setup time t RCS 0 — 0 — 0 — ns Read command hold time to CAS t RCH 0 — 0 — 0 — ns 17 Read command hold time to RAS t RRH 0 — 0 — 0 — ns 17 Column address to RAS lead time t RAL 30 — 35 — 40 — ns Output buffer turn-off time t OFF 0 15 0 20 0 20 ns 6 Write Cycle HM514100D -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — 0 — ns Write command hold time t WCH 15 — 15 — 15 — ns Write command pulse width t WP 10 — 10 — 10 — ns Write command to RAS lead time t RWL 15 — 20 — 20 — ns Write command to CAS lead time t CWL 15 — 20 — 20 — ns Data-in setup time t DS 0 — 0 — 0 — ns 11 Data-in hold time t DH 15 — 15 — 15 — ns 11 10 Read-Modify-Write Cycle HM514100D -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 130 — 155 — 175 — ns RAS to WE delay time t RWD 60 — 70 — 80 — ns 10 CAS to WE delay time t CWD 15 — 20 — 20 — ns 10 Column address to WE delay time t AWD 30 — 35 — 40 — ns 10 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series Refresh Cycle HM514100D -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes CAS setup time (CBR refresh cycle) t CSR 10 — 10 — 10 — ns CAS hold time (CBR refresh cycle) t CHR 10 — 10 — 10 — ns RAS precharge to CAS hold time t RPC 10 — 10 — 10 — ns CAS precharge time in normal mode t CPN 10 — 10 — 10 — ns Fast Page Mode Cycle HM514100D -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode cycle time t PC 40 — 45 — 50 — ns Fast page mode CAS precharge time t CP 10 — 10 — 10 — ns Fast page mode RAS pulse width t RASC — 100000 — 100000 — 100000 ns 13 Access time from CAS precharge t ACP — 35 — 40 — 45 ns 3, 14, 16 RAS hold time from CAS precharge t RHCP 35 — 40 — 45 — ns Fast Page Mode Read-Modify-Write Cycle HM514100D -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode read-modify-write cycle time t PCM 60 — 70 — 75 — ns CAS precharge to WE delay time t CPW 35 — 40 — 45 — ns 10 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series Test Mode Cycle HM514100D -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Test mode WE setup time t WS 0 — 0 — 0 — ns Test mode WE hold time t WH 10 — 10 — 10 — ns Notes: 1. AC measurements assume t T = 5 ns. 2. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that t RCD ≥ tRCD (max) and tRAD ≤ tRAD (max). 5. Assumes that t RCD ≤ tRCD (max) and tRAD ≥ tRAD (max). 6. t OFF (max) defines the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD, t AWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min) , the cycle is a read-modifywrite and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or read-modify-write cycle. 12. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 13. t RASC defines RAS pulse width in fast page mode cycles. 14. Access time is determined by the longest among t AA , t CAC and t ACP. 15. Test mode operation specified in this data sheet is 8-bit test function controlled by control address bits - - - RA10, CA10 and CA0. This test mode operation can be performed by WE-andCAS-before-RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of eight test bits accord each other, the condition of the output data is high level. When the state of test bits do not accord, the condition of the output data is low level. Data output pin is Dout and data input pin is Din. In order to end this test mode operation, perform a CAS-before-RAS refresh cycle or a RAS-only refresh cycle. 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series 16. In a test mode read cycle, the value of tRAC , t AA , t CAC and t ACP is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 17. Either t RCH or tRRH must be satisfied 18. t RAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle. 19. t CAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle. 20. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series Timing Waveforms*20 Read Cycle t RC t RAS t RP RAS t CSH t RCD t CRP t RSH t CAS tT CAS t RAD t RAL t ASR t RAH t ASC Address Row t CAH Column t RRH t RCH t RCS WE t CAC t AA t OFF t RAC Dout 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Dout HM514100D Series Early Write Cycle tRC tRAS RAS tRP tRSH tCAS tT tRCD tCRP tCSH CAS tASR Address tRAH tASC Row tCAH Column tWCS tWCH WE tDH tDS Din Dout Din High-Z* * t WCS t WCS (min) 13 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series Delayed Write Cycle t RC t RAS t RP RAS t CSH t RCD t CRP t RSH t CAS tT CAS t CAH t ASR Address t RAH Row t ASC Column t CWL t RWL t RCS t WP WE t DH t DS Din Din t OFF Dout Invalid Dout 14 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series Read-Modify-Write Cycle t RWC t RAS t RP RAS tT t CRP t RCD t CAS CAS t RAD t ASR t RAH Address t ASC Row t CAH Column t RCS t CWD t CWL t AWD t RWD t RWL t WP WE t DS Din t DH Din t CAC t RAC Dout t AA t OFF Dout 15 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP tRPC CAS t RAH t ASR Address Row Dout 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 High-Z tCRP HM514100D Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP RAS tT t CPN CAS t CSR t RPC t CHR t CRP t CPN t RPC t WS t WH WE Address t OFF1 High-Z Dout 17 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series Hidden Refresh Cycle t RC t RAS t RP (Read) t RC t RAS t RC t RP (Refresh) t RAS t RP (Refresh) RAS tT t RSH t RCD t CHR t CRP t CAS CAS t RAD t ASR Address t RAH t RAL t ASC Row t CAH Column t RCH t RCS t RRH WE t CAC t AA t OFF t RAC Dout 18 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Dout HM514100D Series Fast Page Mode Read Cycle t RASC t RHCP t RP RAS tT t CSH t RCD t CAS t CP t PC t CAS t RSH t CP t CAS tCRP CAS t RAL t RAD t ASR Address t RAH t ASC t CAH Row t ASC Column t CAH Column t RCS t RCS t ASC t RCH t CAH Column t RCS tRRH t RCH t RCH WE t CAC t AA t AA t AA tACP t ACP t RAC Dout t CAC t CAC t OFF t OFF Dout Dout t OFF Dout 19 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series Fast Page Mode Early Write Cycle t RASC t RP RAS tT t CSH t RCD t RSH t HPC t CAS t CP t CAS t CAS t CP t CRP CAS t ASR Address t RAH Row t ASC t CAH Column t WCS t WCH t ASC t CAH Column t WCS t ASC t CAH Column t WCH t WCH t WCS WE t DS Din Din Dout t DH t DS Din t DH t DS t DH Din High-Z * t WCS 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t WCS (min) HM514100D Series Fast Page Mode Delayed Write Cycle t RASC t RP t RSH RAS tT t CSH t RCD t CAS t RWL t PC t CP t CAS t CP t CAS t CRP CAS t ASR t RAH Address t ASC t CAH t ASC t CAH Row t CAH t ASC Column Column Column t CWL t CWL t CWL t WP t RCS t WP t WP WE t DH t RCS t DS t DS t RCS t DS Din Din t DH Din Din t DH t OFF t OFF t OFF Dout Invalid Dout Invalid Dout Invalid Dout 21 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series Fast Page Mode Read-Modify-Write Cycle t RASC t RP RAS tT t RWL t PCM tCAS t RCD t CP t CP t CAS t CAS t CRP CAS t ASR Address tRAH t AWD t RCS t CWL t CAH t CWL Column Column t RAD t RWD WE t ASC t CAH Row t ASC tCAH t ASC Column t CWD t CWL t AWD t AWD t WP t WP t CWD t WP t RCS t RCS t CWD t CPW tCPW t DS t DS t DH Din Din t AA t ACP t CAC t ACP t AA t AA t OFF Powered by ICminer.com Electronic-Library Service CopyRight 2003 Din t CAC t RAC 22 t DH Din t CAC Dout t DS t DH Dout t OFF Dout t OFF Dout HM514100D Series Test Mode Cycle Set Cycle** Test Mode Cycle *,** Reset Cycle Normal Mode RAS CAS WE * CBR or RAS-only refresh ** Address, Din: H or L 23 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series Test Mode Set Cycle WE-and-CAS-Before RAS-Refresh t RC t RP t RAS t RP RAS t RPC t CSR t CHR t RPC t CRP CAS t WS t WH t CPN t CPN À@À@ tT WE Address t OFF Dout 24 Powered by ICminer.com Electronic-Library Service CopyRight 2003 High-Z * Din: H or L HM514100D Series Package Dimensions HM514100DS/DLS Series (CP-26/20D) Unit: mm 13 1.30 Max 0.43 ± 0.10 0.41 ± 0.08 5.08 1.27 0.21 2.40 +– 0.24 9 0.80 +0.25 –0.17 5 0.74 3.50 ± 0.26 1 8.51 ± 0.13 14 7.62 ± 0.13 26 16.90 17.27 Max 22 18 + 0.19 6.79 – 0.18 0.10 Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) CP-26/20D Conforms Conforms 0.6 g 25 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 26 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM514100D Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.0 Dec. 3, 1996 Initial issue T. Oono S. Suzuki 1.0 Nov. 13, 1997 Deletion of HM514100DTT Series 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003