RFMD RF2469

RF2469
Preliminary
8
W-CDMA AND PCS LOW NOISE
AMPLIFIER/MIXER DOWNCONVERTER
Typical Applications
• W-CDMA Handsets
• Commercial and Consumer Systems
• PCS Handsets
• Portable Battery-Powered Equipment
• General Purpose Downconverter
Product Description
1.00
0.90
0.60
0.24 typ
3
VCC1
ENABLE
Si CMOS
VCC1
SiGe HBT
LNA1 IN
GaAs MESFET
GND
ü
Si Bi-CMOS
GaAs HBT
20
19
18
17
16
0.05
0.23
0.13
0.50
4 PLCS
Dimensions in mm.
8
Note orientation of package.
NOTES:
1 Shaded lead is Pin 1.
2 Pin 1 identifier must exist on top surface of package by identification
mark or feature on the package body. Exact shape and size is optional.
3 Dimension applies to plated terminal: to be measured between 0.02 mm
and 0.25 mm from terminal end.
4 Package Warpage: 0.05 mm max.
5 Die Thickness Allowable: 0.305 mm max.
Package Style: LCC, 20-Pin, 4x4
Features
• Complete Receiver Front-End
• Stepped LNA/Mixer Gain Control
LNA1 OUT
1
15
LNA1 BYP
GND
2
14
LNA2
BYP
VCC1
3
13
GND
VCC1
4
12
VCC1
LNA2 IN
5
11
LO IN
Logic
Control
2.10
sq.
0.20
0.75
0.50
12°
MAX
Optimum Technology Matching® Applied
Si BJT
0.65
0.30
4 PLCS
FRONT-ENDS
The RF2469 is a receiver front-end designed for the
receive section of W-CDMA and PCS applications. It is
designed to amplify and downconvert RF signals while
providing 23dB of stepped gain control range and features digital control of the LNA gain and mixer gain. A further feature of the chip is adjustable IIP3 of the LNA and
mixer using an off-chip current setting resistor. Noise Figure, IP3, and other specs are designed to be compatible
with W-CDMA and PCS communications. The IC is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (GaAs HBT) process and
packaged in a 20-pin, leadless chip carrier with an
exposed die flag.
4.00
sq.
• Adjustable LNA/Mixer Bias Current
• 23dB Maximum Cascade Gain
• 2.5dB Noise Figure at Maximum
6
7
8
9
10
LNA2 OUT
GND
MIX IN
IF+
IF-
Cascade Gain
Functional Block Diagram
Rev A5 010717
Ordering Information
RF2469
RF2469 PCBA
W-CDMA and PCS Low Noise Amplifier/Mixer Downconverter
Fully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
8-33
RF2469
Preliminary
Absolute Maximum Ratings
Parameter
Operating Ambient Temperature
Storage Temperature
Parameter
Rating
Unit
-40 to +85
-40 to +150
°C
°C
Specification
Min.
Typ.
Max.
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Unit
T=25°C, VCC =2.78V, RF=2140MHz,
LO=2330MHz @ -10dBm
Overall
RF Frequency Range
LO Frequency Range
IF Frequency Range
2110 to 2170
2300 to 2360
190
MHz
MHz
MHz
1st LNA current setting resistor (R1) is
1.1kΩ. 1st LNA current and IIP3 are adjustable via R1.
LNA 1
Gain
Noise Figure
Input IP3
Input VSWR
Output VSWR
P1dB
Current
FRONT-ENDS
8
Condition
9
+7.0
10
1.45
+10.0
<2:1
<2:1
-3
4.5
11
1.6
-2
2
+25.0
<2:1
<2:1
1.6
0
2.4
dB
dB
dBm
dB
mA
See LNA P1dB Compression Point section.
LNA 1 Bypass
Gain
Noise Figure
Input IP3
Input VSWR
Output VSWR
Current
-5
+20.0
dB
dB
dBm
mA
Single-ended.
Optimum LO Drive -10dBm to -5dBm.
Local Oscillator Input
Input Level
LO to IF Isolation
-10
+38
dBm
dB
T=25°C, VCC =2.78V, RF=2140MHz,
LO=2330MHz@-10dBm, LNA2BYP=1,
EN=1
Mixer/LNA2 BYP High
Gain
Noise Figure
Input IP3
Input IP2
15
-7.0
+11.0
17
4.5
-3.0
+14.0
dB
dB
dBm
dBm
6
10.5
+4.0
+22.0
dB
dB
dBm
dBm
Mixer/LNA2 BYP Low
Gain
Noise Figure
Input IP3
Input IP2
8-34
4
+2.0
+19.0
LNA 2 current setting resistor (R2) is 2.4kΩ
LNA 2 current and IIP3 are adjustable via R2
T=25°C, VCC =2.78V, RF=2140MHz,
LNA2BYP=0, EN =1
LNA 2 current setting resistor (R2) is 2.4kΩ
LNA 2 current and IIP3 are adjustable via R2
Rev A5 010717
RF2469
Preliminary
Parameter
Specification
Min.
Typ.
Max.
Unit
Cascade - Condition 1
Gain
Noise Figure
Input IP3
Current Consumption*
LNA1 BYP high, LNA2 BYP high,
ENABLE high. Assuming 2.5dB filter loss.
24.5
2.55
-10.5
18.6
23
dB
dB
dBm
mA
Cascade - Condition 2
Gain
Noise Figure
Input IP3
Current Consumption*
LNA1 BYP high, LNA2 BYP low,
ENABLE high. Assuming 2.5dB filter loss.
13.5
5.2
-3.5
17
17.5
dB
dB
dBm
mA
Cascade - Condition 3
Gain
Noise Figure
Input IP3
Current Consumption*
LNA1 BYP low, LNA2 BYP high,
ENABLE high. Assuming 2.5dB filter loss.
12.5
9
+1.4
14
15
dB
dB
dBm
mA
Cascade - Condition 4
Gain
Noise Figure
Input IP3
Current Consumption*
Condition
LNA1 BYP low, LNA2 BYP low,
ENABLE High. Assuming 2.5dB filter loss.
1.50
15
+8.2
12.5
13.5
dB
dB
dBm
mA
8
Power Supply
Rev A5 010717
FRONT-ENDS
Voltage
2.7
2.75
3.3
V
*RF2469 is a very flexible device. Customers may choose different current consumption (see Low Current Configuration section).
8-35
RF2469
Pin
1
Function
LNA1 OUT
2
3
GND
VCC1
4
VCC1
5
LNA2 IN
Preliminary
Description
Interface Schematic
LNA output pin. This is an open-collector output. Externally matched to
50Ω.
LNA1 OUT
This pin is connected to the ground plane.
Supply voltage for LNA1. An external resistor is placed in series with
this pin to adjust the current and IIP3 of LNA1. A nominal value of
1.1kΩ sets the LNA1 current to 4.5mA with a minimum IIP3 of +7dBm.
External RF bypassing is required. The trace length between the
bypass caps and the pin should be minimized. Connect ground sides of
caps directly to ground.
Supply voltage for LNA2. An external resistor is placed in series with
this pin to adjust the current and IIP3 of LNA2. A nominal value of
2.4kΩ sets the LNA2 current to 1.6mA. External RF bypassing is
required. The trace length between the bypass caps and the pin should
be minimized. Connect ground sides of caps directly to ground.
RF input to LNA2. This pin is internally DC-biased and, if it is connected to a device with DC present, should be DC-blocked with a
capacitor suitable for the frequency of operation.
6
LNA2 OUT
LNA output pin. This is an open-collector output. In normal operation,
this pin is externally cascaded with pin 8 (MIX IN).
7
GND
8
MIX IN
9
IF+
Ground connection. For best performance, keep traces physically short
and connect directly to ground plane.
Mixer RF input pin. This pin requires a DC path to ground. In normal
operation, this pin is externally cascaded with pin 6 (LNA2 OUT). The
external match ensures a conjugate match between pin 6 and pin 8
while providing a DC path to ground for pin 8 and a DC-block between
pin 8 and pin 6.
IF output pin. The output is balanced. A current combiner external network performs a differential to single-ended conversion and sets the
output impedance. There must be a DC path from VCC to this pin. This
is normally achieved with the current combiner network. A DC blocking
cap must be present if the IF filter input has a DC path to ground.
LNA2 IN
LNA2 OUT
FRONT-ENDS
8
10
11
IFLO IN
12
VCC1
13
14
GND
LNA2 BYP
8-36
Same as pin 9, except complementary output.
Mixer LO single-ended input. The pin is internally DC-blocked. External
matching sets impedance.
IF+
IF-
See pin 9.
LO IN
Supply voltage for LO buffer. External RF bypassing is required. The
trace length between the bypass caps and the pin should be minimized.
Connect ground sides of caps directly to ground.
This pin is connected to the ground plane.
Logic control for LNA2 gain. A logic high (>2.4V) places LNA2 in the
high gain mode. A logic low (<0.3V) place LNA2 in the bypass mode.
32 kΩ
LNA2 BYP
Rev A5 010717
RF2469
Preliminary
Pin
15
16
Function
LNA1 BYP
ENABLE
17
VCC1
18
VCC1
19
LNA1 IN
20
GND
Pkg
Base
GND
Description
Logic control for LNA1 gain. A logic high (>2.4V) places LNA1 in the
high gain mode. A logic low (<0.3V) place LNA1 in the bypass mode.
A logic control for mixer and LO buffer. A logic high (>2.4V) turn the
mixer and LO buffer on. A logic low (<0.3V) disable the mixer and LO
buffer.
Supply voltage for the mixer. An external resistor is place in series with
this pin to adjust the mixer current. A nominal value of 1000Ω set the
mixer current to ~10mA. External RF bypassing is required. The trace
length between the bypass caps and the pin should be minimized. Connect ground sides of caps directly to ground.
Supply voltage for IC. External RF bypassing is required. The trace
length between the bypass caps and the pin should be minimized. Connect ground sides of caps directly to ground.
RF input to LNA1. This pin is internally DC-biased and, if it is connected to a device with DC present, should be DC-blocked with a
capacitor suitable for the frequency of operation.
Interface Schematic
32 kΩ
LNA1 BYP
32 kΩ
ENABLE
LNA1 IN
Ground connection. For best performance, keep traces physically short
and connect directly to ground plane.
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with multiple vias.
FRONT-ENDS
8
Rev A5 010717
8-37
RF2469
Preliminary
LNA1, LNA2 and Mixer Application Schematic
(RF=2140MHz, IF=190MHz)
VCC
VCC
LNA1 IN
VCC
10 nF
DNI
330 pF
0.5 pF
1000
Ω
10 pF
ENABLE
10 pF
27 nH
20
LNA1 OUT
19
18
17
16
1
2
10 nF
VCC
10 pF
1.1
kΩ
10 nF
VCC
2.4
kΩ
10 pF
Logic
Control
LNA1 BYP
14
LNA2 BYP
3
13
4
12
5
7
8
9
LO IN
500 Ω
C2
3.0 pF
1.0 pF
IF SAW
C3*
IF OUT
C1
5 pF
FRONT-ENDS
3.0 pF
10
MIX IN
8
VCC
11
6
10 nF
15
R
4.7
kΩ
C1
5pF
L2*
L4
VCC
L1
100 nH
VCC
L3
C4
10 pF
10 nF
C5
LNA2 OUT and MIX IN matching network need
to be determined. (L3, L4, C4, and C5)
LNA2 OUT
8-38
MIX IN
* See output interface network of the mixer to
determine L2 and C3.
Rev A5 010717
RF2469
Preliminary
LNA1, LNA2 Cascade with Mixer Application Schematic
(RF=2140MHz, IF=190MHz)
VCC
VCC
LNA1 IN
VCC
10 nF
330 pF
0.5 pF
1000
Ω
10 pF
ENABLE
10 pF
27 nH
20
LNA1 OUT
19
18
17
16
1
2
10 nF
10 pF
1.1
kΩ
10 nF
VCC
2.4
kΩ
10 pF
LNA1 BYP
14
LNA2 BYP
3
13
4
12
5
VCC
11
3.0 pF
6
10 nF
7
8
9
10
LO IN
MIX IN
500 Ω
C2
3.0 pF
1.0 pF
C3*
IF SAW
8
IF OUT
C1
5 pF
R
4.7
kΩ
C1
5 pF
L2*
10 nH
VCC
5 pF
L1
100 nH
15 nH
VCC
FRONT-ENDS
VCC
Logic
Control
15
10 pF
10 nF
*See output interface network of the
mixer to determine L2 and C3.
Rev A5 010717
8-39
RF2469
Preliminary
Output Interface Network of the Mixer
L1, C1, C2, and R form a current combiner which performs a differential to single-ended conversion at the IF frequency
and sets the output impedance. In most cases, the resonance frequency is independent of R and can be set according to
the following equation:
1
f IF = ----------------------------------------------------------L1
2π ------ ( C 1 + 2C 2 + C EQ )
2
Where CEQ is the equivalent stray capacitance and capacitance looking into pins 9 and 10. An average value to use for
CEQ is 2.5pF.
R can then be used to set the output impedance according to the following equation:
1 –1
1
R = æ --------------------- – ------ö
è 4 ⋅ R OUT R Pø
where ROUT is the desired output impedance and RP is the parasitic equivalent parallel resistance of L1.
8
C2 should first be set to 0 and C1 should be chosen as high as possible, while maintaining an RP of L1 that allows for the
desired ROUT. If the self-resonant frequencies of the selected C1 produce unsatisfactory linearity performance, their values may be reduced and compensated for by including C2 capacitor with a value chosen to maintain the desired FIF frequency.
FRONT-ENDS
L2 and C3 serve dual purposes. L2 serves as an output bias choke, and C3 serves as a series DC block.
In addition, L2 and C3 may be chosen to form an impedance matching network if the input impedance of the IF filter is
not equal to ROUT. Otherwise, L2 is chosen to be large (suggested 120nH) and C3 is chosen to be large (suggested
22nF) if a DC path to ground is present in the IF filter, or omitted if the filter is DC-blocked.
8-40
Rev A5 010717
RF2469
Preliminary
LNA P1dB Compression Point
For large signal input, this type of LNA will not have a fixed DC bias current. The LNA will tend to self-bias when the input
signal level starts increasing above small signal conditions. This particular characteristic will move the DC bias current to
a higher DC bias current. Obviously, increasing the bias current will increase the linearity of the LNA.
To accurately measure the P1dB, the measurement technique must force the bias current in the LNA to be a constant,
while preserving the collector output voltage of the LNA. In order to due this, a separate supply voltage must be used for
the bias voltage of the LNA (pin 3) and the open collector supply (pin 1). As the input signal level is increased, the bias
voltage must be dropped while monitoring the DC current in the LNA to ensure that it remains constant. Incidentally, the
P1dB compression measured with this technique is consistent with the standard approximation relating P1dB to IIP3
(i.e., Input P1dB=IIP3(dBm)-10). Since the IIP3 measurements are done under small signal conditions (the input tones
are low power levels), this approximation provides a good figure for P1dB under a constant DC bias condition. For the
RF2469, with an IIP3 of approximately +8dBm, the Input P1dB is approximately -2dBm.
However, for many applications, forcing the bias current in the LNA to be constant is not a practical solution. Leaving the
LNA to self-bias will not produce any damage to the part and the P1dB performance under this condition will be:
Frequency
(MHz)
2140
Gain
(dB)
10.5
Input
P1dB
5.25
Output
P1dB
14.92
LNA Current
(mA)
~23
FRONT-ENDS
8
Rev A5 010717
8-41
RF2469
Preliminary
Evaluation Board Schematic
(RF=2140MHz, IF=190MHz)
(Download Bill of Materials from www.rfmd.com.)
VCC1
J5
LNA1 IN
50 Ω µstrip
VCC1
C26
330 pF
VCC1
C1
10 nF
P1-1
1
ENABLE
P1-2
2
LNA1 BYP
P1-3
3
LNA2 BYP
P2-1
P2-3
CON3
R5
1000
Ω
C25
DNI
50 Ω µstrip
C2
10 pF
P2
P1
C27
0.5 pF
C24
DNI
1
VCC2
2
GND
3
VCC1
CON3
C23
DNI
ENABLE
L1
27 nH
J1
LNA1 OUT
50 Ω µstrip
20
50 Ω µstrip
C3
10 pF
19
18
17
16
1
2
Logic
Control
3
VCC1
R1
1.1
kΩ
C4
10 nF
C5
10 pF
8
FRONT-ENDS
J2
MIX IN
R2
2.4
kΩ
C6
10 nF
4
C9
1.0 pF
VCC1
C21
DNI
11
7
8
9
50 Ω µstrip
R3
0Ω
50 Ω µstrip
50 Ω µstrip
C14
5 pF
50 Ω µstrip
C15
3 pF
R4
4.7
kΩ
L4
100 nH
L2
15 nH
8-42
C11
DNI
50 Ω µstrip
J4
LO IN
500 Ω
C19
7 pF
50 Ω µstrip
C18
5 pF
50 Ω µstrip
J3
IF OUT
L5
120 nH
C17
10 pF
L3
10 nH
C16
10 nF
VCC1
C10
DNI
C22
3.0 pF
2469400-
50 Ω µstrip
50 Ω µstrip
Typical Board Losses:
LNA1_OUT = 0.22 dB @ 2140 MHz
LNA1_IN = 0.23 dB @2140 MHz
MIX_IN = 0.21 dB @ 2140 MHz
IF_OUT = 0.03 dB @ 190 MHz
C20
DNI
10
50 Ω µstrip
C8
10 nF
50 Ω µstrip
LNA2 BYP
12
6
C7
10 pF
LNA1 BYP
14
13
5
VCC1
15
C12
5 pF
C13
DNI
VCC2
Rev A5 010717
RF2469
Preliminary
Evaluation Board Layout
Board Size 2.0” x 2.0”
Board Thickness 0.031”, Board Material FR-4, Multi-Layer
Assembly
Top
8
Rev A5 010717
Back
FRONT-ENDS
Power Plane
8-43
RF2469
Preliminary
LNA1
LNA1
(Low Gain Mode)
(High Gain Mode)
11.6
0.0
Gain, -30º
Gain, 25º
Gain, 85º
11.4
-0.5
-1.0
Gain (dB)
Gain (dB)
11.2
-1.5
11.0
10.8
10.6
-2.0
Gain, -30º
Gain, 25º
10.4
Gain, 85º
-2.5
10.2
2.7
2.8
2.9
3.0
3.1
3.2
2.7
3.3
2.8
2.9
VCC (V)
3.0
3.1
3.2
3.3
VCC (V)
LNA1
LNA1
(Low Gain Mode)
(High Gain Mode)
3.5
2.5
3.0
2.0
Noise Figure (dB)
Noise Figure (dB)
2.5
2.0
1.5
1.5
1.0
1.0
NF, -30º
NF, -30º
NF, 25º
0.5
NF, 25º
0.5
NF, 85º
NF, 85º
0.0
0.0
2.7
2.8
2.9
3.0
3.1
3.2
3.3
2.7
2.8
2.9
VCC (V)
3.0
3.1
3.2
3.3
VCC (V)
LNA1
LNA1
(Low Gain Mode)
(High Gain Mode)
16.0
31.0
29.0
14.0
27.0
12.0
IIP3 (dBm)
25.0
IIP3 (dBm)
FRONT-ENDS
8
23.0
10.0
8.0
21.0
6.0
19.0
IIP3, -30º
IIP3, -30º
IIP3, 25º
17.0
IIP3, 25º
IIP3, 85º
4.0
IIP3, 85º
15.0
2.0
2.7
2.8
2.9
3.0
VCC (V)
8-44
3.1
3.2
3.3
2.7
2.8
2.9
3.0
3.1
3.2
3.3
VCC (V)
Rev A5 010717
RF2469
Preliminary
Total Current
Total Current
(LNA1BYP=LNA2BYP=EN=0)
(LNA1BYP=LNA2BYP=EN=1)
9.5
40.0
35.0
9.0
30.0
8.5
ICC (mA)
ICC (mA)
25.0
8.0
7.5
20.0
15.0
7.0
10.0
Icc, -30º
6.5
Icc, -30º
Icc, 25º
Icc, 25º
5.0
Icc, 85º
Icc, 85º
6.0
0.0
2.7
2.8
2.9
3.0
VCC (V)
3.1
3.2
3.3
2.7
2.8
2.9
3.0
3.1
3.2
3.3
VCC (V)
FRONT-ENDS
8
Rev A5 010717
8-45
RF2469
Preliminary
Mixer/LNA2, Low Gain Mode (LNA2BYP=0),
Mixer/LNA2, Low Gain Mode (LNA2BYP=0),
LO @ -10dBm
LO @ -10dBm
8.0
12.0
7.0
10.0
6.0
8.0
IIP3 (dBm)
Gain (dB)
5.0
6.0
4.0
3.0
4.0
2.0
Gain, -30º
IIP3, -30º
Gain, 25º
2.0
IIP3, 25º
1.0
Gain, 85º
IIP3, 85º
0.0
0.0
2.7
2.8
2.9
3.0
3.1
3.2
2.7
3.3
2.8
2.9
VCC (V)
Mixer/LNA2, Low Gain Mode (LNA2BYP=0),
3.1
3.2
3.3
Mixer/LNA2 IF, Low Gain Mode (LNA2BYP=0),
LO @ -10dBm
LO @ -10dBm
11.5
27.0
11.0
25.0
8
10.5
Noise Figure (dB)
IIP2 (dBm)
23.0
21.0
19.0
10.0
9.5
9.0
IIP2, -30º
NF, -30º
IIP2, 25º
IIP2, 85º
17.0
8.5
NF, 25º
NF, 85º
15.0
8.0
2.7
2.8
2.9
3.0
3.1
3.2
2.7
3.3
2.8
2.9
VCC (V)
3.0
3.1
3.2
3.3
VCC (V)
Mixer/LNA2, High Gain Mode (LNA2BYP=1),
Mixer/LNA2, High Gain Mode (LNA2BYP=1),
LO @ -10dBm
LO @ -10dBm
24.0
0.0
23.0
-1.0
22.0
-2.0
21.0
-3.0
IIP3 (dBm)
Gain (dB)
FRONT-ENDS
3.0
VCC (V)
20.0
19.0
18.0
IIP3, -30º
IIP3, 25º
IIP3, 85º
-4.0
-5.0
-6.0
17.0
-7.0
Gain, -30º
16.0
-8.0
Gain, 25º
Gain, 85º
15.0
-9.0
2.7
2.8
2.9
3.0
VCC (V)
8-46
3.1
3.2
3.3
2.7
2.8
2.9
3.0
3.1
3.2
3.3
VCC (V)
Rev A5 010717
RF2469
Preliminary
Mixer/LNA2, High Gain Mode (LNA2BYP=1),
Mixer/LNA2, High Gain Mode (LNA2BYP=1),
LO @ -10dBm
LO @ -10dBm
17.0
6.0
IIP2, -30º
IIP2, 25º
16.0
5.5
IIP2, 85º
NF, -30º
Noise Figure (dB)
IIP2 (dBm)
15.0
14.0
13.0
5.0
NF, 25º
NF, 85º
4.5
4.0
12.0
3.5
11.0
10.0
3.0
2.7
2.8
2.9
3.0
3.1
3.2
3.3
2.7
2.8
2.9
VCC (V)
3.0
3.1
3.2
3.3
VCC (V)
Mixer/LNA2 LO to IF Leakage
Mixer/LNA2, High Gain Mode (LNA2BYP=1),
(LNA2BYP=1)
-25.0
21.0
-27.0
20.5
-29.0
20.0
-31.0
19.5
-33.0
19.0
VCC @ 2.78V
8
Gain, 25º
-35.0
-37.0
FRONT-ENDS
Gain, 85º
Gain (dB)
LO to IF Leakage (dB)
Gain, -30º
18.5
18.0
Isolation, -30º
Isolation, 25º
Isolation, 85º
-39.0
17.5
-41.0
17.0
-43.0
16.5
-45.0
2.7
2.8
2.9
3.0
3.1
3.2
16.0
-10.0
3.3
-9.0
-8.0
Mixer/LNA2 IF, High Gain Mode (LNA2BYP=1),
-6.0
-5.0
-4.0
-3.0
Mixer/LNA2 IF, High Gain Mode (LNA2BYP=1),
VCC=2.78V
0.0
-7.0
LO (dBm)
VCC (V)
VCC=2.78V
22.0
IIP3, -30º
IIP3, 25º
-2.0
20.0
IIP3, 85º
18.0
IIP2 (dBm)
IIP3 (dBm)
-4.0
-6.0
16.0
-8.0
14.0
-10.0
12.0
IIP2, -30º
IIP2, 25º
IIP2, 85º
-12.0
-10.0
-9.0
-8.0
-7.0
-6.0
LO (dBm)
Rev A5 010717
-5.0
-4.0
-3.0
10.0
-10.0
-9.0
-8.0
-7.0
-6.0
-5.0
-4.0
-3.0
LO (dBm)
8-47
RF2469
Preliminary
Low Current Configuration
External resistors can set different bias currents for LNA1 (pin 3), LNA2 (pin 4, also called the preamplifier of the mixer),
and mixer (pin 17). Customers have the flexibility to choose the most suitable bias current, and therefore the performance, of the IC. The charts on the following page reflect different bias currents for the RF2469.
The currents were calculated using the following equations.
LNA1 current (R1)=Total Current (LNA1=EN=1, LNA2=0)-Total Current (EN=1, LNA1=LNA2=0)+1.6
1.6 is the bypass current of LNA1
Mixer/LNA2 current (R2)=Total Current (LNA1=0, LNA2=EN=1)-Total Current (LNA1=LNA2=0, EN=1)+1.4+10.2
1.4 is the bypass current of LNA2; 10.2 is the mixer (LO buffer included)
Mixer Only current (R5)=Total Current (EN=LNA2=1, LNA1=0)-4.5
4.5 is the bypass current of the LNA1 (1.6mA)+LNA2 high mode current (2.9mA)
RFMD chose a low current configuration of the RF2469, by using R1=3kΩ, R2=3.6kΩ, and R5=1kΩ in the evaluation
board, and the following lab results over temperature were obtained.
LNA1 High Mode
Temp
(°C)
FRONT-ENDS
8
Frequency
(MHz)
PIN
VCC
(dBm)
(VDC)
-30
2140
-25
2.78
+25
2140
-25
2.78
+85
2140
-25
2.78
Total Current (mA) is when LNA1BYP=LNA2BYP2=EN =1.
Gain
(dB)
IIP3
(dBm)
Noise Figure
(dB)
Total
Current
+7.97
+8.81
+9.70
-3.78
+2.32
+7.71
+1.72
+1.95
+2.37
+11.33
+12.36
+16.45
Mixer/LNA2 BYP High Mode
Temp
(°C)
Frequency
(MHz)
-30
+25
+85
2140
2140
2140
8-48
PIN
(dBm)
-25
-25
-25
LO Frequency
(MHz)
2330
2330
2330
PIN LO
(dBm)
-10
-10
-10
VCC
(VDC)
2.78
2.78
2.78
Gain
(dB)
IIP3
(dBm)
Noise Figure
(dB)
+18.73
+17.74
+16.67
-8.16
+5.13
-3.66
+3.98
+4.54
+5.19
Rev A5 010717
RF2469
Preliminary
LNA Gain, Noise Figure and IIP3 versus ICC - LNA1 Only
(LNA High Gain)
12.0
Resistor (R1) versus ICC (mA) - LNA Only
(LNA High Gain)
4.0
16.0
14.0
10.0
3.0
10.0
8.0
6.0
6.0
Gain (dB)
NF (dB)
IIP3 (dBm)
4.0
Resistor R1 (k Ω)
8.0
IIP3 (dBm)
Gain and Noise Figure (dB)
12.0
2.0
4.0
1.0
2.0
2.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
-2.0
10.0
0.0
1.0
3.0
5.0
ICC (mA)
7.0
9.0
11.0
ICC (mA)
Mixer Gain, Noise Figure and IIP3 versus ICC -
Resistor (R2) versus ICC - Mixer/LNA2 BYP High
Mixer/LNA2 BYP High (LO=2330MHz @ -10dBm, sweeping R2)
(LO=2330MHz @ -10dBm)
5.0
0.0
20.0
18.0
4.5
8
12.0
Gain (dB)
10.0
NF (dB)
IIP3 (dBm)
8.0
Resistor R2 (k Ω)
-2.0
FRONT-ENDS
4.0
14.0
IIP3 (dBm)
Gain and Noise Figure (dB)
16.0
3.5
3.0
-4.0
6.0
2.5
4.0
2.0
2.0
0.0
11.0
11.5
12.0
12.5
13.0
-6.0
13.5
1.5
11.0
11.5
12.0
12.5
13.0
13.5
ICC (mA)
ICC (mA)
Mixer Gain, Noise Figure and IIP3 versus ICC -
Resistor (R5) versus ICC - Mixer/LNA2 BYP High
Mixer/LNA2 BYP High (LO=2330MHZ @ 019dBm, sweeping R5)
25.0
(LO=2330MHz @ -10dBm)
1.6
0.0
-1.0
1.4
-2.0
NF (dB)
15.0
-4.0
IIP3 (dBm)
-5.0
10.0
-6.0
Resistor R5 (k Ω)
-3.0
Gain (dB)
IIP3 (dBm)
Gain and Noise Figure (dB)
20.0
1.2
1.0
0.8
-7.0
5.0
-8.0
0.6
-9.0
0.0
7.0
8.0
9.0
10.0
11.0
ICC (mA)
Rev A5 010717
12.0
13.0
-10.0
14.0
0.4
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
ICC (mA)
8-49
RF2469
Preliminary
FRONT-ENDS
8
8-50
Rev A5 010717