ETC STB80NF10-T4

STB80NF10

N - CHANNEL 100V - 0.014Ω - 80A I2PAK/D2PAK
LOW Qg STripFET POWER MOSFET
PRELIMINARY DATA
TYPE
STB80NF10
■
■
■
■
■
V DSS
R DS( on )
ID
100 V
< 0.018 Ω
80 A
TYPICAL RDS(on) = 0.014 Ω
EXCEPTIONAL dv/dt CAPABILITY
100% AVALANCHE TESTED
APPLICATION ORIENTED
CHARACTERIZATION
SURFACE-MOUNTING D2PAK (TO-263)
POWER PACKAGE IN TUBE (NO SUFFIX)
OR IN TAPE & REEL (SUFFIX ”T4”)
DESCRIPTION
This
MOSFET
series
realized
with
STMicroelectronics unique STripFET process has
specifically been designed to minimize input
capacitance and gate charge. It is therefore
suitable as primary switch in advanced
high-efficiency, high-frequency isolated DC-DC
converters for
Telecom and
Computer
applications. It is also intended for any
applications with low gate drive requirements.
3
12
I2PAK
TO-262
(Suffix ”-1”)
3
1
D2PAK
TO-263
(Suffix ”T4”)
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
HIGH-EFFICIENCY DC-DC CONVERTERS
■ UPS AND MOTOR CONTROL
■
ABSOLUTE MAXIMUM RATINGS
Symb ol
V DS
V DGR
VGS
Value
Unit
Drain-source Voltage (VGS = 0)
Parameter
100
V
Drain- gate Voltage (R GS = 20 kΩ)
100
V
G ate-source Voltage
± 20
V
80
A
ID
Drain Current (continuous) at Tc = 25 oC
ID
Drain Current (continuous) at Tc = 100 o C
50
A
Drain Current (pulsed)
320
A
I DM (•)
P tot
dv/dt( 1 )
E AS ( 2 )
T st g
o
T otal Dissipation at Tc = 25 C
210
W
Derating Factor
1.4
W /o C
9
V/ns
245
mJ
Peak Diode Recovery voltage slope
Single Pulse Avalanche Energy
Storage Temperature
Max. Operating Junction Temperature
Tj
(•) Pulse width limited by safe operating area
( 2) starting Tj = 25 oC, ID =80A , VDD = 50V
April 2000
-65 to 175
o
C
175
o
C
(1) I SD ≤ 80 A, di/dt ≤ 300A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMA
1/7
STB80NF10
THERMAL DATA
R thj -case
R thj -amb
Tl
Thermal Resistance Junction-case
Max
Thermal Resistance Junction-ambient
Max
Maximum Lead Temperature F or Soldering Purpose
o
0.71
62.5
300
o
C/W
C/W
o
C
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)
OFF
Symbo l
V (BR)DSS
Parameter
Drain-source
Breakdown Voltage
Test Con ditions
I D = 250 µA
V GS = 0
I DSS
V DS = Max Rating
Zero Gate Voltage
Drain Current (V GS = 0) V DS = Max Rating
IGSS
Gate-body Leakage
Current (VDS = 0)
Min.
Typ.
Max.
100
Unit
V
T c =125 oC
V GS = ± 20 V
1
10
µA
µA
± 100
nA
ON (∗)
Symbo l
Parameter
Test Con ditions
ID = 250 µA
V GS(th)
Gate Threshold Voltage V DS = V GS
R DS(on)
Static Drain-source On
Resistance
V GS = 10 V
I D(o n)
On State Drain Current
V DS > ID(o n) x R DS(on )ma x
V GS = 10 V
Min.
Typ.
Max.
Unit
2
3
4
V
0.014
0.018
Ω
ID = 40 A
80
A
DYNAMIC
Symbo l
g f s (∗)
C iss
C os s
C rss
2/7
Parameter
Test Con ditions
Forward
Transconductance
V DS > ID(o n) x R DS(on )ma x
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V DS = 25 V
f = 1 MHz
I D =40 A
V GS = 0
Min.
Typ.
Max.
Unit
20
S
4300
600
240
pF
pF
pF
STB80NF10
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbo l
Parameter
Test Con ditions
Min.
Typ.
Max.
Unit
t d(on)
tr
Turn-on Delay T ime
Rise Time
V DD = 50 V
I D = 40 A
R G = 4.7 Ω
V GS = 10 V
(Resistive Load, see fig. 3)
40
145
ns
ns
Qg
Q gs
Q gd
Total G ate Charge
Gate-Source Charge
Gate-Drain Charge
V DD = 80 V ID = 80 A V GS = 10 V
140
23
51
nC
nC
nC
SWITCHING OFF
Symbo l
Parameter
Test Con ditions
Min.
Typ.
Max.
Unit
t d(of f)
tf
Turn-off Delay T ime
Fall T ime
V DD = 27 V
I D = 40 A
V GS = 10 V
R G = 4.7 Ω
(Resistive Load, see fig. 3)
134
115
ns
ns
t d(of f)
tf
tc
Off-voltage Rise T ime
Fall T ime
Cross-over Time
Vclamp = 80 V
I D = 80 A
V GS = 10 V
R G = 4.7 Ω
(Induct ive Load, see fig. 5)
111
125
185
ns
ns
ns
SOURCE DRAIN DIODE
Symbo l
Parameter
Test Con ditions
ISD
I SDM (•)
Source-drain Current
Source-drain Current
(pulsed)
V SD (∗)
Forward On Voltage
I SD = 80 A
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I SD = 80 A
di/dt = 100 A/µs
T j = 150 o C
V DD = 50 V
(see test circuit, fig. 5)
t rr
Q rr
I RRM
Min.
Typ.
V GS = 0
Max.
Unit
80
320
A
A
1.5
V
155
ns
850
nC
11
A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operatingarea
3/7
STB80NF10
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
4/7
STB80NF10
TO-262 (I2PAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
4.4
4.6
0.173
0.181
A1
2.49
2.69
0.098
0.106
B
0.7
0.93
0.027
0.036
B2
1.14
1.7
0.044
0.067
C
0.45
0.6
0.017
0.023
C2
1.23
1.36
0.048
0.053
D
8.95
9.35
0.352
0.368
e
2.4
2.7
0.094
0.106
E
10
10.4
0.393
0.409
L
13.1
13.6
0.515
0.531
L1
3.48
3.78
0.137
0.149
L2
1.27
1.4
0.050
0.055
E
e
B
B2
C2
A1
A
C
A
L1
L2
D
L
P011P5/E
5/7
STB80NF10
TO-263 (D2PAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.4
4.6
0.173
0.181
A1
2.49
2.69
0.098
0.106
B
0.7
0.93
0.027
0.036
B2
1.14
1.7
0.044
0.067
C
0.45
0.6
0.017
0.023
C2
1.21
1.36
0.047
0.053
D
8.95
9.35
0.352
0.368
E
10
10.4
0.393
0.409
G
4.88
5.28
0.192
0.208
L
15
15.85
0.590
0.624
L2
1.27
1.4
0.050
0.055
L3
1.4
1.75
0.055
0.068
D
C2
A2
A
C
DETAIL”A”
DETAIL ”A”
A1
B2
E
B
G
L2
L
L3
P011P6/E
6/7
STB80NF10
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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