ETC STD12NF06LT4

STD12NF06L
N-CHANNEL 60V - 0.08 Ω - 12A IPAK/DPAK
STripFET II POWER MOSFET
TYPE
STD12NF06L
■
■
■
■
■
■
VDSS
RDS(on)
ID
60 V
< 0.1 Ω
12 A
TYPICAL RDS(on) = 0.08 Ω
EXCEPTIONAL dv/dt CAPABILITY
LOW GATE CHARGE
LOW THRESHOLD DRIVE
THROUGH-HOLE IPAK (TO-251) POWER
PACKAGE IN TUBE (SUFFIX “-1”)
SURFACE-MOUNTING DPAK (TO-252)
POWER PACKAGE IN TAPE & REEL
(SUFFIX “T4”)
3
3
1
2
1
IPAK
TO-251
(Suffix “-1”)
DPAK
TO-252
(Suffix “T4”)
DESCRIPTION
This Power MOSFET is the latest development of
STMicroelectronis unique ”Single Feature Size ” stripbased process. The resulting transistor shows extremely
high packing density for low on-resistance, rugged
avalanche characteristics and less critical alignment
steps
therefore
a
remarkable
manufacturing
reproducibility.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■ HIGH CURRENT, HIGH SWITCHING SPEED
■ SOLENOID AND RELAY DRIVERS
■ MOTOR CONTROL, AUDIO AMPLIFIERS
■ DC-DC & DC-AC CONVERTERS
■ AUTOMOTIVE ENVIRONMENT
ABSOLUTE MAXIMUM RATINGS
Symbol
V DS
V DGR
VGS
Parameter
Unit
60
V
Drain-gate Voltage (RGS = 20 kΩ)
60
V
± 16
V
Gate- source Voltage
ID
Drain Current (continuous) at TC = 25°C
12
A
ID
Drain Current (continuous) at TC = 100°C
8.5
A
IDM(•)
Ptot
Drain Current (pulsed)
48
A
Total Dissipation at TC = 25°C
30
W
Derating Factor
0.2
W/°C
dv/dt (1)
Peak Diode Recovery voltage slope
15
V/ns
E AS (2)
Single Pulse Avalanche Energy
100
mJ
-55 to 175
°C
Tstg
Tj
Storage Temperature
Operating Junction Temperature
(•) Pulse width limit ed by safe operating area.
June 2002
.
Value
Drain-source Voltage (VGS = 0)
(1) ISD ≤12A, di/dt ≤200A/µs, VDD=40V, Tj ≤ TJMAX
(2) Starting Tj = 25 oC, IAR = 6A, VDD= 30V
1/10
STD12NF06L
THERMAL DATA
Rthj-case
Rthj-amb
Tl
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
Max
Max
Typ
°C/W
°C/W
°C
5
100
275
ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified)
OFF
Symbol
Parameter
Test Conditions
Drain-source
Breakdown Voltage
ID = 250 µA, VGS = 0
IDSS
Zero Gate Voltage
Drain Current (V GS = 0)
VDS = Max Rating
VDS = Max Rating TC = 100°C
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ± 16 V
V(BR)DSS
Min.
Typ.
Max.
60
Unit
V
1
10
µA
µA
±100
nA
Max.
Unit
2.5
V
0.08
0.10
0.10
0.12
Ω
Ω
Typ.
Max.
Unit
ON (*)
Symbol
Parameter
Test Conditions
VGS(th)
Gate Threshold Voltage
VDS = VGS
I D = 250 µA
R DS(on)
Static Drain-source On
Resistance
VGS = 10 V
VGS = 5 V
ID = 6 A
ID = 6 A
Min.
Typ.
1
DYNAMIC
Symbol
2/10
Parameter
gfs (*)
Forward Transconductance
C iss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Test Conditions
VDS =25 V
ID = 6 A
VDS = 25V, f = 1 MHz, VGS = 0
Min.
7
S
350
75
30
pF
pF
pF
STD12NF06L
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
td(on)
tr
Turn-on Delay Time
Rise Time
VDD = 30 V
ID = 6 A
VGS = 4.5 V
R G = 4.7 Ω
(Resistive Load, Figure 3)
10
35
Qg
Qgs
Q gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 48 V ID = 12 A VGS= 5V
7.5
2.5
3.0
10
nC
nC
nC
Typ.
Max.
Unit
ns
ns
SWITCHING OFF
Symbol
td(off)
tf
Parameter
Turn-off Delay Time
Fall Time
Test Conditions
Min.
VDD = 30 V
ID = 6 A
VGS = 4.5 V
RG = 4.7 Ω
(Resistive Load, Figure 3)
20
13
ns
ns
SOURCE DRAIN DIODE
Symbol
Parameter
ISD
ISDM (•)
Source-drain Current
Source-drain Current (pulsed)
VSD (*)
Forward On Voltage
ISD = 12 A
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 12 A
di/dt = 100A/µs
T j = 150°C
VDD = 16 V
(see test circuit, Figure 5)
trr
Qrr
IRRM
Test Conditions
Min.
Typ.
V GS = 0
50
67
2.5
Max.
Unit
12
48
A
A
1.5
V
ns
nC
A
(*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(•)Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
3/10
STD12NF06L
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/10
STD12NF06L
Normalized Gate Threshold Voltage vs Temperature
Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics
.
.
.
5/10
STD12NF06L
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/10
STD12NF06L
TO-251 (IPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A3
0.7
1.3
0.027
0.051
B
0.64
0.9
0.025
0.031
B2
5.2
5.4
0.204
0.212
B3
0.85
B5
0.033
0.3
0.012
B6
0.95
0.037
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
15.9
16.3
0.626
0.641
L
9
9.4
0.354
0.370
L1
0.8
1.2
0.031
0.047
L2
0.8
1
0.031
0.039
A1
C2
A3
A
C
H
B
B3
=
1
=
2
G
=
=
=
E
B2
=
3
B5
L
D
B6
L2
L1
0068771-E
7/10
STD12NF06L
TO-252 (DPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.64
0.9
0.025
0.035
B2
5.2
5.4
0.204
0.212
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
9.35
10.1
0.368
0.397
L2
0.8
L4
0.031
0.6
1
0.023
0.039
A1
C2
A
H
A2
C
DETAIL ”A”
L2
D
=
1
=
G
2
=
=
=
E
=
B2
3
B
DETAIL ”A”
L4
0068772-B
8/10