CS8151 5.0 V, 100 mA Low Dropout Linear Regulator with Watchdog, RESET, and Wake Up The CS8151 is a precision 5.0 V, 100 mA micro–power voltage regulator with very low quiescent current (400 µA typical at 200 µA load). The 5.0 V output is accurate within ±2% and supplies 100 mA of load current with a typical dropout voltage of 400 mV. Microprocessor control logic includes Watchdog, Wake Up and RESET. This unique combination of low quiescent current and full microprocessor control makes the CS8151 ideal for use in battery operated, microprocessor controlled equipment. The CS8151 Wake Up function brings the microprocessor out of Sleep mode. The microprocessor in turn, signals its Wake Up status back to the CS8151 by issuing a Watchdog signal. The Watchdog logic function monitors an input signal (WDI) from the microprocessor. The CS8151 responds to the falling edge of the Watchdog signal which it expects at least once during each wake–up period. When the correct Watchdog signal is received, a falling edge is issued on the wake–up signal line. RESET is independent of VIN and operates correctly to an output voltage as low as 1.0 V. A RESET signal is issued in any of three situations. During power up the RESET is held low until the output voltage is in regulation. During operation if the output voltage shifts below the regulation limits, the RESET toggles low and remains low until proper output voltage regulation is restored. And finally, a RESET signal is issued if the regulator does not receive a Watchdog signal within the Wake Up period. The RESET pulse width, Wake Up signal frequency, and Wake Up delay time are all set by one external capacitor CDelay. The regulator is protected against short circuit, over voltage, and thermal runaway conditions. The device can withstand 74 volt peak transients, making it suitable for use in automotive environments. Features • 5.0 V ± 2%/100 mA Output Voltage • Micropower Compatible Control Functions – Wake Up – Watchdog – RESET • Low Dropout Voltage: 400 mV @ 100 mA • Low Sleep Mode Quiescent Current (400 µA Typ) • Protection Features – Thermal Shutdown – Short Circuit – 74 V Peak Transient Capability – Reverse Transient (–50 V) • Internally Fused Leads in DIP–16 and SO–16L Packages Semiconductor Components Industries, LLC, 2001 March, 2001 – Rev. 8 http://onsemi.com TO–220 SEVEN LEAD T SUFFIX CASE 821E 1 7 TO–220 SEVEN LEAD TVA SUFFIX CASE 821J 1 D2PAK 7–PIN DPS SUFFIX CASE 936H 1 7 DIP–16 NF SUFFIX CASE 648 16 1 SO–16L DWF SUFFIX CASE 751G 16 1 ORDERING INFORMATION Device Package Shipping CS8151YT7 TO–220* STRAIGHT 50 Units/Rail CS8151YTVA7 TO–220* VERTICAL 50 Units/Rail CS8151YDPS7 D2PAK* 50 Units/Rail CS8151YDPSR7 D2PAK* 750 Tape & Reel CS8151YNF16 DIP–16 25 Units/Rail CS8151YDWF16 SO–16L 46 Units/Rail CS8151YDWFR16 SO–16L 1000 Tape & Reel *7 Lead/Pin. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 9 of this data sheet. 1 Publication Order Number: CS8151/D CS8151 PIN CONNECTIONS TO–220 SEVEN LEAD DIP–16 1 Tab = GND Pin 1. VOUT 2. VIN 3. WDI 4. GND 5. Wake Up 6. RESET 7. Delay 1 D2PAK 7–PIN SO–16L 16 1 NC Delay NC NC NC RESET Wake Up NC NC 16 Delay RESET Wake Up GND GND GND GND GND GND GND GND NC Sense WDI NC GND Sense WDI NC VOUT VIN VOUT VIN 1 VOUT VIN Current Source (Circuit Bias) Delay Overvoltage Shutdown VOUT Current Limit Sense Timing Circuit Wake Up Circuit + – Watchdog Circuit WDI Internally connected on TO–220 and D2PAK Wake Up Sense Error Amplifier Thermal Shutdown Falling Edge Detector Bandgap Reference VOUT RESET RESET Circuit GND Figure 1. Block Diagram http://onsemi.com 2 CS8151 ABSOLUTE MAXIMUM RATINGS* Rating Value Unit Power Dissipation Internally Limited – Output Current (VOUT, RESET, Wake Up) Internally Limited – Reverse Battery –15 V Peak Transient Voltage (60 V Load Dump @ VIN = 14 V) +74 V Maximum Negative Transient (t < 2.0 ms) –50 V ESD Susceptibility (Human Body Model) 2.0 kV ESD Susceptibility (Machine Model) 200 V Logic Inputs/Outputs –0.3 to +6.0 V Storage Temperature Range –55 to +150 °C 260 peak 230 peak °C °C Lead Temperature Soldering Wave Solder (through hole styles only) Note 1. Reflow (SMD styles only) Note 2. 1. 10 seconds max. 2. 60 seconds max above 183°C *The maximum package power dissipation must be observed. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ 125°C, –40°C ≤ TJ ≤ 150°C, 6.0 V ≤ VIN ≤ 26 V, 100 µA ≤ IOUT ≤ 100 mA, C2 = 47 µF (ESR < 8.0 Ω), CDelay = 0.1 µF; unless otherwise specified.) Test Conditions Min Typ Max Unit Output Voltage, VOUT 9.0 V < VIN < 16 V 6.0 V < VIN < 26 V, 0 < IOUT < 100 mA 4.90 4.85 5.0 5.0 5.10 5.15 V V Dropout Voltage (VIN – VOUT) IOUT = 100 mA IOUT = 100 µA – – 400 100 600 150 mV mV Load Regulation VIN = 14 V, 100 µA < IOUT < 100 mA – 10 50 mV Line Regulation IOUT = 1.0 mA, 6.0 V < VIN < 26 V – 10 50 mV Ripple Rejection 7.0 V < VIN < 17 V @ f = 120 Hz, IOUT = 100 mA 60 75 – dB Current Limit VOUT = 4.5 V 100 250 – mA 150 180 210 °C Characteristic Output Section Thermal Shutdown – Overvoltage Shutdown VOUT < 1.0 V 50 56 62 V Quiescent Current IOUT = 200 µA (Sleep) IOUT = 50 mA IOUT = 100 mA (Wake Up) – – – 0.4 4.0 12 0.75 – 20 mA mA mA Reverse Current VOUT = 5.0 V, VIN = 0 V – 1.0 1.5 mA RESET Threshold High (RTH) RTH VOUT Increasing VOUT – 0.3 – VOUT – 0.04 V Threshold Low (RTL) RTL VOUT Decreasing 4.5 4.7 4.91 V Hysteresis RTH – RTL 150 200 250 mV Output Low 1.0 V < VOUT RTL, IOUT = 25 µA – 0.2 0.8 V Output High IOUT = 25 µA, VOUT > RTH 3.8 4.2 5.1 V Current Limit RESET = 0 V, VOUT > VRTH (Sourcing) RESET = 5.0 V, VOUT > 1.0 V (Sinking) 0.025 0.1 0.5 12 1.30 80 mA mA Delay Time POR Mode 3.0 5.0 7.0 ms http://onsemi.com 3 CS8151 ELECTRICAL CHARACTERISTICS (continued) (–40°C ≤ TA ≤ 125°C, –40°C ≤ TJ ≤ 150°C, 6.0 V ≤ VIN ≤ 26 V, 100 µA ≤ IOUT ≤ 100 mA, C2 = 47 µF (ESR < 8.0 Ω), CDelay = 0.1 µF; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Threshold High – – 1.4 2.0 V Threshold Low – 0.8 1.3 – V Hysteresis – 25 100 – mV Watchdog Input Input Current 0 < WDI < 6.0 V –10 0 +10 µA Pulse Width 50% WDI Falling Edge to 50% WDI Rising Edge and 50% WDI Rising Edge to 50% WDI Falling Edge (see Figures 2, 3, and 4) 5.0 – – µs Wake Up Period See Figure 2. 30 40 50 ms Wake Up Duty Cycle Nominal See Figure 4. 40 50 60 % RESET High to Wake Up Rising Delay Time 50% RESET Rising Edge to 50% Wake Up Edge (see Figures 2, 3, and 4 ) 15 20 25 ms Wake Up Response to Watchdog Input 50% WDI Falling Edge to 50% Wake Up Falling Edge – 2.0 10 µs Wake Up Response to RESET 50% RESET Falling Edge to 50% Wake Up Falling Edge, VOUT = 5.0 V → 4.5 V – 2.0 10 µs Output Low IOUT = 25 µA (Sinking) – 0.2 0.8 V Output High IOUT = 25 µA (Sourcing) 3.8 4.2 5.1 V Current Limit Wake Up = 5.0 V Wake Up = 0 V 0.025 0.5 1.0 – 7.0 3.5 mA mA Wake Up Output PACKAGE PIN DESCRIPTION PACKAGE PIN # TO–220 & D2PAK DIP–16 SO–16L PIN SYMBOL 1 8 8 VOUT 2 9 9 VIN Supply voltage to the IC. 3 11 11 WDI CMOS/TTL compatible input lead. The Watchdog function monitors the falling edge of the incoming signal. 4 4, 5, 12, 13 4, 5, 6, 12, 13 GND Ground connection. 5 14 14 Wake Up CMOS/TTL compatible output consisting of a continuously generated signal used to Wake Up the microprocessor from sleep mode. 6 15 15 RESET CMOS/TTL compatible output lead RESET goes low whenever VOUT drops by more than 6.0% from nominal, or during the absence of a correct watchdog signal. 7 16 16 Delay Input lead from timing capacitor for RESET and Wake Up signal. – 7 7 Sense Kelvin connection which allows remote sensing of the output voltage for improved regulation. If remote sensing is not required, connect to VOUT. http://onsemi.com 4 FUNCTION Regulated output voltage 5.0 V ± 2%. CS8151 TIMING DIAGRAMS VIN RESET Wake Up Duty Cycle = 50% Wake Up WDI VOUT POR RESET High to Wake Up Delay Time Power Up Sleep Mode Normal Operation with Varying Watchdog Signal Figure 2. Power Up, Sleep Mode and Normal Operation VIN RESET Delay Time RESET Wake Up WDI VOUT POR RESET High to Wake Up Delay Time Wake Up Period RESET High to Wake Up Delay Time Figure 3. Error Condition: Watchdog Remains Low and a RESET Is Issued RESET Wake Up Period Wake Up WDI RTL VOUT Watchdog Pulse Width Power Down POR POR Watchdog Pulse Width Figure 4. Power Down and Restart Sequence http://onsemi.com 5 CS8151 DEFINITION OF TERMS techniques such that the average chip temperature is not significantly affected. Load Regulation: The change in output voltage for a change in load current at constant chip temperature. Quiescent Current: The part of the positive input current that does not contribute to the positive load current. The regulator ground lead current. Ripple Rejection: The ratio of the peak–to–peak input ripple voltage to the peak–to–peak output ripple voltage. Current Limit: Peak current that can be delivered to the output. Dropout Voltage: The input–output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100mV from the nominal value obtained at 14V input, dropout voltage is dependent upon load current and junction temperature. Input Voltage: The DC voltage applied to the input terminals with respect to ground. Line Regulation: The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse CIRCUIT DESCRIPTION Functional Description The first falling edge of the watchdog signal causes the Wake Up to go low within 2.0 µs (typ) and remain low until the next Wake Up cycle (see Figure 5). Other watchdog pulses received within the same cycle are ignored (Figures 2, 3, and 4). During power up, RESET is held low until the output voltage is in regulation. During operation, if the output voltage shifts below the regulation limits, the RESET toggles low and remains low until proper output voltage regulation is restored. After the RESET delay, RESET returns high. The Watchdog circuitry continuously monitors the input watchdog signal (WDI) from the microprocessor. The absence of a falling edge on the Watchdog input during one Wake Up cycle will cause a RESET pulse to occur at the end of the Wake Up cycle (see Figure 3). The Wake Up output is pulled low during a RESET regardless of the cause of the RESET. After the RESET returns high, the Wake Up cycle begins again (see Figure 3). The RESET pulse width, Wake Up signal frequency and RESET high to Wake Up delay time are all set by one external capacitor CDelay. Wake Up Period = (4 × 105)CDelay RESET Delay Time = (5 × 104)CDelay RESET High to Wake Up Delay Time = (2 × 105)CDelay Capacitor temperature coefficient and tolerance as well as the tolerance of the CS8151 must be taken into account in order to get the correct system tolerance for each parameter. To reduce the drain on the battery a system can go into a low current consumption mode when ever its not performing a main routine. The Wake Up signal is generated continuously and is used to interrupt a microcontroller that is in sleep mode. The nominal output is a 5.0 volt square wave with a duty cycle of 50% at a frequency that is determined by a timing capacitor, CDelay. When the microprocessor receives a rising edge from the Wake Up output, it must issue a watchdog pulse and check its inputs to decide if it should resume normal operations or remain in the sleep mode. Wake Up WDI Wake Up Response to WDI Figure 5. Wake Up Response to WDI RESET Wake Up Wake Up Response to RESET Figure 6. Wake Up Response to RESET (Low Voltage) http://onsemi.com 6 CS8151 APPLICATION NOTES Output Stage Protection The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provide this information. The value for the output capacitor C2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator The output stage is protected against overvoltage, short circuit and thermal runaway conditions (see Figure 7). If the input voltage rises above the overvoltage shutdown threshold (e.g. load dump), the output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage transients. Should the junction temperature of the power device exceed 180°C (typ) the power transistor is turned off. Thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the IC. > 50 V VIN VOUT IOUT Load Dump Short Circuit Thermal Shutdown Figure 7. Typical Circuit Waveforms for Output Stage Protection Stability Considerations The output or compensation capacitor C2 (see Figure 8) helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. VIN VOUT C1* 0.1 µF CS8151 RRST C2** 10 µF RESET *C1 required if regulator is located far from the power supply filter. **C2 required for stability. Figure 8. Test and Application Circuit Showing Output Compensation http://onsemi.com 7 CS8151 performance. Most good quality aluminum electrolytic capacitors have a tolerance of ±20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. IQ Figure 9. Single Output Regulator with Key Performance Parameters Labeled In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. (1) where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated: Heat Sinks Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RΘJA: RJA RJC RCS RSA (2) Battery VOUT C1 VCC C2 Microprocessor CS8151 WDI CDelay RESET I/O RESET CDelay GND (3) where: RΘJC = the junction–to–case thermal resistance, RΘCS = the case–to–heatsink thermal resistance, and RΘSA = the heatsink–to–ambient thermal resistance. RΘJC appears in the package section of the data sheet. Like RΘJA, it too is a function of package type. RΘCS and RΘSA are functions of the package type, heatsink and the interface between them. These values appear in heatsink data sheets of heatsink manufacturers. The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. VIN VOUT } Control Features The maximum power dissipation for a single output regulator (Figure 9) is: RJA 150°C TA PD SMART REGULATOR VIN Calculating Power Dissipation In a Single Output Linear Regulator PD(max) (VIN(max) VOUT(min))IOUT(max) VIN(max)IQ IOUT IIN Wake Up I/O Figure 10. Application Diagram http://onsemi.com 8 CS8151 MARKING DIAGRAMS TO–220 SEVEN LEAD T SUFFIX CASE 821E D2PAK 7–PIN DPS SUFFIX CASE 936H TO–220 SEVEN LEAD TVA SUFFIX CASE 821J DIP–16 NF SUFFIX CASE 648 16 16 CS8151 AWLYYWW CS8151 AWLYWW CS8151 AWLYWW CS8151 AWLYWW CS8151 AWLYYWW 1 1 1 1 SO–16L DWF SUFFIX CASE 751G 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week PACKAGE DIMENSIONS TO–220 SEVEN LEAD T SUFFIX CASE 821E–04 ISSUE C Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.003 (0.076) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. A G B D L DIM A B C D G H J K L M Q U V U K OPTIONAL CHAMFER M M SEATING PLANE C H V M M J http://onsemi.com 9 INCHES MIN MAX 0.600 0.610 0.386 0.403 0.170 0.180 0.028 0.037 0.045 0.055 0.088 0.102 0.018 0.026 1.028 1.042 0.355 0.365 5 NOM 0.142 0.148 0.490 0.501 0.045 0.055 MILLIMETERS MIN MAX 15.24 15.49 9.80 10.23 4.32 4.56 0.71 0.94 1.15 1.39 2.24 2.59 0.46 0.66 26.11 26.47 9.02 9.27 5 NOM 3.61 3.75 12.45 12.72 1.15 1.39 CS8151 TO–220 SEVEN LEAD TVA SUFFIX CASE 821J–02 ISSUE A –T– C B –Q– E W A U H F L K M D 0.356 (0.014) M N S 7 PL T Q M G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM A B C D E F G H J K L M N Q R S U W INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.023 0.037 0.045 0.055 0.540 0.555 0.050 BSC 0.570 0.595 0.014 0.022 0.785 0.800 0.322 0.337 0.073 0.088 0.090 0.115 0.146 0.156 0.289 0.304 0.164 0.179 0.460 0.475 3° MILLIMETERS MIN MAX 14.22 14.99 9.77 10.54 4.06 4.82 0.58 0.94 1.14 1.40 13.72 14.10 1.27 BSC 14.48 15.11 0.36 0.56 19.94 20.32 8.18 8.56 1.85 2.24 2.28 2.91 3.70 3.95 7.34 7.72 4.17 4.55 11.68 12.07 3° R J D2PAK 7–PIN DPS SUFFIX CASE 936H–01 ISSUE O –T– SEATING PLANE B M U C E 8 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS B AND M. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAX. V DIM A B C D E F G H J K M N U V A 1 2 34 5 6 7 K F G D H 7 PL 0.13 (0.005) M T B J M N http://onsemi.com 10 INCHES MIN MAX 0.326 0.336 0.396 0.406 0.170 0.180 0.026 0.036 0.045 0.055 0.058 0.078 0.050 BSC 0.100 0.110 0.018 0.025 0.204 0.214 0.055 0.066 0.000 0.004 0.256 REF 0.305 REF MILLIMETERS MIN MAX 8.28 8.53 10.05 10.31 4.31 4.57 0.66 0.91 1.14 1.40 1.41 1.98 1.27 BSC 2.54 2.79 0.46 0.64 5.18 5.44 1.40 1.68 0.00 0.10 6.50 REF 7.75 REF CS8151 DIP–16 NF SUFFIX CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C DIM A B C D F G H J K L M S L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 SO–16L DWF SUFFIX CASE 751G–03 ISSUE B A D 9 1 8 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. 16X M 14X e T A S B h X 45 DIM A A1 B C D E e H h L S L A 0.25 B B SEATING PLANE A1 H E 0.25 8X M B M 16 C T MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0 7 PACKAGE THERMAL DATA Parameter TO–220 7 LEAD D2PAK 7–Pin DIP–16 SO–16L Unit RΘJC Typical 1.8 1.8 15 18 °C/W RΘJA Typical 50 10–50* 50 75 °C/W *Depending on thermal properties of substrate. RΘJA = RΘJC + RΘCA. http://onsemi.com 11 CS8151 SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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