2.5V 12BIT 80MSPS DAC
GENERAL DESCRIPTION
dac1391x
FEATURES
The dac1391x is a CMOS 12-bit D/A converter for
general applications. The maximum conversion rate of
dac1391x is 80MSPS and supply voltage is 2.5V.
•
•
•
•
•
•
•
•
TYPICAL APPLICATIONS
• Graphic display
• General purpose high-speed
Resolution : 12 Bit
Differential Linearity Error : ± 1.0 LSB
Integral Linearity Error : ± 4.0 LSB
Maximum Conversion Rate : 80MSPS
BGR (Internal / External)
Power Down Mode
Analog Output Range : 0.0 ~ 1.024V
Power Supply : 2.5V Single
FUNCTIONAL BLOCK DIAGRAM
AVDD25A
AVSS25A
AVDD25D
AVSS25D
Decoder
D[11:0]
1st
Latch
2nd
Latch
Buffer
CK12 PDN
CK11
PDB
BGR
CK11
CLK
PD
Clock
Generator
AVBB25A
AVBB25D
COMP
+
PDB
PDB
Amp
_
IOUTB
SIN
Slot
Cell
VREF
CK12
PDN
IOUT
Current
Cell
Matrix
CM
Block
COMP
SIN
PDB
VREF
IREF
Ver 1.0 (April 2002)
This datasheet is a preliminary version. No responsibility is
assumed by SEC for its use nor for any infringements of patents
or other rights of third parties that may result from its use. The
content of this datasheet is subject to change without any notice.
SAMSUNG ELECTRONICS Co. LTD
COMP SIN
dac1391x
2.5V 12BIT 80MSPS DAC
CORE PIN DESCRIPTION
NAME
I/O TYPE
I/O PAD
PIN DESCRIPTION
D[11:0]
DI
pmicc_abb
Digital Input Data (12 bit)
D[11] : MSB , D[0] : LSB
CLK
DI
pmicc_abb
Clock for DAC
PD
DI
pmicc_abb
Power Down Control
VREF
AI
pmia_abb
Voltage Reference (BGR Output)
IREF
AI
pmia_abb
External Resistor Connection
IOUT
AO
pmoa_abb
Analog Output
IOUTB
AO
pmoa_abb
Complementary Analog Output
COMP
AO
pmoa_abb
External Capacitor Connection
SIN
AO
pmoa_abb
Cascode Current Source Gate Node
AVDD25A
AP
AVSS25A
AG
vsstm_abb
Analog Ground (0.0V)
AVBB25A
AG
vbbm_abb
Analog Sub Bias (0.0V)
AVDD25D
DP
AVSS25D
DG
vsstm_abb
Digital Ground (0.0V)
AVBB25D
DG
vbbm_abb
Digital Sub Bias (0.0V)
I/O TYPE ABBR.
•
•
•
•
•
•
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Digital Output
AB : Analog Bidirectional
DB : Digital Bidirectional
•
•
•
•
AP
DP
AG
DG
:
:
:
:
Analog Power
Digital Power
Analog Ground
Digital Ground
vdd25tm_abb Analog Power (+2.5V)
vdd25tm_abb Digital Power (+2.5V)
CORE CONFIGURATION
AVDD25A AVSS25A AVDD25D AVSS25D AVBB25A AVBB25D
IOUT
D[11:0]
dac1391x
CLK
IOUTB
PD
VREF
SEC ASIC
IREF
COMP
2 / 13
SIN
ANALOG
dac1391x
2.5V 12BIT 80MSPS DAC
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
Value
Unit
Supply Voltage
AVDD25A , AVDD25D
3.3
V
Digital Input Voltage
D[11:0]
AVSS25D to AVDD25D
V
Operating Temperature Range
Topr
-40 to 85
°C
Storage Temperature Range
Tstg
-45 to 125
°C
NOTES :
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.
Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition
value is applied with the other values kept within the following operating conditions and function operation under any
of these conditions is not implied.
2. All voltages are measured with respect to VSS(AVSS25A or AVSS25D or AVBB25A or AVBB25D)
unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Typ
Max
Unit
Supply Voltage
AVDD25A - AVSS25A
AVDD25D - AVSS25D
2.25
2.5
2.75
V
Supply Voltage Difference
AVDD25A - AVDD25D
-0.1
0.0
0.1
V
Digital Input 'Low' Voltage
Digital Input 'High' Voltage
VIL
VIH
0.7×VDD
-
0.3×VDD
-
V
Output Load Resistance
RLOAD
-
50
-
Ω
Operating Temperature
Topr
-40
-
85
°C
NOTE :
1. It is strongly recommended that to avoid power latch-up all the supply pins (AVDD25A , AVDD25D)
be driven from the same source.
2. Digital Input : VDD → AVDD25D
SEC ASIC
3 / 13
ANALOG
dac1391x
2.5V 12BIT 80MSPS DAC
DC ELECTRICAL CHARACTERISTICS
(Converter Specifications : AVDD25A=AVDD25D=2.5V, AVSS25A=AVSS25D=AVBB25A=AVBB25D=0V,
PD=Low, Top=25°C, R(IREF)=3.84kΩ, Load Resistance=50Ω unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Unit
Resolution
Bit
-
-
10
Bits
Differential Linearity Error
DLE
-
-
±1
LSB
Integral Linearity Error
ILE
-
-
±4
LSB
RLOAD
-
50
-
Ω
CLOAD
-
10
-
pF
Output Loading
Monotonicity
-
Maximum Output Compliance
VOC
-
-
1.2
V
Full Scale Current
IFS
-
20.49
-
mA
External Reference Voltage
VREF
-
1.23
-
V
Zero Scale Error1
VZSE
-
±5
-
mV
Full Scale Voltage Error2
VFSE
-
±5
-
mV
Maximum Output Voltage
VoMAX
-
1.024
-
V
LSB Size
VLSB
-
250.24
-
uV
NOTE
Guaranteed
Conditions
-
VoMAX = VOUT(D[11:0]=High)
VLSB = VoMAX / 4095
1 : VZSE=VOUT(D[11:0]=Low) − 0.0V
2 : VFSE=VOUT(D[11:0]=High) − {V(IREF)/[R(IREF)×64]}×4095×50Ω
SEC ASIC
4 / 13
ANALOG
dac1391x
2.5V 12BIT 80MSPS DAC
AC ELECTRICAL CHARACTERISTICS
(Converter Specifications : AVDD25A=AVDD25D=2.5V, AVSS25A=AVSS25D=AVBB25A=AVBB25D=0V,
PD=Low, Top=25°C, R(IREF)=3.84kΩ, Load Resistance=50Ω , Load Cap.=10pF unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Unit
Conditions
Maximum Conversion Rate
fC
-
80
-
Dynamic Supply Current
Ivdd1
-
24
-
mA
Ivdd1 = IAVDD25A + IAVDD25D
Data Rate = 80MHz
Dynamic Supply Current
(Power Down Mode)
Ivdd2
-
-
10
uA
Ivdd2 = IAVDD18A , fCLK = 80MHz
PD=High
Analog Output Delay
Td
-
2.0
-
ns
fCLK = 80MHz
Data : All LOW → All HIGH
Analog Output Rise Time
Tr
-
2.0
-
ns
fCLK = 80MHz
Data : All LOW → All HIGH
Analog Output Fall Time
Tf
-
2.0
-
ns
fCLK = 80MHz
Data : All HIGH → All LOW
Analog Output
Settling Time (< ±0.025%)
Tset
-
12.5
-
ns
fCLK = 80MHz
Data : All LOW → All HIGH
Data Input Setup Time
Ts
-
2
-
ns
fCLK = 80MHz
Data Input Hold Time
Th
-
2
-
ns
fCLK = 80MHz
Power Down On Time
Ton
-
4
-
us
PD=High
Power Down Off Time
Toff
-
4
-
ms
PD=Low
Clock and Data Feedthrough
FDTHR
-
-30
-
dB
fCLK = 80MHz
Spurious Free
Dynamic Range
SFDR
-
-50
-
dB
fCLK = 80MHz
Glitch Impulse
GI
-
50
-
pVsec
fCLK = 80MHz
MSPS fCLK = 80MHz
NOTES
1. The above parameters are all simulation results.
2. Clock and data feed through is a function of the amount of overshoot and undershoot on the digital inputs.
Settling time does not include clock and data feedthrough. Glitch impulse include clock and data feedthrough.
SEC ASIC
5 / 13
ANALOG
dac1391x
2.5V 12BIT 80MSPS DAC
TIMING DIAGRAM
Ts
Digital Input
(D[11:0])
Th
D(n-1)
D(n)
D(n+1)
D(n+2)
D(n+3)
VO(n)
VO(n+1)
VO(n+2)
CLK
1/2 Clock delay
Analog Output
(VO)
VO(n-2)
VO(n-1)
Td
Digital Input
(D[11:0])
000000000000
111111111111
000000000000
CLK
(< ± 0.025%)
90%
Analog Output
(VO)
td
10%
tset
tr
tf
1. Output delay is measured from the 50% point of the falling edge of clock(CLK) to the full scale transition.
2. Settling time is measured from the 50% point of full scale transition to the output remaining
within ±0.025% of full scale voltage.
3. Output rise/fall time is measured between the 10% and 90% points of full scale transition.
4. Power down on time (Ton) is measured from the 50% point of full scale transition
to the output remaining within ±1% of full scale voltage. (0.0V ± VoMAX×0.01)
5. Power down off time (Toff) is measured from the 50% point of full scale transition
to the output remaining within ±1% of full scale voltage. (VoMAX ± VoMAX×0.01)
SEC ASIC
6 / 13
ANALOG
dac1391x
2.5V 12BIT 80MSPS DAC
FUNCTIONAL DESCRIPTION
1. This is 12bit 80MSPS DAC(digital-to-analog data converter) and uses segment architecture for 6bits of
MSB side, binary-weighted architecture for 6bits of LSB side. It contains of first latch block,
decoder block, second latch block, AMP block ,BGR block, clock generator, CM(current mirror) block and
current cell block.
This core uses reference current to decide the 1LSB current size by dividing the reference current by 64times.
So the reference current must be constant and the switch's physical size can be constant by using OPA block
with high DC gain. The most significant block of this core is current cell block so it must maintain the
uniformity at each cell, therefore layout designer must care of the matching characteristics on current cells and
CM block, and more than 90% of supply current is dissipated at current cell block and AMP block.
To adjust the full current output, you must decide the "R(IREF)" resistor value(connected to IREF pin) and
"VREF" voltage value(connected to VREF pin). Its voltage output can be obtained by connecting RLOAD
(connected to IOUT pin).
2. The voltage output of dac1391x are decided by R(IREF), RLOAD, and V(IREF).
11
V(IREF)
VO =
×∑
R(IREF) × 32 i = 0
(2 × D[i])× R
i
LOAD
V(IREF) is almost same with VREF.
SEC ASIC
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ANALOG
HOST
DSP
CORE
12
12
MUX
TEST PATH
12
50Ω
Digital Digital
Power Ground
RO , ROB
2.5V GND
3.84kΩ
Analog Analog
Power Ground
RSET
2.5V GND
0.1uF CERAMIC CAPACITOR
Cc
RO
Analog
Ground
GND
Cc
Cc
VO
VOB
10uF TANTALUM CAPACITOR
Ct
IOUT
IOUTB
ROB
Analog
Ground
GND
DESCRIPTION
Ct
Ct
COMP
dac1391x
IREF
Cc
3.3V
RSET
(=3.84kΩ)
GND
Analog
Power
SIN
AVDD25A AVSS25A AVBB25A AVDD25D AVSS25D AVBB25D
D[11:0]
CLK
PD
VREF
1.23V
Analog
Ground
(If the output voltage of VREF is not 1.23V, please connect VREF
to 1.23V external voltage source.)
LOCATION
ANALOG
8 / 13
SEC ASIC
dac1391x
2.5V 12BIT 80MSPS DAC
CORE EVALUATION GUIDE
dac1391x
2.5V 12BIT 80MSPS DAC
PHANTOM CELL INFORMATION
SIN
COMP
AVDD25A
AVSS25A
AVBB25A
IREF
VREF
CLK
PD
D[11]
D[10]
dac1391x
D[9]
D[8]
D[7]
D[6]
IOUT
D[5]
D[4]
IOUTB
D[3]
D[2]
AVSS25D
AVDD25D
D[0]
AVBB25D
D[1]
Pin Name
Property
Pin Usage
D[11:0]
DI
Internal / External
CLK
DI
Internal / External
PD
DI
Internal / External
IOUT
AO
External
IOUTB
AO
External
VREF
AI
External
IREF
AI
External
CCOMP
AO
External
SIN
AO
External
AVDD25A
AP
External
AVSS25A
AG
External
AVBB25A
AG
External
AVDD25D
DP
External
AVSS25D
DG
External
AVBB25D
DG
External
Pin Layout Guide
1. Digital input signal lines(D[11:0]) must have
same length to reduce propagation delay.
1. Analog output lines (IOUT & IOUTB) and IREF
must be wide metal to reduce voltage drop of metal lines.
2. Analog signal should not be crossed by any digital signals
and not run next to digital signals to minimize capacitive
coupling between the two signals.
1. It is recommended that you use thick analog power
metal. When connected to PAD, the path should be kept
as short as possible.
2. Digital power and analog power are separately used.
1. When the core block is connected to other blocks, it must be double guard-ring using N-well and
P+ active to remove the substrate and coupling noise.
In that case, the power metal should be connected to PAD directly.
2. The Bulk power is used to reduce the influence of substrate noise.
SEC ASIC
9 / 13
ANALOG
dac1391x
2.5V 12BIT 80MSPS DAC
PACKAGE CONFIGURATION
L1
Cc
Ct
+
L2
1
AVBB25D
NC
48
2
AVSS25D
NC
47
3
AVDD25D
NC
46
4
NC
NC
45
5
NC
NC
44
D[11]
6
D[11]
AVBB25A
43
D[10]
7
D[10]
AVSS25A
42
D[9]
8
D[9]
NC
41
D[8]
9
D[8]
NC
40
D[7]
10
D[7]
AVDD25A
39
D[6]
11
D[6]
NC
38
D[5]
12
D[5]
NC
37
D[4]
13
D[4]
NC
36
D[3]
14
D[3]
IREF
35
0.0V
(AVSS25A)
D[2]
15
D[2]
VREF
34
1.23V
D[1]
16
D[1]
NC
33
D[0]
17
D[0]
SIN
32
18
NC
COMP
31
CLK
19
CLK
NC
30
PD
20
PD
NC
29
21
NC
IOUT
28
IOUT
22
NC
IOUTB
27
IOUTB
23
NC
NC
26
24
NC
NC
25
(VSS)
0.0V
Cc
Ct
DAC1391X
+
2.5V
(VDD)
RSET(=3.84kΩ)
Cc
2.5V
(AVDD25A)
(0.0V in normal operation)
RO
RO
0.0V
(AVSS25A)
SEC ASIC
LOCATION
DESCRIPTION
Ct
10uF TANTALUM CAPACITOR
Cc
0.1uF CERAMIC CAPACITOR
L1~L2
FERRITE BEAD ( 0.1mh )
RO
50 Ω
10 / 13
ANALOG
dac1391x
2.5V 12BIT 80MSPS DAC
PACKAGE PIN DESCRIPTION
NAME
PIN NO
I/O TYPE
PIN DESCRIPTION
AVBB25D
1
DG
Digital Sub Bias (0.0V)
AVSS25D
2
DG
Digital Ground (0.0V)
AVDD25D
3
DP
Digital Power (+2.5V)
D[11:0]
6 ~ 17
DI
Digital Input Data (12 bit)
CLK
19
DI
Clock for DAC
PD
20
DI
Power Down Control
IOUTB
27
AO
Complementary Analog Output
IOUT
28
AO
Analog Output
COMP
31
AO
External Capacitor Connection
SIN
32
AO
Cascode Current Source Gate Node
VREF
35
AI
Voltage Reference (BGR Output)
IREF
36
AI
External Resistor Connection
AVDD25A
39
AP
Analog Power (+2.5V)
AVSS25A
42
AG
Analog Ground (0.0V)
AVBB25A
43
AG
Analog Sub Bias (0.0V)
NC
4,5,18,21,
22,23,24
DO
No Connection
NC
25,26,29,30,
32,33,36,37,
38,40,41,44,
45,46,47,48
AO
No Connection
I/O TYPE ABBR.
•
•
•
•
•
•
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Digital Output
AB : Analog Bidirectional
DB : Digital Bidirectional
•
•
•
•
AP :
DP :
AG :
DG :
Analog Power
Digital Power
Analog Ground
Digital Ground
SEC ASIC
11 / 13
ANALOG
dac1391x
2.5V 12BIT 80MSPS DAC
PC BOARD LAYOUT CONSIDERATION
1. PC Board Considerations
To minimize noise on the power lines and the ground lines, the digital inputs
need to be shielded and decoupled. This trace length between groups
of VDD (AVDD25A,AVDD25D) and VSS (AVSS25A,AVSS25D) pins should be as short as possible
so as to minimize inductive ringing.
2. Supply Decoupling and Planes
For the decoupling capacitor between the power line and the ground line, 0.1uF
ceramic capacitor is used in parallel with a 10uF tantalum capacitor.
The digital power plane(AVDD25D) and analog power plane(AVDD25A) are connected
through a ferrite bead, and also the digital ground plane(AVSS25D) and the analog
ground plane(AVSS25A). This ferrite bead should be located within 3inches of
the DAC1391X. The analog power plane supplies power to the DAC1391X of
the analog output pin and related devices.
SEC ASIC
12 / 13
ANALOG
dac1391x
2.5V 12BIT 80MSPS DAC
FEEDBACK REQUEST
We appreciate your interest in out products.
If you have further questions, please specify in the attached form.
Thank you very much.
DC / AC ELECTRICAL CHARACTERISTIC
Characteristics
Min
Typ
Max
Unit
Supply Voltage
V
Power dissipation
mW
Resolution
Bits
Analog Output Voltage
V
Operating Temperature
°C
Output Load Capacitor
pF
Output Load Resistor
kΩ
Integral Non-Linearity Error
LSB
Differential Non-Linearity Error
LSB
Maximum Conversion Rate
MHz
Remarks
VOLTAGE OUTPUT DAC
Reference Voltage TOP
BOTTOM
V
Analog Output Voltage Range
Digital Input Format
V
Binary Code or 2's Complement Code
CURRENT OUTPUT DAC
-
Analog Output Maximum Current
mA
Analog Output Maximum Signal Frequency
kHz
Reference Voltage
V
External Resistor for Current Setting(RSET)
kΩ
Pipeline Delay
sec
Do you want to Power down mode?
Do you want to Internal Reference Voltage(BGR)?
Which do you want to serial input data type or parallel input data type?
Do you need 3.3V and 5V power supply in your system?
SEC ASIC
13 / 13
ANALOG
dac1391x
2.5V 12BIT 80MSPS DAC
HISTORY CARD
Version
Ver 1.0
Date
Modified Items
Comments
02.04.23 Preliminary Version
SEC ASIC
ANALOG