3.3V 10BIT 2MSPS DAC
GENERAL DESCRIPTION
dac1264x_ra
FEATURES
The dac1264x_ra is a CMOS 10Bit D/A converter for
general application. This digital to analog converter has
a R-string structure.
Its settling time is 400ns (Typical value).
TYPICAL APPLICATIONS
• Hard Disk Drive (HDD)
• Motor Control Systems
• General Applications
•
•
•
•
•
•
•
•
Resolution : 10Bit
Differential Linearity Error : ± 1.0 LSB
Integral Linearity Error : ± 2.0 LSB
Settling Time : 400ns
Low Power Consumption : 3.0mA
Power Down Mode
Operation Temperature Range : 0ºC ~ 70ºC
Power Supply : 3.3V Single
: 1.8V (for Digital Input)
FUNCTIONAL BLOCK DIAGRAM
AVDD33A AVSS33A AVDD33D AVSS33D
D[9:0]
10
Level
Shifter
N
AVBB
AVDD18D
M
Slot Cell
Two Decoders
VTOP
VRT
VHALF
VRB
VBOT
PWDNB
Doutn
Doutm
2N
2M
_
3.3V
OP
AMP
2.65V
1.65V
R-String
+
0.65V
0.0V
Level
Shifter
Ver 1.7 (May 2002)
No responsibility is assumed by SEC for its use nor for any
infringements of patents or other rights of third parties that may
result from its use. The content of this datasheet is subject to
change without any notice.
SAMSUNG ELECTRONICS Co. LTD
VOUT
dac1264x_ra
3.3V 10BIT 2MSPS DAC
CORE PIN DESCRIPTION
NAME
I/O
TYPE
I/O PAD
PIN DESCRIPTION
D[9:0]
DI
picc_abb
Digital Input Data (10bit : 1.8V)
D[9] : MSB , D[0] : LSB
PWDNB
DI
picc_abb
Power Down (Active Low : 1.8V)
VHALF
AB
phia_abb
External Voltage Reference (1.65V)
VTOP
AB
phia_abb
Voltage Reference Top (3.3V)
VBOT
AB
phia_abb
Voltage Reference Bottom (0.0V)
VRT
AB
phia_abb
Internal Voltage Reference Top (2.65V)
VRB
AB
phia_abb
Internal Voltage Reference Bottom (0.65V)
VOUT
AO
phoa_abb
Analog Voltage Output
AVDD33D
AP
vdd3t_abb Analog Power (+3.3V)
AVSS33D
AG
vss3t_abb
AVDD33A
DP
vdd3t_abb Digital Power (+3.3V)
AVSS33A
DG
vss3t_abb
AVBB
AG
vbb3t_abb Analog Sub Bias (0.0V)
AVDD18D
DP
vdd1t_abb Digital Power (+1.8V)
I/O TYPE ABBR.
•
•
•
•
•
•
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Digital Output
AB : Analog Bidirectional
DB : Digital Bidirectional
•
•
•
•
AP
DP
AG
DG
:
:
:
:
Analog Power
Digital Power
Analog Ground
Digital Ground
Analog Ground (0.0V)
Digital Ground (0.0V)
CORE CONFIGURATION
AVDD33A AVSS33A AVDD33D AVSS33D
AVBB
AVDD18D
dac1264x_ra
D[9:0]
VOUT
PWDNB
VHALF
SEC ASIC
VTOP VBOT
VRT
VRB
2 / 9
ANALOG
dac1264x_ra
3.3V 10BIT 2MSPS DAC
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
Value
Unit
VDD (AVDD33A,AVDD33D)
4.5
V
Analog Output Voltage
VOUT
AVSS33A to AVDD33A
V
Digital Input Voltage
D[9:0]
AVSS33D to AVDD18D
V
Reference Voltage
VRT
VRB
AVDD33A
AVSS33A
V
Operating Temperature Range
Topr
0 to 70
°C
Supply Voltage
NOTES :
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.
Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition
value is applied with the other values kept within the following operating conditions and function operation under any
of these conditions is not implied.
2. All voltages are measured with respect to VSS (AVSS33A or AVSS33D or AVBB) unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
AVDD33A - AVSS33A
AVDD33D - AVSS33D
3.15
3.3
3.45
V
AVDD18D - AVSS33D
1.65
1.8
1.95
V
AVDD33A - AVDD33D
-0.1
0.0
0.1
V
Reference Voltage
VRT
VRB
0.0
2.65
0.65
3.3
-
V
Digital Input 'Low' Voltage
Digital Input 'High' Voltage
VIL
VIH
0.7×VDD
-
0.3×VDD
-
V
Operating Temperature
Topr
0
-
70
°C
Characteristics
Supply Voltage
Supply Voltage Difference
NOTE :
1. It is strongly recommended that to avoid power latch-up all the supply pins(AVDD33A,AVDD33D)
be driven from the same source.
2. VDD → AVDD18D
SEC ASIC
3 / 9
ANALOG
dac1264x_ra
3.3V 10BIT 2MSPS DAC
DC ELECTRICAL CHARACTERISTICS
(Converter Specifications : AVDD33D=AVDD33A=3.3V, AVSS33D=AVSS33A=AVBB=0V, AVDD18D=1.8V
PWDNB=High, Top=25°C, VRT=2.65V, VRB=0.65V unless otherwise specified.)
Symbol
Min
Typ
Max
Unit
Bit
-
10
-
Bits
-
Differential Linearity Error
DLE
-1.0
±0.2
+1.0
LSB
-
Integral Linearity Error
ILE
-2.5
±1.6
+2.5
LSB
-
Zero Scale Error1
VZSE
-15
10
+15
mV
VFSE
-15
10
+15
mV
VTOP=3.3V , VRB=0.0V
(VRT and VRB are floated.)
VoMAX
2.633
2.648
2.663
V
VLSB
1.93
1.953
1.97
mV
Characteristics
Resolution
Full Scale Voltage Error
2
Maximum Output Voltage
LSB Size
NOTE
Conditions
VoMAX = VOUT(D[9:0]=High)
VLSB = (VoMAX - VOUT(D[9:0]=Low)) / 1023
1 : VZSE=VOUT(D[9:0]=Low) - VRB
2 : VFSE=VOUT(D[9:0]=High) - {(VRT-VRB) × 1023/1024 + VRB}
AC ELECTRICAL CHARACTERISTICS
(Converter Specifications : AVDD33D=AVDD33A=3.3V, AVSS33D=AVSS33A=AVBB=0V, AVDD18D=1.8V , load cap=25pF
load resistance=5kΩ, Top=25°C, VRT=2.65V, VRB=0.65V unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Unit
Supply Current
(Average Current)
Ivdd1
2
3
4
mA
Ivdd1 = IAVDD33A + IAVDD33D
Data Input : All Low or All High
Supply Current
(Power Down Mode)
Ivdd2
-
-
10
uA
Ivdd2 = IAVDD33A + IAVDD33D
Data Rate = 2MHz
PWDNB=LOW
Reference Current
IVRT
-
0.75
-
mA
Analog Output Delay
Td
35
50
80
ns
Data Rate = 2MHz
Data : All LOW → All HIGH
Analog Output Rise Time
Tr
40
60
100
ns
Data Rate = 2MHz
Data : All LOW → All HIGH
Analog Output Fall Time
Tf
65
103
176
ns
Data Rate = 2MHz
Data : All HIGH → All LOW
Analog Output
Settling Time
Ts
360
400
420
ns
Data Rate = 2MHz
Data : All LOW → All HIGH
Power Down On Time
Ton
-
30
-
ns
PWDNB : HIGH → LOW
Power Down Off Time
Toff
-
300
-
ns
PWDNB : LOW → HIGH
Glitch Energy
GLE
-0.1
0.1
nsV
Data Rate = 2MHz
Data : 0111111111 → 1111111111
Signal-to-Noise and
Distortion Ratio
SNDR
-48
-58
dB
Data Rate = 2MHz
Output Frequency (fout) = 50kHz
SEC ASIC
-56
4 / 9
Conditions
ANALOG
dac1264x_ra
3.3V 10BIT 2MSPS DAC
TIMING DIAGRAM
DATA
0000000000
0000000000
1111111111
1111111111
0000000000
90%
VOUT
DATA
50%
10%
Td
VOUT
Tf
Tr
DATA
50%
0000000000
1111111111
0000000000
± 0.5LSB
VOUT
50%
Ts
PWDNB
50%
50%
Toff
Ton
± 0.5LSB
VOUT
± 0.5LSB
0.0V
1. Output delay measured from the 50% point of the rising edge of input data to the full scale transition.
2. Settling time measured from the 50% point of full scale transition to the output remaining within ±1/2 LSB.
3. Output rise/fall time measured between the 10% and 90% points of full scale transition.
FUNCTIONAL DESCRIPTION
1. The dac1264x_ra has a 10bit R-string block, two decoders, and an OP amp.
2. The digital outputs of two decoders decide the voltage level of R-string block.
VRT − VRB 9
VRstring =
10
∑
2
n= 0
(2 × D[n])+ VRB
n
3. The voltages of VRT and VRB are internally generated by resistor strings.
(VTOP = 3.3V , VBOT = 0.0V then VRT = 2.65V , VRB= 0.65V)
For more accurate operations, you had better connect VRT and VRB with voltage sources
instead of connecting VTOP and VBOT with voltage sources. (VRT = 2.65V , VRB = 0.65V)
4. The VOUT pin is dependent of digital input values.
5. Power Down Mode reduces only analog currents (IAVDD33A) and
reference current (IVRT) is always dissipated.
SEC ASIC
5 / 9
ANALOG
HOST
DSP
CORE
10
10
MUX
TEST PATH
10
Ct
Cc
3.3V GND 3.3V GND
Cc
Ct
Ct
Cc
Ct
1.8V
AVBB AVDD18D
VRT VRB
GND 0.0V GND
Cc
VBOT
dac1264x_ra
AVDD33D AVSS33D AVDD33A AVSS33A
D[9:0]
PWDNB
3.3V
VHALF VTOP
1.65V
LOCATION
DESCRIPTION
Ct
10uF TANTALUM CAPACITOR
Cc
0.1uF CERAMIC CAPACITOR
VOUT
VOUT
ANALOG
6 / 9
SEC ASIC
dac1264x_ra
3.3V 10BIT 2MSPS DAC
CORE EVALUATION GUIDE
dac1264x_ra
3.3V 10BIT 2MSPS DAC
TESTABILITY
Whether you use MUX or the internal logic for testability, it is required to be able to select
the values of digital inputs ( D[9:0] ).
See above figure. Only if it is, you can check the main function. ( Linearity )
For more accurate operations, you had better connect VRT and VRB with voltage sources
instead of connecting VTOP and VBOT with voltage sources.
(VRT = 2.65V , VRB = 0.65V)
SEC ASIC
7 / 9
ANALOG
dac1264x_ra
3.3V 10BIT 2MSPS DAC
PHANTOM CELL INFORMATION
AVSS33A
VHALF
AVDD33A
AVBB
dac1264x_ra
VOUT
AVDD33D
DI
Internal / External
VRT
AB
Internal / External
VRB
AB
Internal / External
VTOP
AB
External
VBOT
AB
External
VOUT
AO
Internal / External
AVDD33A
AP
External
AVSS33A
AG
External
AVDD33D
DP
External
AVSS33D
DG
External
AVBB
AG
External
AVDD18D
DP
External
PWDNB
PWDNB
VRT
Internal / External
VTOP
DI
VRB
D[9:0]
VBOT
Pin Usage
D[9]
Property
D[9]
Pin Name
D[9]
D[9]
D[9]
D[9]
D[9]
D[9]
D[9]
D[9]
AVSS33D
AVDD18D
Pin Layout Guide
1. Digital Input Signal lines must have same length to
reduce propagation delay.
1. Voltage reference lines (VRT / VRB and VTOP / VBOT)
must be wide metal to reduce voltage drop of metal lines.
2. If you use VRT and VRB, VTOP and VBOT may be
disconnected and vice versa.
3. VOUT signal should not be crossed by any signals and
should not run next to digital signals to minimize capacitive
coupling between the two signals.
1. It is recommended that you use thick analog power metal.
When connected to PAD, the path should be kept as short
as possible.
2. Digital power and analog power are separately used.
1. When the core block is connected to other blocks, it must be double guard-ring using N-well and
P+ active to remove the substrate and coupling noise.
In that case, the power metal should be connected to PAD directly.
2. The Bulk power is used to reduce the influence of substrate noise.
SEC ASIC
8 / 9
ANALOG
dac1264x_ra
3.3V 10BIT 2MSPS DAC
FEEDBACK REQUEST
We appreciate your interest in out products.
If you have further questions, please specify in the attached form.
Thank you very much.
DC / AC ELECTRICAL CHARACTERISTIC
Characteristics
Min
Typ
Max
Unit
Supply Voltage
V
Power dissipation
mW
Resolution
Bits
Analog Output Voltage
V
Operating Temperature
°C
Output Load Capacitor
pF
Output Load Resistor
kΩ
Integral Non-Linearity Error
LSB
Differential Non-Linearity Error
LSB
Maximum Conversion Rate
MHz
Remarks
VOLTAGE OUTPUT DAC
Reference Voltage TOP
BOTTOM
V
Analog Output Voltage Range
V
Digital Input Format
Binary Code or 2's Complement Code
CURRENT OUTPUT DAC
-
Analog Output Maximum Current
mA
Analog Output Maximum Signal Frequency
kHz
Reference Voltage
V
External Resistor for Current Setting(RSET)
kΩ
Pipeline Delay
sec
Do you want to Power down mode?
Do you want to Internal Reference Voltage(BGR)?
Which do you want to serial input data type or parallel input data type?
Do you need 3.3V and 5V power supply in your system?
SEC ASIC
9 / 9
ANALOG
dac1264x_ra
3.3V 10BIT 2MSPS DAC
HISTORY CARD
Version
Date
Ver 1.0
00.09
Modified Items
Comments
Preliminary Version
Ver 1.1
01.03.15 Page 1 : block diagram is modified (AVSS33A → AVSS33D)
Ver 1.2
01.03.28
Version Updated
page 8 : °C → kΩ (Output Load Resistor)
Ver 1.3
01.04.12
Version Updated
page 8 : Interal → Internal
Ver 1.4
Version Updated
1.8V pin for digital input is added. (block diagram, symbol,
01.10.05
spec..etc)
Core layout guide is added.
Ver 1.5
01.11.02
Ver 1.6
Version Updated
page 3 : Absolute Maximum Rating is modified.
page 4 : Test result is added.
02.05.13 page 5 : Functional description is modified.
page 6 : Diagram is modified.
page 8 : Diagram is modified.
page 9 : Question is modified.
Version Updated
page 7 : Layout guide is modified.
SEC ASIC
ANALOG