8-BIT 250KSPS SAR ADC ADC_PCI2010_CS2 FEATURES GENERAL DESCRIPTION The adc_pci2010_cs2 is a CMOS 8-bit low supply, low power, successive approximation A/D converter which is composed of auto-zeroing comparator, 8-bit DAC, clock generator, successive approximation register(SAR) and output register. The 8-bit DAC consists of capacitor arrays and resistor strings. The conversion result can be accessed over a parallel interface. The adc_pci2010_cs2 operates with a single +2.5V power supply and the conversion rate is up to 250KSPS. - Resolution: 8-Bit Differential Linearity Error:±0.5 LSB(Max) Integral Linearity Error:±0.75 LSB(Typ) Maximum Conversion Rate: 250KSPS Low Power Consumption: 2.5mW(Typ) Power Supply Voltage: 2.5V(Typ) No Pipeline Delays No Missing Code Guaranteed Internal Voltage Reference Operating Temperature Range: -40ºC~85ºC FUNCTIONAL BLOCK DIAGRAM AVDD25A AVSS25A AVBBA REFT VCOM REFB AVDD25DAVSS25D AVBBD AVDD25O AVSS25O A1 AVDD18D MCO[2:0] INP[7:0] MUX (8:1) 8-Bit DAC COMP INN CONV EOC CONTROLLER SAR CLK SLEEP OUT_REG DO[7:0] Ver 1.0 (July, 2000) This data sheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any notice. SEC ASIC ANALOG ADC_PCI2010_CS2 8-BIT 250KSPS SAR ADC CORE PIN DESCRIPTION NAME I/O TYPE I/O PAD REFT AI pia_abb Reference Top Voltage VCOM AI pia_abb Analog Common Voltage; Reference Middle Voltage REFB AI pia_abb Reference Bottom Voltage AVDD25A AP vdd2t_abb AVBBA AG vbb_abb AVSS25A AG vss2t_abb INP[7:0] AI piar50_abb 8-channel Analog Input(+) INN AI piar50_abb Analog Input(-) (DC 1.25V) MCO[2:0] DI picc_abb Mux Input Control SLEEP DI picc_abb SLEEP; Power Saving Mode (Active High) CLK DI picc_abb Master Clock Input DO[7:0] DO poa_abb Digital Output Data EOC DO poa_abb End of Conversion CONV DI picc_abb Conversion Control Pin (Active High) AVSS25D DG vss2t_abb Digital Ground AVBBD DG vbb_abb AVDD25D DP vdd2t_abb Digital Power AVSS25O DG vss2t_abb Output Buffer Ground AVDD25O DP vdd2t_abb Output Buffer Power AVDD18D DP vdd1t_abb 1.8V Digital Power for Level Shifter ITEST AB - CORE CONFIGURATION PIN DESCRIPTION Analog Power Analog Bulk Analog Ground I/O TYPE ABBR. - AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AP : Analog Power AG : Analog Ground DP : Digital Power DG : Digital Ground - AB : Analog Bidirection - DB : Digital Bidirection Digital Bulk Floating Node; Current Bias Test AVDD25A AVSS25A AVBBA AVDD25D AVSS25D AVBBD AVDD25O AVSS25O MCO[2:0] AVDD18D INP[7:0] INN adc_pci2010_cs2 DO[7:0] REFT VCOM REFB SLEEP SEC ASIC CLK 2 / 10 EOC CONV MIXED ADC_PCI2010_CS2 8-BIT 250KSPS SAR ADC ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit Supply Voltage VDD 3.3 V Analog Input Voltage AIN VSS to VDD V Digital Input Voltage DIN VSS to VDD V VOH, VOL VSS to VDD V REFT/REFB VSS to VDD V Digital Output Voltage Reference Voltage Storage Temperature Range Tstg -45 to 125 ºC Operating Temperature Range Topr -40 to 85 ºC NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model) RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Typ Max Unit 2.3 2.5 - V - V VDD25A1 Supply Voltage VDD25A2 VDD25A3 Reference Voltage Analog Input Voltage Operating Temperature REFT - REFB INP 0.0 INN Toper 1.875 0.625 - 2.5 1.25 -40 - 85 V ºC NOTES It is strongly recommended that all the supply pins (VDD25A1, VDD25A2, VDD25A3) be powered from the same source to avoid power latch-up. Reference voltage can be generated internally. SEC ASIC 3 / 10 MIXED ADC_PCI2010_CS2 8-BIT 250KSPS SAR ADC ANALOG SPECIFICATIONS Characteristics Symbol Min Typ Max Unit Resolution - - 10 - Bits Differential Llinearity Error DLE - - ±0.5 LSB Integral Linearity Error ILE - ±0.75 - LSB Offset Voltage Error(Top) EOT - ±2.0 - LSB Offset Voltage Error(Bottom) EOB - ±2.0 - LSB Conversion Rate fAD 1 - 250 KSPS Conversion Time tAD 100 - 40 us Master Clock Frequency fck 14 360 KHz Dynamic Supply Current Is - 1 2 mA Conversion Mode Power Dissipation Pd - 2.5 5 mW Conversion Mode Ron (Mux Switch) Ron - - 100 ohm Conditions NOTES 1. Converter Specifications (unless otherwise specified) AVDD25A=2.5V AVDD25D=2.5V AVDD25O=2.5V AVDD18D=1.8V AVSS25A=GND AVSS25D=GND AVSS25O=GND AVBBA=GND AVBBD=GND REFT=1.875V REFB=0.625V Ta=25ºC 2. TBD: To Be Determined TIMING SPECIFICATIONS Characteristics Symbol Min Typ Max Unit Clock High Time tpwh 130 - - ns Clock Low Time tpwl 130 - - ns BUSY Signal Output Delay tBD 10 ADC Output Delay tOD 10 SEC ASIC Conditions Output load capacitor = 5pF - 4 / 10 - ns Output load capacitor = 5pF MIXED ADC_PCI2010_CS2 8-BIT 250KSPS SAR ADC TIMING DIAGRAM Conversion Timing To be continued 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK SLEEP "LOW" EOC CONV tOD DO[7:0] DO(n)[7:0] To be continued 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 CLK SLEEP EOC 14 cycles CONV tOD tOD DO(n)[7:0] DO[7:0] 45 46 47 48 49 50 DO(n+1)[7:0] 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 CLK SLEEP EOC CONV tOD DO[7:0] SEC ASIC DO(n+3)[7:0] DO(n+2)[7:0] 5 / 10 MIXED ADC_PCI2010_CS2 8-BIT 250KSPS SAR ADC FUNCTIONAL DESCRIPTION The adc_pci2010_cs2 is a 8-bit analog-to-digital converter including successive approximation register, parallel output port and level shifter. The adc_pci2010_cs2 employs a successive approximation technique to determine the value of the analog input voltage. An array of binary-weighted capacitors subdivides the input value to perform the analog to digital conversion. The conversion of the adc_pci2010_cs2 is controlled by two signals, CONV and CLK. When CONV is taken "HIGH" on the rising edge of CLK, the adc_pci2010_cs2 is internally reset after next two clock cycles, the BUSY pin is driven "HIGH". The CONV pin should be held "HIGH" for at least one CLK cycle. The number of conversion cycles to generate an output data is 14 except the first conversion after the CONV pin is asserted. DO[7:0] are actual 8-bit output data with 2.5V power supply. SEC ASIC 6 / 10 MIXED ADC_PCI2010_CS2 8-BIT 250KSPS SAR ADC CORE EVALUATION GUIDE The reference voltages should be asserted externally through REFT and REFB pins AVDD25A AVSS25A AVBBA AVDD25D AVSS25D AVBBD AVDD25O AVSS25O MCO[2:0] INP[7:0] AVDD18D INN DO[7:0] adc_pci2010_cs2 REFT VCOM REFB SLEEP CLK EOC CONV DO[7:0] MUX HOST DSP/Microcontroller CORE (ADC Function Test & externally forced Digital Input) SEC ASIC 7 / 10 MIXED ADC_PCI2010_CS2 8-BIT 250KSPS SAR ADC USER GUIDE 1. Power Saving Mode When the overall system is in sleep, as SLEEP pin goes "HIGH", power consumption of the adc_pci2010_cs2 can fairly be reduced. 2. Analog Input Range The analog input range is concerned with the difference voltage, REFT - REFB. In case that the INN pin is connected with VCOM pin, the analog input range of INP pin is equal to 2*(REFT - REFB). 3. Conversion Control To operate the adc_pci2010_cs2 in conversion mode, the CONV pin should be set to "HIGH" for more than one clock cycle. 4. Digital Output Data DO[7:0] are actual 8-bit output data with 2.5V power supply. 5. Input MUX Control SEC ASIC MCO[2:0] Analog Input "000" INP[0] "001" INP[1] "010" INP[2] "011" INP[3] "100" INP[4] "101" INP[5] "110" INP[7] "111" INP[8] 8 / 10 MIXED ADC_PCI2010_CS2 8-BIT 250KSPS SAR ADC FEEDBACK REQUEST It should be quite helpful to ADC core development if you specify your system requirements on ADC in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Characteristic Min Typ Max Unit Analog Power Supply Voltage V Digital Power Supply Voltage V Resolution Remarks Bits Reference Input Voltage V Analog Input Voltage Vpp Number of Analog Input Channel Operating Temperature ºC Integral Linearity Error LSB Differential Linearity Error LSB Bottom Offset Voltage Error mV Top Offset Voltage Error mV Conversion Rate KSPS Conversion Time us Dynamic Supply Current mA Power Dissipation mW Power Dissipation at Power Down uW Digital Output Format (Provide detailed description & timing diagram) SEC ASIC 9 / 10 MIXED ADC_PCI2010_CS2 8-BIT 250KSPS SAR ADC FEEDBACK REQUEST (To be continued) 1. We want to know the detail of the analog input waveform because sample & hold amplifier is not included in the adc_pci2010_cs2. Which one is adequate for your analog input waveform among the a, b, and c below. If none of the three is adequate, please describe the analog input waveform to be used. If your analog input signal is a sinusoidal wave as c, please let me know what is the maximum frequency of the analog input signal ? It may be necessary to add a external sample & hold amplifier in any case. AIN a. (fixed DC input) b. (holding input) c. (sinusoidal wave) 2. Which one is suitable for your system between single ended input and differential input configurations and why ? 3. Please, mention on the internal/external pin configurations and draw the timing diagram as desired. 4. Freely list those functions you want to be implemented in ADC, if any. SEC ASIC 10 / 10 MIXED