HD74HCT563/HD74HCT573 Octal Transparent Latches (with 3-state outputs) ADE-205-559 (Z) 1st. Edition Sep. 2000 Description When the latch enable (LE) input is high, the Q outputs of HD74HCT563 will follow the inversion of the D inputs and the Q outputs of HD74HCT573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enabled returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Features • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (D to Q, Q) = 13 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Outputs Output Control Latch Enable Data HD74HCT563 HD74HCT573 L H H L H L H L H L L L X Q0 Q0 H X X Z Z HD74HCT563/HD74HCT573 Pin Arrangement HD74HCT563 Output Control 1 20 VCC OE 1D 2 2D 3 OE OE OE OE OE OE D OE D Q 13 7Q 12 8Q Q Latch 11 Enable GND 10 (Top view) 2 15 5Q 14 6Q Q 7D 8 8D 9 Q D D 17 3Q 16 4Q Q 5D 6 6D 7 Q D D 19 1Q 18 2Q Q D 3D 4 4D 5 Q D HD74HCT563/HD74HCT573 HD74HCT573 Output Control 1 20 VCC OE 1D 2 2D 3 D OE D OE D OE D OE D OE D 15 5Q 14 6Q Q 7D 8 8D 9 Q OE D 17 3Q 16 4Q Q 5D 6 6D 7 Q OE D 19 1Q 18 2Q Q 3D 4 4D 5 Q Q 13 7Q 12 8Q Q Latch 11 Enable GND 10 (Top view) 3 HD74HCT563/HD74HCT573 Block Diagram HD74HCT563 Enable C OC 4 1D D C Q C 1Q 2D D C Q C 2Q 3D D C Q C 3Q 4D D C Q C 4Q 5D D C Q C 5Q 6D D C Q C 6Q 7D D C Q C 7Q 8D D C Q C 8Q HD74HCT563/HD74HCT573 HD74HCT573 1D D C Q C 1Q 2D D C Q C 2Q 3D D C Q C 3Q 4D D C Q C 4Q 5D D C Q C 5Q 6D D C Q C 6Q 7D D C Q C 7Q 8D D C Q C 8Q Enable C OC Absolute Maximum Ratings Item Symbol Rating Unit Supply voltage range VCC –0.5 to +7.0 V Input voltage VIN –0.5 to VCC + 0.5 V Output voltage VOUT –0.5 to VCC + 0.5 V DC current drain per pin I OUT ±35 mA DC current drain per VCC, GND I CC, I GND ±75 mA DC input diode current I IK ±20 mA DC output diode current I OK ±20 mA Power dissipation per package PT 500 mW Storage temperature Tstg –65 to +150 °C 5 HD74HCT563/HD74HCT573 DC Characteristics Ta = –40 to +85°C Ta = 25°C Test Conditions Item Symbol Min Typ Max Min Max Unit VCC (V) Input voltage VIH 2.0 — — — V 4.5 to 5.5 VIL — — 0.8 — 0.8 V 4.5 to 5.5 VOH 4.4 — — 4.4 — V 4.5 Vin = VIH or VIL I OH = –20 µA 4.18 — — 4.13 — 4.5 I OH = –6 mA — — 0.1 — 0.1 — — 0.26 — 0.33 Output voltage VOL 2.0 V 4.5 Vin = VIH or VIL I OL = 20 µA 4.5 I OL = 6 mA Off-state output current I OZ — — ±0.5 — ±5.0 µA 5.5 Vin = VIH or VIL, Vout = VCC or GND Input current Iin — — ±0.1 — ±1.0 µA 5.5 Vin = VCC or GND Quiescent current I CC — — 4.0 — 40 µA 5.5 Vin = VCC or GND, Iout = 0 µA AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = –40 to +85°C Ta = 25°C Test Conditions Min Typ Max Min Max Unit VCC (V) Propagation delay t PLH — 13 22 — 28 ns 4.5 time t PHL — 13 22 — 28 t PLH — 14 23 — 29 t PHL — 14 23 — 29 Output enable t ZL — 14 30 — 38 time t ZH — 15 30 — 38 Output disable t LZ — 16 30 — 38 time t HZ — 17 30 — 38 Setup time t su 15 3 — 19 — ns 4.5 Hold time th 5 –1 — 5 — ns 4.5 Pulse width tw 16 4 — 20 — ns 4.5 Output rise/fall t TLH — 4 12 — 15 ns 4.5 time t THL — 4 12 — 15 Input capacitance Cin — 5 10 — 10 Item 6 Symbol Data to Q, Q 4.5 ns 4.5 4.5 ns 4.5 4.5 ns 4.5 4.5 4.5 pF — Enable G to Q, Q HD74HCT563/HD74HCT573 Package Dimensions Unit: mm 24.50 25.40 Max 1 7.00 Max 11 6.30 20 10 1.30 2.54 ± 0.25 0.48 ± 0.10 0.51 Min 1.27 Max 7.62 2.54 Min 5.08 Max 0.89 + 0.11 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Mass (reference value) DP-20N — Conforms 1.26 g Unit: mm 12.6 13 Max 11 1 10 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 20 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Mass (reference value) FP-20DA — Conforms 0.31 g 7 HD74HCT563/HD74HCT573 Unit: mm 12.8 13.2 Max 11 1 10 0.20 ± 0.10 0.935 Max *0.27 ± 0.05 0.25 ± 0.04 2.65 Max 7.50 20 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.25 10.40 +– 0.40 1.45 0° – 8° 0.57 0.70 +– 0.30 0.15 0.12 M Hitachi Code JEDEC EIAJ Mass (reference value) *Dimension including the plating thickness Base material dimension FP-20DB Conforms — 0.52 g Unit: mm 6.50 6.80 Max 11 1 10 4.40 20 0.65 *0.22+0.08 –0.07 0.20 ± 0.06 1.0 0.13 M 6.40 ± 0.20 *Dimension including the plating thickness Base material dimension 8 0.07 +0.03 –0.04 0.10 *0.17 ± 0.05 0.15 ± 0.04 1.10 Max 0.65 Max 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Mass (reference value) TTP-20DA — — 0.07 g HD74HCT563/HD74HCT573 Cautions 1. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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