PD -9.1353
IRFI530N
PRELIMINARY
HEXFET® Power MOSFET
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Advanced Process Technology
Isolated Package
High Voltage Isolation = 2.5KVRMS …
Sink to Lead Creepage Dist. = 4.8mm
Fully Avalanche Rated
VDSS = 100V
RDS(on) = 0.11Ω
ID = 11A
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design for which HEXFET Power MOSFETs are
well known, provides the designer with an extremely
efficient device for use in a wide variety of applications.
The TO-220 Fullpak eliminates the need for additional
insulating hardware in commercial-industrial applications.
The moulding compound used provides a high isolation
capability and a low thermal resistance between the tab
and external heatsink. This isolation is equivalent to using
a 100 micron mica barrier with standard TO-220 product.
The Fullpak is mounted to a heatsink using a single clip or
by a single screw fixing.
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current •†
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy ‚†
Avalanche Current•†
Repetitive Avalanche Current•†
Peak Diode Recovery dv/dt Ġ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw.
Units
11
7.8
60
33
0.22
±20
150
9.0
6.3
5.2
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case)
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθJA
Junction-to-Case
Junction-to-Ambient
Min.
Typ.
Max.
Units
––––
––––
––––
––––
4.5
65
°C/W
IRFI530N
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
V(BR)DSS
∆V(BR)DSS/∆TJ
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
LD
Internal Drain Inductance
LS
Internal Source Inductance
Ciss
Coss
Crss
C
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Drain to Sink Capacitance
IGSS
Min. Typ. Max. Units
Conditions
100 ––– –––
V
VGS = 0V, ID = 250µA
––– 0.12 ––– V/°C Reference to 25°C, ID = 1mA†
––– ––– 0.11
Ω
VGS = 10V, ID = 6.6A „
2.0
––– 4.0
V
VDS = VGS, ID = 250µA
6.4
––– –––
S
VDS = 50V, ID = 9.0A†
––– ––– 25
VDS = 100V, VGS = 0V
µA
––– ––– 250
VDS = 80V, VGS = 0V, TJ = 150°C
––– ––– 100
VGS = 20V
nA
––– ––– -100
VGS = -20V
––– ––– 44
ID = 9.0A
––– ––– 6.2
nC VDS = 80V
––– ––– 21
VGS = 10V, See Fig. 6 and 13 „†
–––
6.4 –––
VDD = 50V
–––
27 –––
ID = 9.0A
ns
–––
37 –––
RG = 12Ω
–––
25 –––
RD = 5.5Ω, See Fig. 10 „†
Between lead,
–––
4.5 –––
6mm (0.25in.)
nH
from package
–––
–––
––– 7.5 –––
and center of die contact
––– 640 –––
VGS = 0V
––– 160 –––
VDS = 25V
pF
–––
88 –––
ƒ = 1.0MHz, See Fig. 5†
–––
12 –––
ƒ = 1.0MHz
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) •†
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Min. Typ. Max. Units
–––
–––
11
–––
–––
60
–––
–––
–––
–––
130
650
1.3
190
970
A
V
ns
nC
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 6.6A, VGS = 0V „
TJ = 25°C, IF = 9.0A
di/dt = 100A/µs „†
Notes:
• Repetitive rating; pulse width limited by
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. ( See fig. 11 )
‚ VDD = 15V, starting TJ = 25°C, L = 3.1mH
… t=60s, ƒ=60Hz
RG = 25Ω, IAS = 9.0A. (See Figure 12)
ƒ ISD ≤ 9.0A, di/dt ≤ 520A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
† Uses IRF530N data and test conditions
IRFI530N
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
I , Drain-to-Source Current (A)
D
I , Drain-to-Source Current (A)
D
10
4.5V
20µs PULSE WIDTH
TJ = 25°C
1
0.1
1
10
A
10
4.5V
3.0
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
10
V DS= 50V
20µs PULSE WIDTH
6
7
8
9
10
A
100
Fig 2. Typical Output Characteristics,
TJ = 175oC
100
5
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics,
TJ = 25oC
1
20µs PULSE WIDTH
TJ = 175°C
1
0.1
100
VDS , Drain-to-Source Voltage (V)
4
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
TOP
10
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
A
I D = 15A
2.5
2.0
1.5
1.0
0.5
VGS = 10V
0.0
-60 -40 -20
0
20
40
60
A
80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
IRFI530N
1200
VGS , Gate-to-Source Voltage (V)
1000
C, Capacitance (pF)
20
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
C oss = C ds + C gd
Ciss
800
600
Coss
400
Crss
200
0
A
1
10
I D = 9.0A
V DS = 80V
V DS = 50V
V DS = 20V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
100
0
5
VDS , Drain-to-Source Voltage (V)
15
20
25
30
35
40
A
45
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
1000
OPERATION IN THIS AREA LIMITED
BY R DS(on)
ID , Drain Current (A)
ISD , Reverse Drain Current (A)
10
TJ = 175°C
10
TJ = 25°C
VGS = 0V
1
0.4
0.6
0.8
1.0
1.2
1.4
VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
A
1.6
100
10µs
100µs
10
1ms
T C = 25°C
T J = 175°C
Single Pulse
1
1
10ms
10
100
A
1000
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
IRFI530N
RD
VDS
12
VGS
ID, Drain Current (Amps)
D.U.T.
RG
10
VDD
10V
8
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
6
Fig 10a. Switching Time Test Circuit
4
2
A
0
25
50
75
100
125
150
175
TC , Case Temperature (°C)
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.1
PD M
0.02
0.01
t
0.01
0.00001
1
t2
SINGLE PULSE
(THERMAL RESPONSE)
N otes :
1 . D u ty fac tor D = t
1
/t
2
2. P e ak TJ = P D M x Z th J C + T C
0.0001
0.001
0.01
0.1
1
t 1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
A
10
10 V
Fig 12a. Unclamped Inductive Test Circuit
EAS , Single Pulse Avalanche Energy (mJ)
IRFI530N
350
TOP
300
BOTTOM
ID
3.7A
6.4A
9.0A
250
200
150
100
50
0
VDD = 25V
25
50
A
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
10 V
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
IRFI530N
Peak Diode Recovery dv/dt Test Circuit
D.U.T
ƒ
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
„
•
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
*
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
IRFI530N
Package Outline — TO-220 Full-Pak
Dimensions are shown in millimeters (inches)
10.60 (.417)
10.40 (.409)
ø
3.40 (.133)
3.10 (.123)
4.80 (.189)
4.60 (.181)
-A3.70 (.145)
3.20 (.126)
16.00 (.630)
15.80 (.622)
2.80 (.110)
2.60 (.102)
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
7.10 (.280)
6.70 (.263)
1.15 (.045)
MIN.
NOTES:
1 DIMENSIONING & TOLERANCING
PER ANSI Y14.5M, 1982
1
2
3
2 CONTROLLING DIMENSION: INCH.
3.30 (.130)
3.10 (.122)
-B-
13.70 (.540)
13.50 (.530)
C
A
1.40 (.055)
3X
1.05 (.042)
0.90 (.035)
3X 0.70 (.028)
0.25 (.010)
3X
M A M
B
2.54 (.100)
2X
0.48 (.019)
0.44 (.017)
2.85 (.112)
2.65 (.104)
D
B
MINIMUM CREEPAGE
DISTANCE BETWEEN
A-B-C-D = 4.80 (.189)
Part Marking Information
EXAMPLE : THIS IS AN IRFI840G
WITH ASSEMBLY
LOT CODE E401
A
INTERNATIONAL
RECTIFIER
IRFI840G
LOGO
PART NUMBER
E401 9245
ASSEMBLY
LOT CODE
DATE CODE
(YYWW)
YY = YEAR
WW = WEEK
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http://www.irf.com/
Data and specifications subject to change without notice.
4/96