AD ADG1404YRUZ

Preliminary Technical Data
2Ω Max On Resistance,
±15 V/12 V/±5 V 4:1 iCMOS™ Multiplexer
ADG1404
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2Ω Max On Resistance
0.5Ω Max On Resistance Flatness
200mA Continuous current
33 V supply range
Fully specified at +12 V, ±15 V, ±5 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
14-lead TSSOP and 16-lead LFCSP
ADG1404
S1
S2
D
S3
S4
1 OF 4
DECODER
A0
APPLICATIONS
A1
EN
Figure 1.
Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems
Relay Replacement
GENERAL DESCRIPTION
The ADG1404 is a complementary metal-oxide semiconductor
(CMOS) analog multiplexer, comprising four single channels
designed on an iCMOS process. iCMOS (industrial CMOS) is a
modular manufacturing process that combines high voltage
CMOS and bipolar technologies. It enables the development of
a wide range of high performance analog ICs capable of 33 V
operation in a footprint that no previous generation of high
voltage parts has been able to achieve. Unlike analog ICs using
conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased
performance, dramatically lower power consumption, and
reduced package size.
The ADG1404 switches one of four inputs to a common output,
D, as determined by the 3-bit binary address lines, A0, A1, and
EN. Logic 0 on the EN pin disables the device. Each switch
conducts equally well in both directions when on and has an
input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches
exhibit break-before-make switching action. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
1.
2Ω Max On Resistance over temperature.
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals.
2.
Minimum distortion
3.
3 V logic-compatible digital inputs:
VIH = 2.0 V, VIL = 0.8 V
No VL logic power supply required.
Ultralow power dissipation: <0.03 µW.
14-lead TSSOP and 16-lead 4 mm × 4 mm LFCSP package.
iCMOS construction ensures ultralow power dissipation,
making the parts ideally suited for portable and batterypowered instruments.
PRODUCT HIGHLIGHTS
4.
5.
6.
Rev.PrB
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infringements of patents or other rights of third parties that may result from its use.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2007 Analog Devices, Inc. All rights reserved.
ADG1404
Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Pin Configurations and Function Descriptions ............................8
Dual Supply ................................................................................... 3
Terminology .......................................................................................9
Single Supply ................................................................................. 5
Typical Performance Characteristics ........................................... 10
Absolute Maximum Ratings............................................................ 7
Test Circuits..................................................................................... 13
Truth Table .................................................................................... 8
Outline Dimensions ....................................................................... 15
ESD Caution.................................................................................. 7
Ordering Guide .......................................................................... 15
REVISION HISTORY
Rev. PrB | Page 2 of 17
Preliminary Technical Data
ADG1404
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V± 10%, GND = 0 V, unless otherwise noted.
Table 1.
25°C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
−40°C to +
85°C
−40°C to +
125°C
VDD to VSS
1.5
2
On Resistance Match Between
Channels (∆RON)
0.1
On Resistance Flatness (RFLAT(ON))
0.1
Ω max
Ω typ
Ω max
0.5
0.5
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
±0.01
±2.5
Drain Off Leakage, ID (Off)
±0.5
±0.01
±0.5
±0.04
±1
±2.5
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINLor INH
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
VS = −5 V, 0 V, +5 V; IS = −10 mA
VDD = +16.5 V, VSS = −16.5 V
±2.5
VS = ±10 V, Vs = ∓10 V; Figure 22
±5
nA max
nA typ
VS = ±10 V, Vs = ∓10 V ; Figure 22
±5
nA max
nA typ
nA max
VS = VD = ±10 V; Figure 23
V min
V max
µA typ
µA max
pF typ
VIN = VINL or VINH
±5
2.0
0.8
0.005
2.5
120
150
70
85
90
110
25
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
Insertion Loss
CS (Off)
50
50
60
0.01
50
0.17
35
CD (Off)
100
CD, CS (On)
150
POWER REQUIREMENTS
IDD
VS = ±10 V, IS = −10 mA; Figure 21
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −10 mA
nA typ
±0.5
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANS
V
Ω typ
Ω max
Ω typ
200
200
110
110
155
155
10
10
0.001
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
dB typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
µA typ
Rev. PrB | Page 3 of 17
RL = 300 Ω, CL = 35 pF
VS = +10 V; Figure 24
RL = 300 Ω, CL = 35 pF
VS = +10 V; Figure 24
RL = 300 Ω, CL = 35 pF
VS = +10 V; Figure 24
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; Figure 25
VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28
RL = 110 Ω, 5 V rms, f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF; Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 29
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
ADG1404
Preliminary Technical Data
25°C
IDD
−40°C to +
85°C
−40°C to +
125°C
1
150
300
ISS
0.001
1
VDD/VSS
1
±4.5/±16.5
Guaranteed by design, not subject to production test.
Rev. PrB | Page 4 of 17
µA max
µA typ
µA max
µA typ
µA max
V
min/max
Digital inputs = 5 V
Digital inputs = 0 V, 5V or VDD
Gnd = 0V
Preliminary Technical Data
ADG1404
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
25°C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
−40°C to
+85°C
−40°C to
+125°C
0 V to VDD
2.5
3
0.1
4
0.1
±0.01
±0.5
±0.01
±0.5
±0.04
±1
±2.5
±5
±2.5
±5
±2.5
±5
2.0
0.8
0.001
±0.5
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANS
2.5
Break-Before-Make Time Delay, tD
150
190
95
120
100
125
50
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off)
50
50
60
50
35
CD (Off)
100
CD, CS (On)
150
tON (EN)
tOFF (EN)
265
170
170
10
POWER REQUIREMENTS
IDD
0.001
1
IDD
150
300
VDD
1
5/16.5
Guaranteed by design, not subject to production test.
Rev. PrB | Page 5 of 17
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
µA typ
µA max
µA typ
µA max
V
min/max
VS = 10 V, IS = −10 mA; Figure 21
VDD = +10.8 V, VSS = 0 V
VS = 10 V, IS = −10 mA
VS = 3 V, 6 V, 9 V; IS = −10 mA
VDD = 13.2 V
VS = 1 V/10 V, VD = 10 V/1 V; Figure 22
VS = 1 V/10 V, VD = 10 V/1 V; Figure 22
VS = VD = 1 V or 10 V; Figure 23
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 24
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 24
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 24
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; Figure 25
VS = 6 V, RS = 0 Ω, CL = 1 nF; Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28
RL = 50 Ω, CL = 5 pF; Figure 29
f = 1 MHz; VS = 6V
f = 1 MHz; VS = 6V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Gnd = 0V, Vss = 0V
ADG1404
Preliminary Technical Data
DUAL SUPPLY
VDD = 5 V ± 10%, VSS = -5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 3.
25°C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (∆RON)
−40°C to
+85°C
−40°C to
+125°C
Unit
Test Conditions/Comments
4
5
0.1
V
Ω typ
Ω max
Ω typ
VS = ±3.3V, IS = −10 mA; See figure x
VDD = +4.5 V, VSS = −4.5 V
VS = ±3.3 V , IS = −10 mA
0 V to VDD
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.1
Ω max
Ω typ
±0.01
nA typ
VS = ±4.5 V, VD = ∓4.5 V; See figure x
±2.5
±5
Drain Off Leakage, ID (Off)
±0.5
±0.01
nA max
nA typ
VS = ±4.5V, VD = ∓4.5 V; See figure x
±0.5
±0.04
±1
±2.5
±5
VS = VD = ±4.5V; See figure x
±5
±5
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
VIN = VINL or VINH
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINLor IINH
2.0
0.8
0.001
±0.5
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANS
3
Break-Before-Make Time Delay, tD
150
190
95
120
100
125
50
Charge Injection
Off Isolation
50
50
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
Channel-to-Channel Crosstalk
60
dB typ
−3 dB Bandwidth
CS (Off)
50
35
CD (Off)
35
CD, CS (On)
150
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
POWER REQUIREMENTS
IDD
0.001
tON (EN)
tOFF (EN)
265
170
170
10
1
VDD/VSS
±4.5/±16.5
Rev. PrB | Page 6 of 17
µA typ
µA max
V
min/max
VS = −3 V/0 V/+3 V; IS = −10 mA
VDD = +5.5 V, VSS = −5.5 V
RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 24
RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 24
RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 24
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; See figure x
VS = 0 V, RS = 0 Ω, CL = 1 nF; See figure x
RL = 50 Ω, CL = 5 pF, f = 1 MHz; See figure
x
RL = 50 Ω, CL = 5 pF, f = 1 MHz; See figure
x
RL = 50 Ω, CL = 5 pF; See figure x
Vs = 0V, f = 1 MHz
Vs = 0V, f = 1 MHz
Vs = 0V, f = 1 MHz
Vs = 0V, f = 1 MHz
Vs = 0V, f = 1 MHz
Vs = 0V, f = 1 MHz
VDD = 5.5 V , Vss = -5.5V
Digital inputs = 0 V, 5V or VDD
Gnd = 0V
Preliminary Technical Data
ADG1404
ABSOLUTE MAXIMUM RATINGS
1
Guaranteed by design, not subject to production test.
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs
Peak Current, S or D
Continuous Current, S or D
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
16-Lead TSSOP, θJA Thermal
Impedance
16-Lead LFCSP, θJA Thermal
Impedance
Reflow Soldering Peak
Temperature, Pb free
1
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
300 mA (pulsed at 1 ms, 10%
duty cycle max)
200 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
−40°C to +125°C
−65°C to +150°C
150°C
150.4°C/W
72.7°C/W
260°C
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 7 of 17
ADG1404
Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
EN A0 A1 NC
16 15 14 13
A0
1
14 A1
EN
2
13 GND
VSS
3
12 VDD
S1
4
S2
5
D
6
9
NC
NC
7
8
NC
ADG1204
TOP VIEW
Vss 1
NC 2
S1 3
11 S3
ADG1404
TOP VIEW
(Not to Scale)
S2 4
12 Gnd
11 Vdd
10 S3
9 S4
10 S4
04779-0-002
NC = NO CONNECT
5 6
7
8
NC D NC NC
EXPOSED PAD TIED TO SUBSTRATE, Vss
NC = NO CONNECT
Figure 3. LFCSP Pin Configuration
Figure 2. TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
1
15
2
16
Mnemonic
A0
EN
3
4
5
6
7 to 9
VSS
S1
S2
D
NC
Description
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.
Most Negative Power Supply Potential.
Source Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Drain Terminal. Can be an input or an output.
No Connection.
S4
S3
VDD
GND
A1
Source Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
10
11
12
13
14
1
3
4
6
2,5,7,8,
13
9
10
11
12
14
TRUTH TABLE
Table 6.
EN
0
1
1
1
1
A1
X
0
0
1
1
A0
X
0
1
0
1
S1
Off
On
Off
Off
Off
Rev. PrB | Page 8 of 17
S2
Off
Off
On
Off
Off
S3
Off
Off
Off
On
Off
S4
Off
Off
Off
Off
On
Preliminary Technical Data
ADG1404
TERMINOLOGY
IDD
The positive supply current.
CD, CS (On)
The on switch capacitance, which is measured with reference to
ground.
ISS
The negative supply current.
CIN
The digital input capacitance.
VD (VS)
The analog voltage on Terminals D and S.
tON (EN)
The delay between applying the digital control input and the
output switching on. See Figure 24, Test Circuit 4.
RON
The ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
IS (Off)
The source leakage current with the switch off.
ID (Off)
The drain leakage current with the switch off.
tOFF (EN)
The delay between applying the digital control input and the
output switching off.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
ID, IS (On)
The channel leakage current with the switch on.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
VINL
The maximum input voltage for Logic 0.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
VINH
The minimum input voltage for Logic 1.
On Response
The frequency response of the on switch.
IINL (IINH)
The input current of the digital input.
Insertion Loss
The loss due to the on resistance of the switch.
CS (Off)
The off switch source capacitance, which is measured with
reference to ground.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
CD (Off)
The off switch drain capacitance, which is measured with
reference to ground.
tTRANS
The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.
Rev. PrB | Page 9 of 17
ADG1404
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. On Resistance as a Function of VD (VS) for Single Supply
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
Figure 8. Leakage Currents as a Function of Temperature for Dual Supply
Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
Figure 9. Leakage Currents as a Function of Temperature for Single Supply
Rev. PrB | Page 10 of 17
Preliminary Technical Data
ADG1404
Figure 10. Logic Threshold Voltage vs Supply Voltage
Figure 13. Transition Times vs. Temperature
Figure 11. IDD vs. Logic Level
Figure 14. Off Isolation vs. Frequency
Figure 12. Charge Injection vs. Source Voltage
Figure 15. Crosstalk vs. Frequency
Rev. PrB | Page 11 of 17
ADG1404
Preliminary Technical Data
Figure 16. On Response vs. Frequency
Figure 19. On Capacitance vs. Source Voltage
Figure 17. THD + N vs. Frequency
Figure 20. Capacitance vs. Source Voltage for Single Supply
Figure 18. Off Capacitance vs. Source Voltage
Rev. PrB | Page 12 of 17
Preliminary Technical Data
ADG1404
TEST CIRCUITS
V
VD
VDD VSS
A
VD
Figure 23. Test Circuit 3—On Leakage
0.1µF
ADDRESS
DRIVE (VIN)
S1
S2
S3
S4
A1
A0
+2.4V
D
NC = No Connect
Figure 22. Test Circuit 2—Off Leakage
VDD VSS
VS
S
NC
A
VS
Figure 21. Test Circuit 1—On Resistance
0.1µF
D
EN
VS1
VS4
3V
50%
90%
VOUT
D
50%
0V
90%
VOUT
GND
RL
50Ω
tTRANSITION
CL
35pF
tTRANSITION
04779-0-023
VS
04779-0-020
IDS
ID (ON)
ID (OFF)
S
A
04779-0-022
D
04779-0-021
IS (OFF)
S
Figure 24. Test Circuit 4—Address to Output Switching Times
VDD VSS
0.1µF
VDD VSS
S1
S2
S3
S4
A1
VS
50Ω
+2.4V
A0
EN
ADDRESS
DRIVE (VIN)
VS1
D
VOUT
GND
RL
50Ω
3V
0V
VOUT
CL
35pF
80%
80%
04779-0-024
0.1µF
tBBM
Figure 25. Test Circuit 5—Break-Before-Make Time
VDD VSS
0.1µF
ENABLE
DRIVE (VIN)
VDD VSS
S1
S2
S3
S4
A1
A0
VS
3V
50%
V0
OUTPUT
EN
VS
D
GND
50Ω
VOUT
RL
50Ω
0.9V0
0.9V0
0V
CL
35pF
Delay.
Figure 26. Test Circuit 6—Enable-to-Output Switching Delay
Rev. PrB | Page 13 of 17
50%
0V
tON(EN)
tOFF(EN)
04779-0-025
0.1µF
ADG1404
Preliminary Technical Data
VDD
VSS
VDD
VSS
S
D
VOUT
RS
∆VOUT
QINJ = CL × ∆VOUT
VOUT
VIN
CL
1nF
VS
SW OFF
SW OFF
SW ON
DECODER
GND
SW ON
SW OFF
04779-0-026
VIN
A1 A2
SW OFF
EN
Figure 27. Test Circuit 7— Charge Injection
VDD
VSS
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
NETWORK
ANALYZER
VSS
S
VOUT
VSS
VDD
VSS
0.1µF
S1
RL
50Ω
50Ω
50Ω
VDD
0.1µF
D
VS
S2
R
50Ω
D
VS
GND
OFF ISOLATION = 20 LOG
VOUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
Figure 28. Test Circuit 8—Off Isolation
VDD
04779-0-029
GND
VOUT
04779-0-027
RL
50Ω
VOUT
VS
Figure 30. Test Circuit 10—Channel-to-Channel Crosstalk
VSS
0.1µF
0.1µF
VDD
VDD
VSS
NETWORK
ANALYZER
VSS
0.1µF
0.1µF
AUDIO PRECISION
S
VDD
50Ω
VSS
RS
VS
S
RL
50Ω
GND
IN
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
04779-0-028
VIN
INSERTION LOSS = 20 LOG
VS
V p-p
D
Figure 29. Test Circuit 9—Bandwidth
RL
600Ω
VOUT
GND
Figure 31. Test Circuit 11—THD + Noise
Rev. PrB | Page 14 of 17
04779-0-030
D
Preliminary Technical Data
ADG1404
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65
BSC
1.05
1.00
0.80
1.20
MAX
0.15
0.05
0.30
0.19
0.20
0.09
SEATING
COPLANARITY
PLANE
0.10
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 32. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimension shown in millimeters
4.00
BSC SQ
PIN 1
INDICATOR
0.65 BSC
TOP
VIEW
12° MAX
1.00
0.85
0.80
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
13
12
16
1
EXPOSED
PAD
3.75
BSC SQ
0.75
0.60
0.50
(BOTTOM VIEW)
2.25
2.10 SQ
1.95
4
9
8
5
0.25 MIN
1.95 BSC
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 33. 16-Lead Lead Frame Chip Scale Package [VQ_LFCSP]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG1404YRUZ1
ADG1404YRUZ-REEL1
ADG1404YRUZ-REEL71
ADG1404YCPZ-500RL71
ADG1404YCPZ-REEL71
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (VQ_LFCSP)
Lead Frame Chip Scale Package (VQ_LFCSP)
Z = Pb-free part.
Rev. PrB | Page 15 of 17
Package Option
RU-14
RU-14
RU-14
CP-16-4
CP-16-4
ADG1404
Preliminary Technical Data
NOTES
Rev. PrB | Page 16 of 17
Preliminary Technical Data
ADG1404
NOTES
© 2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06841-0-5/07(PrB)
Rev. PrB | Page 17 of 17